1 /*- 2 * Copyright (c) 2018 Emmanuel Vadot <manu@freebsd.org> 3 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 /* 31 * X-Powers AXP803/813/818 PMU for Allwinner SoCs 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/eventhandler.h> 40 #include <sys/bus.h> 41 #include <sys/rman.h> 42 #include <sys/kernel.h> 43 #include <sys/reboot.h> 44 #include <sys/gpio.h> 45 #include <sys/module.h> 46 #include <machine/bus.h> 47 48 #include <dev/iicbus/iicbus.h> 49 #include <dev/iicbus/iiconf.h> 50 51 #include <dev/gpio/gpiobusvar.h> 52 53 #include <dev/ofw/ofw_bus.h> 54 #include <dev/ofw/ofw_bus_subr.h> 55 56 #include <dev/extres/regulator/regulator.h> 57 58 #include "gpio_if.h" 59 #include "iicbus_if.h" 60 #include "regdev_if.h" 61 62 MALLOC_DEFINE(M_AXP8XX_REG, "AXP8xx regulator", "AXP8xx power regulator"); 63 64 #define AXP_POWERSRC 0x00 65 #define AXP_POWERSRC_ACIN (1 << 7) 66 #define AXP_POWERSRC_VBUS (1 << 5) 67 #define AXP_POWERSRC_VBAT (1 << 3) 68 #define AXP_POWERSRC_CHARING (1 << 2) 69 #define AXP_POWERSRC_SHORTED (1 << 1) 70 #define AXP_POWERSRC_STARTUP (1 << 0) 71 #define AXP_ICTYPE 0x03 72 #define AXP_POWERCTL1 0x10 73 #define AXP_POWERCTL1_DCDC7 (1 << 6) /* AXP813/818 only */ 74 #define AXP_POWERCTL1_DCDC6 (1 << 5) 75 #define AXP_POWERCTL1_DCDC5 (1 << 4) 76 #define AXP_POWERCTL1_DCDC4 (1 << 3) 77 #define AXP_POWERCTL1_DCDC3 (1 << 2) 78 #define AXP_POWERCTL1_DCDC2 (1 << 1) 79 #define AXP_POWERCTL1_DCDC1 (1 << 0) 80 #define AXP_POWERCTL2 0x12 81 #define AXP_POWERCTL2_DC1SW (1 << 7) /* AXP803 only */ 82 #define AXP_POWERCTL2_DLDO4 (1 << 6) 83 #define AXP_POWERCTL2_DLDO3 (1 << 5) 84 #define AXP_POWERCTL2_DLDO2 (1 << 4) 85 #define AXP_POWERCTL2_DLDO1 (1 << 3) 86 #define AXP_POWERCTL2_ELDO3 (1 << 2) 87 #define AXP_POWERCTL2_ELDO2 (1 << 1) 88 #define AXP_POWERCTL2_ELDO1 (1 << 0) 89 #define AXP_POWERCTL3 0x13 90 #define AXP_POWERCTL3_ALDO3 (1 << 7) 91 #define AXP_POWERCTL3_ALDO2 (1 << 6) 92 #define AXP_POWERCTL3_ALDO1 (1 << 5) 93 #define AXP_POWERCTL3_FLDO3 (1 << 4) /* AXP813/818 only */ 94 #define AXP_POWERCTL3_FLDO2 (1 << 3) 95 #define AXP_POWERCTL3_FLDO1 (1 << 2) 96 #define AXP_VOLTCTL_DLDO1 0x15 97 #define AXP_VOLTCTL_DLDO2 0x16 98 #define AXP_VOLTCTL_DLDO3 0x17 99 #define AXP_VOLTCTL_DLDO4 0x18 100 #define AXP_VOLTCTL_ELDO1 0x19 101 #define AXP_VOLTCTL_ELDO2 0x1A 102 #define AXP_VOLTCTL_ELDO3 0x1B 103 #define AXP_VOLTCTL_FLDO1 0x1C 104 #define AXP_VOLTCTL_FLDO2 0x1D 105 #define AXP_VOLTCTL_DCDC1 0x20 106 #define AXP_VOLTCTL_DCDC2 0x21 107 #define AXP_VOLTCTL_DCDC3 0x22 108 #define AXP_VOLTCTL_DCDC4 0x23 109 #define AXP_VOLTCTL_DCDC5 0x24 110 #define AXP_VOLTCTL_DCDC6 0x25 111 #define AXP_VOLTCTL_DCDC7 0x26 112 #define AXP_VOLTCTL_ALDO1 0x28 113 #define AXP_VOLTCTL_ALDO2 0x29 114 #define AXP_VOLTCTL_ALDO3 0x2A 115 #define AXP_VOLTCTL_STATUS (1 << 7) 116 #define AXP_VOLTCTL_MASK 0x7f 117 #define AXP_POWERBAT 0x32 118 #define AXP_POWERBAT_SHUTDOWN (1 << 7) 119 #define AXP_IRQEN1 0x40 120 #define AXP_IRQEN2 0x41 121 #define AXP_IRQEN3 0x42 122 #define AXP_IRQEN4 0x43 123 #define AXP_IRQEN5 0x44 124 #define AXP_IRQEN5_POKSIRQ (1 << 4) 125 #define AXP_IRQEN6 0x45 126 #define AXP_IRQSTAT5 0x4c 127 #define AXP_IRQSTAT5_POKSIRQ (1 << 4) 128 #define AXP_GPIO0_CTRL 0x90 129 #define AXP_GPIO0LDO_CTRL 0x91 130 #define AXP_GPIO1_CTRL 0x92 131 #define AXP_GPIO1LDO_CTRL 0x93 132 #define AXP_GPIO_FUNC (0x7 << 0) 133 #define AXP_GPIO_FUNC_SHIFT 0 134 #define AXP_GPIO_FUNC_DRVLO 0 135 #define AXP_GPIO_FUNC_DRVHI 1 136 #define AXP_GPIO_FUNC_INPUT 2 137 #define AXP_GPIO_FUNC_LDO_ON 3 138 #define AXP_GPIO_FUNC_LDO_OFF 4 139 #define AXP_GPIO_SIGBIT 0x94 140 #define AXP_GPIO_PD 0x97 141 142 static const struct { 143 const char *name; 144 uint8_t ctrl_reg; 145 } axp8xx_pins[] = { 146 { "GPIO0", AXP_GPIO0_CTRL }, 147 { "GPIO1", AXP_GPIO1_CTRL }, 148 }; 149 150 enum AXP8XX_TYPE { 151 AXP803 = 1, 152 AXP813, 153 }; 154 155 static struct ofw_compat_data compat_data[] = { 156 { "x-powers,axp803", AXP803 }, 157 { "x-powers,axp813", AXP813 }, 158 { "x-powers,axp818", AXP813 }, 159 { NULL, 0 } 160 }; 161 162 static struct resource_spec axp8xx_spec[] = { 163 { SYS_RES_IRQ, 0, RF_ACTIVE }, 164 { -1, 0 } 165 }; 166 167 struct axp8xx_regdef { 168 intptr_t id; 169 char *name; 170 char *supply_name; 171 uint8_t enable_reg; 172 uint8_t enable_mask; 173 uint8_t enable_value; 174 uint8_t disable_value; 175 uint8_t voltage_reg; 176 int voltage_min; 177 int voltage_max; 178 int voltage_step1; 179 int voltage_nstep1; 180 int voltage_step2; 181 int voltage_nstep2; 182 }; 183 184 enum axp8xx_reg_id { 185 AXP8XX_REG_ID_DCDC1 = 100, 186 AXP8XX_REG_ID_DCDC2, 187 AXP8XX_REG_ID_DCDC3, 188 AXP8XX_REG_ID_DCDC4, 189 AXP8XX_REG_ID_DCDC5, 190 AXP8XX_REG_ID_DCDC6, 191 AXP813_REG_ID_DCDC7, 192 AXP803_REG_ID_DC1SW, 193 AXP8XX_REG_ID_DLDO1, 194 AXP8XX_REG_ID_DLDO2, 195 AXP8XX_REG_ID_DLDO3, 196 AXP8XX_REG_ID_DLDO4, 197 AXP8XX_REG_ID_ELDO1, 198 AXP8XX_REG_ID_ELDO2, 199 AXP8XX_REG_ID_ELDO3, 200 AXP8XX_REG_ID_ALDO1, 201 AXP8XX_REG_ID_ALDO2, 202 AXP8XX_REG_ID_ALDO3, 203 AXP8XX_REG_ID_FLDO1, 204 AXP8XX_REG_ID_FLDO2, 205 AXP813_REG_ID_FLDO3, 206 AXP8XX_REG_ID_GPIO0_LDO, 207 AXP8XX_REG_ID_GPIO1_LDO, 208 }; 209 210 static struct axp8xx_regdef axp803_regdefs[] = { 211 { 212 .id = AXP803_REG_ID_DC1SW, 213 .name = "dc1sw", 214 .enable_reg = AXP_POWERCTL2, 215 .enable_mask = (uint8_t) AXP_POWERCTL2_DC1SW, 216 .enable_value = AXP_POWERCTL2_DC1SW, 217 }, 218 }; 219 220 static struct axp8xx_regdef axp813_regdefs[] = { 221 { 222 .id = AXP813_REG_ID_DCDC7, 223 .name = "dcdc7", 224 .enable_reg = AXP_POWERCTL1, 225 .enable_mask = (uint8_t) AXP_POWERCTL1_DCDC7, 226 .enable_value = AXP_POWERCTL1_DCDC7, 227 .voltage_reg = AXP_VOLTCTL_DCDC7, 228 .voltage_min = 600, 229 .voltage_max = 1520, 230 .voltage_step1 = 10, 231 .voltage_nstep1 = 50, 232 .voltage_step2 = 20, 233 .voltage_nstep2 = 21, 234 }, 235 }; 236 237 static struct axp8xx_regdef axp8xx_common_regdefs[] = { 238 { 239 .id = AXP8XX_REG_ID_DCDC1, 240 .name = "dcdc1", 241 .enable_reg = AXP_POWERCTL1, 242 .enable_mask = (uint8_t) AXP_POWERCTL1_DCDC1, 243 .enable_value = AXP_POWERCTL1_DCDC1, 244 .voltage_reg = AXP_VOLTCTL_DCDC1, 245 .voltage_min = 1600, 246 .voltage_max = 3400, 247 .voltage_step1 = 100, 248 .voltage_nstep1 = 18, 249 }, 250 { 251 .id = AXP8XX_REG_ID_DCDC2, 252 .name = "dcdc2", 253 .enable_reg = AXP_POWERCTL1, 254 .enable_mask = (uint8_t) AXP_POWERCTL1_DCDC2, 255 .enable_value = AXP_POWERCTL1_DCDC2, 256 .voltage_reg = AXP_VOLTCTL_DCDC2, 257 .voltage_min = 500, 258 .voltage_max = 1300, 259 .voltage_step1 = 10, 260 .voltage_nstep1 = 70, 261 .voltage_step2 = 20, 262 .voltage_nstep2 = 5, 263 }, 264 { 265 .id = AXP8XX_REG_ID_DCDC3, 266 .name = "dcdc3", 267 .enable_reg = AXP_POWERCTL1, 268 .enable_mask = (uint8_t) AXP_POWERCTL1_DCDC3, 269 .enable_value = AXP_POWERCTL1_DCDC3, 270 .voltage_reg = AXP_VOLTCTL_DCDC3, 271 .voltage_min = 500, 272 .voltage_max = 1300, 273 .voltage_step1 = 10, 274 .voltage_nstep1 = 70, 275 .voltage_step2 = 20, 276 .voltage_nstep2 = 5, 277 }, 278 { 279 .id = AXP8XX_REG_ID_DCDC4, 280 .name = "dcdc4", 281 .enable_reg = AXP_POWERCTL1, 282 .enable_mask = (uint8_t) AXP_POWERCTL1_DCDC4, 283 .enable_value = AXP_POWERCTL1_DCDC4, 284 .voltage_reg = AXP_VOLTCTL_DCDC4, 285 .voltage_min = 500, 286 .voltage_max = 1300, 287 .voltage_step1 = 10, 288 .voltage_nstep1 = 70, 289 .voltage_step2 = 20, 290 .voltage_nstep2 = 5, 291 }, 292 { 293 .id = AXP8XX_REG_ID_DCDC5, 294 .name = "dcdc5", 295 .enable_reg = AXP_POWERCTL1, 296 .enable_mask = (uint8_t) AXP_POWERCTL1_DCDC5, 297 .enable_value = AXP_POWERCTL1_DCDC5, 298 .voltage_reg = AXP_VOLTCTL_DCDC5, 299 .voltage_min = 800, 300 .voltage_max = 1840, 301 .voltage_step1 = 10, 302 .voltage_nstep1 = 42, 303 .voltage_step2 = 20, 304 .voltage_nstep2 = 36, 305 }, 306 { 307 .id = AXP8XX_REG_ID_DCDC6, 308 .name = "dcdc6", 309 .enable_reg = AXP_POWERCTL1, 310 .enable_mask = (uint8_t) AXP_POWERCTL1_DCDC6, 311 .enable_value = AXP_POWERCTL1_DCDC6, 312 .voltage_reg = AXP_VOLTCTL_DCDC6, 313 .voltage_min = 600, 314 .voltage_max = 1520, 315 .voltage_step1 = 10, 316 .voltage_nstep1 = 50, 317 .voltage_step2 = 20, 318 .voltage_nstep2 = 21, 319 }, 320 { 321 .id = AXP8XX_REG_ID_DLDO1, 322 .name = "dldo1", 323 .enable_reg = AXP_POWERCTL2, 324 .enable_mask = (uint8_t) AXP_POWERCTL2_DLDO1, 325 .enable_value = AXP_POWERCTL2_DLDO1, 326 .voltage_reg = AXP_VOLTCTL_DLDO1, 327 .voltage_min = 700, 328 .voltage_max = 3300, 329 .voltage_step1 = 100, 330 .voltage_nstep1 = 26, 331 }, 332 { 333 .id = AXP8XX_REG_ID_DLDO2, 334 .name = "dldo2", 335 .enable_reg = AXP_POWERCTL2, 336 .enable_mask = (uint8_t) AXP_POWERCTL2_DLDO2, 337 .enable_value = AXP_POWERCTL2_DLDO2, 338 .voltage_reg = AXP_VOLTCTL_DLDO2, 339 .voltage_min = 700, 340 .voltage_max = 4200, 341 .voltage_step1 = 100, 342 .voltage_nstep1 = 27, 343 .voltage_step2 = 200, 344 .voltage_nstep2 = 4, 345 }, 346 { 347 .id = AXP8XX_REG_ID_DLDO3, 348 .name = "dldo3", 349 .enable_reg = AXP_POWERCTL2, 350 .enable_mask = (uint8_t) AXP_POWERCTL2_DLDO3, 351 .enable_value = AXP_POWERCTL2_DLDO3, 352 .voltage_reg = AXP_VOLTCTL_DLDO3, 353 .voltage_min = 700, 354 .voltage_max = 3300, 355 .voltage_step1 = 100, 356 .voltage_nstep1 = 26, 357 }, 358 { 359 .id = AXP8XX_REG_ID_DLDO4, 360 .name = "dldo4", 361 .enable_reg = AXP_POWERCTL2, 362 .enable_mask = (uint8_t) AXP_POWERCTL2_DLDO4, 363 .enable_value = AXP_POWERCTL2_DLDO4, 364 .voltage_reg = AXP_VOLTCTL_DLDO4, 365 .voltage_min = 700, 366 .voltage_max = 3300, 367 .voltage_step1 = 100, 368 .voltage_nstep1 = 26, 369 }, 370 { 371 .id = AXP8XX_REG_ID_ALDO1, 372 .name = "aldo1", 373 .enable_reg = AXP_POWERCTL3, 374 .enable_mask = (uint8_t) AXP_POWERCTL3_ALDO1, 375 .enable_value = AXP_POWERCTL3_ALDO1, 376 .voltage_min = 700, 377 .voltage_max = 3300, 378 .voltage_step1 = 100, 379 .voltage_nstep1 = 26, 380 }, 381 { 382 .id = AXP8XX_REG_ID_ALDO2, 383 .name = "aldo2", 384 .enable_reg = AXP_POWERCTL3, 385 .enable_mask = (uint8_t) AXP_POWERCTL3_ALDO2, 386 .enable_value = AXP_POWERCTL3_ALDO2, 387 .voltage_min = 700, 388 .voltage_max = 3300, 389 .voltage_step1 = 100, 390 .voltage_nstep1 = 26, 391 }, 392 { 393 .id = AXP8XX_REG_ID_ALDO3, 394 .name = "aldo3", 395 .enable_reg = AXP_POWERCTL3, 396 .enable_mask = (uint8_t) AXP_POWERCTL3_ALDO3, 397 .enable_value = AXP_POWERCTL3_ALDO3, 398 .voltage_min = 700, 399 .voltage_max = 3300, 400 .voltage_step1 = 100, 401 .voltage_nstep1 = 26, 402 }, 403 { 404 .id = AXP8XX_REG_ID_ELDO1, 405 .name = "eldo1", 406 .enable_reg = AXP_POWERCTL2, 407 .enable_mask = (uint8_t) AXP_POWERCTL2_ELDO1, 408 .enable_value = AXP_POWERCTL2_ELDO1, 409 .voltage_min = 700, 410 .voltage_max = 1900, 411 .voltage_step1 = 50, 412 .voltage_nstep1 = 24, 413 }, 414 { 415 .id = AXP8XX_REG_ID_ELDO2, 416 .name = "eldo2", 417 .enable_reg = AXP_POWERCTL2, 418 .enable_mask = (uint8_t) AXP_POWERCTL2_ELDO2, 419 .enable_value = AXP_POWERCTL2_ELDO2, 420 .voltage_min = 700, 421 .voltage_max = 1900, 422 .voltage_step1 = 50, 423 .voltage_nstep1 = 24, 424 }, 425 { 426 .id = AXP8XX_REG_ID_ELDO3, 427 .name = "eldo3", 428 .enable_reg = AXP_POWERCTL2, 429 .enable_mask = (uint8_t) AXP_POWERCTL2_ELDO3, 430 .enable_value = AXP_POWERCTL2_ELDO3, 431 .voltage_min = 700, 432 .voltage_max = 1900, 433 .voltage_step1 = 50, 434 .voltage_nstep1 = 24, 435 }, 436 { 437 .id = AXP8XX_REG_ID_FLDO1, 438 .name = "fldo1", 439 .enable_reg = AXP_POWERCTL3, 440 .enable_mask = (uint8_t) ~AXP_POWERCTL3_FLDO1, 441 .enable_value = AXP_POWERCTL3_FLDO1, 442 .voltage_min = 700, 443 .voltage_max = 1450, 444 .voltage_step1 = 50, 445 .voltage_nstep1 = 15, 446 }, 447 { 448 .id = AXP8XX_REG_ID_FLDO2, 449 .name = "fldo2", 450 .enable_reg = AXP_POWERCTL3, 451 .enable_mask = (uint8_t) AXP_POWERCTL3_FLDO2, 452 .enable_value = AXP_POWERCTL3_FLDO2, 453 .voltage_min = 700, 454 .voltage_max = 1450, 455 .voltage_step1 = 50, 456 .voltage_nstep1 = 15, 457 }, 458 { 459 .id = AXP8XX_REG_ID_GPIO0_LDO, 460 .name = "ldo-io0", 461 .enable_reg = AXP_GPIO0_CTRL, 462 .enable_mask = (uint8_t) AXP_GPIO_FUNC, 463 .enable_value = AXP_GPIO_FUNC_LDO_ON, 464 .disable_value = AXP_GPIO_FUNC_LDO_OFF, 465 .voltage_reg = AXP_GPIO0LDO_CTRL, 466 .voltage_min = 700, 467 .voltage_max = 3300, 468 .voltage_step1 = 100, 469 .voltage_nstep1 = 26, 470 }, 471 { 472 .id = AXP8XX_REG_ID_GPIO1_LDO, 473 .name = "ldo-io1", 474 .enable_reg = AXP_GPIO1_CTRL, 475 .enable_mask = (uint8_t) AXP_GPIO_FUNC, 476 .enable_value = AXP_GPIO_FUNC_LDO_ON, 477 .disable_value = AXP_GPIO_FUNC_LDO_OFF, 478 .voltage_reg = AXP_GPIO1LDO_CTRL, 479 .voltage_min = 700, 480 .voltage_max = 3300, 481 .voltage_step1 = 100, 482 .voltage_nstep1 = 26, 483 }, 484 }; 485 486 struct axp8xx_softc; 487 488 struct axp8xx_reg_sc { 489 struct regnode *regnode; 490 device_t base_dev; 491 struct axp8xx_regdef *def; 492 phandle_t xref; 493 struct regnode_std_param *param; 494 }; 495 496 struct axp8xx_softc { 497 struct resource *res; 498 uint16_t addr; 499 void *ih; 500 device_t gpiodev; 501 struct mtx mtx; 502 int busy; 503 504 int type; 505 506 /* Regulators */ 507 struct axp8xx_reg_sc **regs; 508 int nregs; 509 }; 510 511 #define AXP_LOCK(sc) mtx_lock(&(sc)->mtx) 512 #define AXP_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 513 514 static int 515 axp8xx_read(device_t dev, uint8_t reg, uint8_t *data, uint8_t size) 516 { 517 struct axp8xx_softc *sc; 518 struct iic_msg msg[2]; 519 520 sc = device_get_softc(dev); 521 522 msg[0].slave = sc->addr; 523 msg[0].flags = IIC_M_WR; 524 msg[0].len = 1; 525 msg[0].buf = ® 526 527 msg[1].slave = sc->addr; 528 msg[1].flags = IIC_M_RD; 529 msg[1].len = size; 530 msg[1].buf = data; 531 532 return (iicbus_transfer(dev, msg, 2)); 533 } 534 535 static int 536 axp8xx_write(device_t dev, uint8_t reg, uint8_t val) 537 { 538 struct axp8xx_softc *sc; 539 struct iic_msg msg[2]; 540 541 sc = device_get_softc(dev); 542 543 msg[0].slave = sc->addr; 544 msg[0].flags = IIC_M_WR; 545 msg[0].len = 1; 546 msg[0].buf = ® 547 548 msg[1].slave = sc->addr; 549 msg[1].flags = IIC_M_WR; 550 msg[1].len = 1; 551 msg[1].buf = &val; 552 553 return (iicbus_transfer(dev, msg, 2)); 554 } 555 556 static int 557 axp8xx_regnode_init(struct regnode *regnode) 558 { 559 return (0); 560 } 561 562 static int 563 axp8xx_regnode_enable(struct regnode *regnode, bool enable, int *udelay) 564 { 565 struct axp8xx_reg_sc *sc; 566 uint8_t val; 567 568 sc = regnode_get_softc(regnode); 569 570 if (bootverbose) 571 device_printf(sc->base_dev, "%sable %s (%s)\n", 572 enable ? "En" : "Dis", 573 regnode_get_name(regnode), 574 sc->def->name); 575 576 axp8xx_read(sc->base_dev, sc->def->enable_reg, &val, 1); 577 val &= ~sc->def->enable_mask; 578 if (enable) 579 val |= sc->def->enable_value; 580 else { 581 if (sc->def->disable_value) 582 val |= sc->def->disable_value; 583 else 584 val &= ~sc->def->enable_value; 585 } 586 axp8xx_write(sc->base_dev, sc->def->enable_reg, val); 587 588 *udelay = 0; 589 590 return (0); 591 } 592 593 static void 594 axp8xx_regnode_reg_to_voltage(struct axp8xx_reg_sc *sc, uint8_t val, int *uv) 595 { 596 if (val < sc->def->voltage_nstep1) 597 *uv = sc->def->voltage_min + val * sc->def->voltage_step1; 598 else 599 *uv = sc->def->voltage_min + 600 (sc->def->voltage_nstep1 * sc->def->voltage_step1) + 601 ((val - sc->def->voltage_nstep1) * sc->def->voltage_step2); 602 *uv *= 1000; 603 } 604 605 static int 606 axp8xx_regnode_voltage_to_reg(struct axp8xx_reg_sc *sc, int min_uvolt, 607 int max_uvolt, uint8_t *val) 608 { 609 uint8_t nval; 610 int nstep, uvolt; 611 612 nval = 0; 613 uvolt = sc->def->voltage_min * 1000; 614 615 for (nstep = 0; nstep < sc->def->voltage_nstep1 && uvolt < min_uvolt; 616 nstep++) { 617 ++nval; 618 uvolt += (sc->def->voltage_step1 * 1000); 619 } 620 for (nstep = 0; nstep < sc->def->voltage_nstep2 && uvolt < min_uvolt; 621 nstep++) { 622 ++nval; 623 uvolt += (sc->def->voltage_step2 * 1000); 624 } 625 if (uvolt > max_uvolt) 626 return (EINVAL); 627 628 *val = nval; 629 return (0); 630 } 631 632 static int 633 axp8xx_regnode_set_voltage(struct regnode *regnode, int min_uvolt, 634 int max_uvolt, int *udelay) 635 { 636 struct axp8xx_reg_sc *sc; 637 uint8_t val; 638 639 sc = regnode_get_softc(regnode); 640 641 if (bootverbose) 642 device_printf(sc->base_dev, "Setting %s (%s) to %d<->%d\n", 643 regnode_get_name(regnode), 644 sc->def->name, 645 min_uvolt, max_uvolt); 646 647 if (sc->def->voltage_step1 == 0) 648 return (ENXIO); 649 650 if (axp8xx_regnode_voltage_to_reg(sc, min_uvolt, max_uvolt, &val) != 0) 651 return (ERANGE); 652 653 axp8xx_write(sc->base_dev, sc->def->voltage_reg, val); 654 655 *udelay = 0; 656 657 return (0); 658 } 659 660 static int 661 axp8xx_regnode_get_voltage(struct regnode *regnode, int *uvolt) 662 { 663 struct axp8xx_reg_sc *sc; 664 uint8_t val; 665 666 sc = regnode_get_softc(regnode); 667 668 if (!sc->def->voltage_step1 || !sc->def->voltage_step2) 669 return (ENXIO); 670 671 axp8xx_read(sc->base_dev, sc->def->voltage_reg, &val, 1); 672 axp8xx_regnode_reg_to_voltage(sc, val & AXP_VOLTCTL_MASK, uvolt); 673 674 return (0); 675 } 676 677 static regnode_method_t axp8xx_regnode_methods[] = { 678 /* Regulator interface */ 679 REGNODEMETHOD(regnode_init, axp8xx_regnode_init), 680 REGNODEMETHOD(regnode_enable, axp8xx_regnode_enable), 681 REGNODEMETHOD(regnode_set_voltage, axp8xx_regnode_set_voltage), 682 REGNODEMETHOD(regnode_get_voltage, axp8xx_regnode_get_voltage), 683 REGNODEMETHOD_END 684 }; 685 DEFINE_CLASS_1(axp8xx_regnode, axp8xx_regnode_class, axp8xx_regnode_methods, 686 sizeof(struct axp8xx_reg_sc), regnode_class); 687 688 static void 689 axp8xx_shutdown(void *devp, int howto) 690 { 691 device_t dev; 692 693 if ((howto & RB_POWEROFF) == 0) 694 return; 695 696 dev = devp; 697 698 if (bootverbose) 699 device_printf(dev, "Shutdown Axp8xx\n"); 700 701 axp8xx_write(dev, AXP_POWERBAT, AXP_POWERBAT_SHUTDOWN); 702 } 703 704 static void 705 axp8xx_intr(void *arg) 706 { 707 device_t dev; 708 uint8_t val; 709 int error; 710 711 dev = arg; 712 713 error = axp8xx_read(dev, AXP_IRQSTAT5, &val, 1); 714 if (error != 0) 715 return; 716 717 if (val != 0) { 718 if ((val & AXP_IRQSTAT5_POKSIRQ) != 0) { 719 if (bootverbose) 720 device_printf(dev, "Power button pressed\n"); 721 shutdown_nice(RB_POWEROFF); 722 } 723 /* Acknowledge */ 724 axp8xx_write(dev, AXP_IRQSTAT5, val); 725 } 726 } 727 728 static device_t 729 axp8xx_gpio_get_bus(device_t dev) 730 { 731 struct axp8xx_softc *sc; 732 733 sc = device_get_softc(dev); 734 735 return (sc->gpiodev); 736 } 737 738 static int 739 axp8xx_gpio_pin_max(device_t dev, int *maxpin) 740 { 741 *maxpin = nitems(axp8xx_pins) - 1; 742 743 return (0); 744 } 745 746 static int 747 axp8xx_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 748 { 749 if (pin >= nitems(axp8xx_pins)) 750 return (EINVAL); 751 752 snprintf(name, GPIOMAXNAME, "%s", axp8xx_pins[pin].name); 753 754 return (0); 755 } 756 757 static int 758 axp8xx_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 759 { 760 if (pin >= nitems(axp8xx_pins)) 761 return (EINVAL); 762 763 *caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT; 764 765 return (0); 766 } 767 768 static int 769 axp8xx_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 770 { 771 struct axp8xx_softc *sc; 772 uint8_t data, func; 773 int error; 774 775 if (pin >= nitems(axp8xx_pins)) 776 return (EINVAL); 777 778 sc = device_get_softc(dev); 779 780 AXP_LOCK(sc); 781 error = axp8xx_read(dev, axp8xx_pins[pin].ctrl_reg, &data, 1); 782 if (error == 0) { 783 func = (data & AXP_GPIO_FUNC) >> AXP_GPIO_FUNC_SHIFT; 784 if (func == AXP_GPIO_FUNC_INPUT) 785 *flags = GPIO_PIN_INPUT; 786 else if (func == AXP_GPIO_FUNC_DRVLO || 787 func == AXP_GPIO_FUNC_DRVHI) 788 *flags = GPIO_PIN_OUTPUT; 789 else 790 *flags = 0; 791 } 792 AXP_UNLOCK(sc); 793 794 return (error); 795 } 796 797 static int 798 axp8xx_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 799 { 800 struct axp8xx_softc *sc; 801 uint8_t data; 802 int error; 803 804 if (pin >= nitems(axp8xx_pins)) 805 return (EINVAL); 806 807 sc = device_get_softc(dev); 808 809 AXP_LOCK(sc); 810 error = axp8xx_read(dev, axp8xx_pins[pin].ctrl_reg, &data, 1); 811 if (error == 0) { 812 data &= ~AXP_GPIO_FUNC; 813 if ((flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) != 0) { 814 if ((flags & GPIO_PIN_OUTPUT) == 0) 815 data |= AXP_GPIO_FUNC_INPUT; 816 } 817 error = axp8xx_write(dev, axp8xx_pins[pin].ctrl_reg, data); 818 } 819 AXP_UNLOCK(sc); 820 821 return (error); 822 } 823 824 static int 825 axp8xx_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) 826 { 827 struct axp8xx_softc *sc; 828 uint8_t data, func; 829 int error; 830 831 if (pin >= nitems(axp8xx_pins)) 832 return (EINVAL); 833 834 sc = device_get_softc(dev); 835 836 AXP_LOCK(sc); 837 error = axp8xx_read(dev, axp8xx_pins[pin].ctrl_reg, &data, 1); 838 if (error == 0) { 839 func = (data & AXP_GPIO_FUNC) >> AXP_GPIO_FUNC_SHIFT; 840 switch (func) { 841 case AXP_GPIO_FUNC_DRVLO: 842 *val = 0; 843 break; 844 case AXP_GPIO_FUNC_DRVHI: 845 *val = 1; 846 break; 847 case AXP_GPIO_FUNC_INPUT: 848 error = axp8xx_read(dev, AXP_GPIO_SIGBIT, &data, 1); 849 if (error == 0) 850 *val = (data & (1 << pin)) ? 1 : 0; 851 break; 852 default: 853 error = EIO; 854 break; 855 } 856 } 857 AXP_UNLOCK(sc); 858 859 return (error); 860 } 861 862 static int 863 axp8xx_gpio_pin_set(device_t dev, uint32_t pin, unsigned int val) 864 { 865 struct axp8xx_softc *sc; 866 uint8_t data, func; 867 int error; 868 869 if (pin >= nitems(axp8xx_pins)) 870 return (EINVAL); 871 872 sc = device_get_softc(dev); 873 874 AXP_LOCK(sc); 875 error = axp8xx_read(dev, axp8xx_pins[pin].ctrl_reg, &data, 1); 876 if (error == 0) { 877 func = (data & AXP_GPIO_FUNC) >> AXP_GPIO_FUNC_SHIFT; 878 switch (func) { 879 case AXP_GPIO_FUNC_DRVLO: 880 case AXP_GPIO_FUNC_DRVHI: 881 data &= ~AXP_GPIO_FUNC; 882 data |= (val << AXP_GPIO_FUNC_SHIFT); 883 break; 884 default: 885 error = EIO; 886 break; 887 } 888 } 889 if (error == 0) 890 error = axp8xx_write(dev, axp8xx_pins[pin].ctrl_reg, data); 891 AXP_UNLOCK(sc); 892 893 return (error); 894 } 895 896 897 static int 898 axp8xx_gpio_pin_toggle(device_t dev, uint32_t pin) 899 { 900 struct axp8xx_softc *sc; 901 uint8_t data, func; 902 int error; 903 904 if (pin >= nitems(axp8xx_pins)) 905 return (EINVAL); 906 907 sc = device_get_softc(dev); 908 909 AXP_LOCK(sc); 910 error = axp8xx_read(dev, axp8xx_pins[pin].ctrl_reg, &data, 1); 911 if (error == 0) { 912 func = (data & AXP_GPIO_FUNC) >> AXP_GPIO_FUNC_SHIFT; 913 switch (func) { 914 case AXP_GPIO_FUNC_DRVLO: 915 data &= ~AXP_GPIO_FUNC; 916 data |= (AXP_GPIO_FUNC_DRVHI << AXP_GPIO_FUNC_SHIFT); 917 break; 918 case AXP_GPIO_FUNC_DRVHI: 919 data &= ~AXP_GPIO_FUNC; 920 data |= (AXP_GPIO_FUNC_DRVLO << AXP_GPIO_FUNC_SHIFT); 921 break; 922 default: 923 error = EIO; 924 break; 925 } 926 } 927 if (error == 0) 928 error = axp8xx_write(dev, axp8xx_pins[pin].ctrl_reg, data); 929 AXP_UNLOCK(sc); 930 931 return (error); 932 } 933 934 static int 935 axp8xx_gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, 936 int gcells, pcell_t *gpios, uint32_t *pin, uint32_t *flags) 937 { 938 if (gpios[0] >= nitems(axp8xx_pins)) 939 return (EINVAL); 940 941 *pin = gpios[0]; 942 *flags = gpios[1]; 943 944 return (0); 945 } 946 947 static phandle_t 948 axp8xx_get_node(device_t dev, device_t bus) 949 { 950 return (ofw_bus_get_node(dev)); 951 } 952 953 static struct axp8xx_reg_sc * 954 axp8xx_reg_attach(device_t dev, phandle_t node, 955 struct axp8xx_regdef *def) 956 { 957 struct axp8xx_reg_sc *reg_sc; 958 struct regnode_init_def initdef; 959 struct regnode *regnode; 960 961 memset(&initdef, 0, sizeof(initdef)); 962 if (regulator_parse_ofw_stdparam(dev, node, &initdef) != 0) 963 return (NULL); 964 if (initdef.std_param.min_uvolt == 0) 965 initdef.std_param.min_uvolt = def->voltage_min * 1000; 966 if (initdef.std_param.max_uvolt == 0) 967 initdef.std_param.max_uvolt = def->voltage_max * 1000; 968 initdef.id = def->id; 969 initdef.ofw_node = node; 970 regnode = regnode_create(dev, &axp8xx_regnode_class, &initdef); 971 if (regnode == NULL) { 972 device_printf(dev, "cannot create regulator\n"); 973 return (NULL); 974 } 975 976 reg_sc = regnode_get_softc(regnode); 977 reg_sc->regnode = regnode; 978 reg_sc->base_dev = dev; 979 reg_sc->def = def; 980 reg_sc->xref = OF_xref_from_node(node); 981 reg_sc->param = regnode_get_stdparam(regnode); 982 983 regnode_register(regnode); 984 985 return (reg_sc); 986 } 987 988 static int 989 axp8xx_regdev_map(device_t dev, phandle_t xref, int ncells, pcell_t *cells, 990 intptr_t *num) 991 { 992 struct axp8xx_softc *sc; 993 int i; 994 995 sc = device_get_softc(dev); 996 for (i = 0; i < sc->nregs; i++) { 997 if (sc->regs[i] == NULL) 998 continue; 999 if (sc->regs[i]->xref == xref) { 1000 *num = sc->regs[i]->def->id; 1001 return (0); 1002 } 1003 } 1004 1005 return (ENXIO); 1006 } 1007 1008 static int 1009 axp8xx_probe(device_t dev) 1010 { 1011 if (!ofw_bus_status_okay(dev)) 1012 return (ENXIO); 1013 1014 switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) 1015 { 1016 case AXP803: 1017 device_set_desc(dev, "X-Powers AXP803 Power Management Unit"); 1018 break; 1019 case AXP813: 1020 device_set_desc(dev, "X-Powers AXP813 Power Management Unit"); 1021 break; 1022 default: 1023 return (ENXIO); 1024 } 1025 1026 return (BUS_PROBE_DEFAULT); 1027 } 1028 1029 static int 1030 axp8xx_attach(device_t dev) 1031 { 1032 struct axp8xx_softc *sc; 1033 struct axp8xx_reg_sc *reg; 1034 uint8_t chip_id; 1035 phandle_t rnode, child; 1036 int error, i; 1037 1038 sc = device_get_softc(dev); 1039 1040 sc->addr = iicbus_get_addr(dev); 1041 mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); 1042 1043 error = bus_alloc_resources(dev, axp8xx_spec, &sc->res); 1044 if (error != 0) { 1045 device_printf(dev, "cannot allocate resources for device\n"); 1046 return (error); 1047 } 1048 1049 if (bootverbose) { 1050 axp8xx_read(dev, AXP_ICTYPE, &chip_id, 1); 1051 device_printf(dev, "chip ID 0x%02x\n", chip_id); 1052 } 1053 1054 sc->nregs = nitems(axp8xx_common_regdefs); 1055 sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 1056 switch (sc->type) { 1057 case AXP803: 1058 sc->nregs += nitems(axp803_regdefs); 1059 break; 1060 case AXP813: 1061 sc->nregs += nitems(axp813_regdefs); 1062 break; 1063 } 1064 sc->regs = malloc(sizeof(struct axp8xx_reg_sc *) * sc->nregs, 1065 M_AXP8XX_REG, M_WAITOK | M_ZERO); 1066 1067 /* Attach known regulators that exist in the DT */ 1068 rnode = ofw_bus_find_child(ofw_bus_get_node(dev), "regulators"); 1069 if (rnode > 0) { 1070 for (i = 0; i < sc->nregs; i++) { 1071 char *regname; 1072 struct axp8xx_regdef *regdef; 1073 1074 if (i <= nitems(axp8xx_common_regdefs)) { 1075 regname = axp8xx_common_regdefs[i].name; 1076 regdef = &axp8xx_common_regdefs[i]; 1077 } else { 1078 int off; 1079 1080 off = i - nitems(axp8xx_common_regdefs); 1081 switch (sc->type) { 1082 case AXP803: 1083 regname = axp803_regdefs[off].name; 1084 regdef = &axp803_regdefs[off]; 1085 break; 1086 case AXP813: 1087 regname = axp813_regdefs[off].name; 1088 regdef = &axp813_regdefs[off]; 1089 break; 1090 } 1091 } 1092 child = ofw_bus_find_child(rnode, 1093 regname); 1094 if (child == 0) 1095 continue; 1096 reg = axp8xx_reg_attach(dev, child, 1097 regdef); 1098 if (reg == NULL) { 1099 device_printf(dev, 1100 "cannot attach regulator %s\n", 1101 regname); 1102 continue; 1103 } 1104 sc->regs[i] = reg; 1105 } 1106 } 1107 1108 /* Enable IRQ on short power key press */ 1109 axp8xx_write(dev, AXP_IRQEN1, 0); 1110 axp8xx_write(dev, AXP_IRQEN2, 0); 1111 axp8xx_write(dev, AXP_IRQEN3, 0); 1112 axp8xx_write(dev, AXP_IRQEN4, 0); 1113 axp8xx_write(dev, AXP_IRQEN5, AXP_IRQEN5_POKSIRQ); 1114 axp8xx_write(dev, AXP_IRQEN6, 0); 1115 1116 /* Install interrupt handler */ 1117 error = bus_setup_intr(dev, sc->res, INTR_TYPE_MISC | INTR_MPSAFE, 1118 NULL, axp8xx_intr, dev, &sc->ih); 1119 if (error != 0) { 1120 device_printf(dev, "cannot setup interrupt handler\n"); 1121 return (error); 1122 } 1123 1124 EVENTHANDLER_REGISTER(shutdown_final, axp8xx_shutdown, dev, 1125 SHUTDOWN_PRI_LAST); 1126 1127 sc->gpiodev = gpiobus_attach_bus(dev); 1128 1129 return (0); 1130 } 1131 1132 static device_method_t axp8xx_methods[] = { 1133 /* Device interface */ 1134 DEVMETHOD(device_probe, axp8xx_probe), 1135 DEVMETHOD(device_attach, axp8xx_attach), 1136 1137 /* GPIO interface */ 1138 DEVMETHOD(gpio_get_bus, axp8xx_gpio_get_bus), 1139 DEVMETHOD(gpio_pin_max, axp8xx_gpio_pin_max), 1140 DEVMETHOD(gpio_pin_getname, axp8xx_gpio_pin_getname), 1141 DEVMETHOD(gpio_pin_getcaps, axp8xx_gpio_pin_getcaps), 1142 DEVMETHOD(gpio_pin_getflags, axp8xx_gpio_pin_getflags), 1143 DEVMETHOD(gpio_pin_setflags, axp8xx_gpio_pin_setflags), 1144 DEVMETHOD(gpio_pin_get, axp8xx_gpio_pin_get), 1145 DEVMETHOD(gpio_pin_set, axp8xx_gpio_pin_set), 1146 DEVMETHOD(gpio_pin_toggle, axp8xx_gpio_pin_toggle), 1147 DEVMETHOD(gpio_map_gpios, axp8xx_gpio_map_gpios), 1148 1149 /* Regdev interface */ 1150 DEVMETHOD(regdev_map, axp8xx_regdev_map), 1151 1152 /* OFW bus interface */ 1153 DEVMETHOD(ofw_bus_get_node, axp8xx_get_node), 1154 1155 DEVMETHOD_END 1156 }; 1157 1158 static driver_t axp8xx_driver = { 1159 "axp8xx_pmu", 1160 axp8xx_methods, 1161 sizeof(struct axp8xx_softc), 1162 }; 1163 1164 static devclass_t axp8xx_devclass; 1165 extern devclass_t ofwgpiobus_devclass, gpioc_devclass; 1166 extern driver_t ofw_gpiobus_driver, gpioc_driver; 1167 1168 EARLY_DRIVER_MODULE(axp8xx, iicbus, axp8xx_driver, axp8xx_devclass, 0, 0, 1169 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LAST); 1170 EARLY_DRIVER_MODULE(ofw_gpiobus, axp8xx_pmu, ofw_gpiobus_driver, 1171 ofwgpiobus_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LAST); 1172 DRIVER_MODULE(gpioc, axp8xx_pmu, gpioc_driver, gpioc_devclass, 0, 0); 1173 MODULE_VERSION(axp8xx, 1); 1174 MODULE_DEPEND(axp8xx, iicbus, 1, 1, 1); 1175