1 /*- 2 * Copyright (c) 2018 Emmanuel Vadot <manu@freebsd.org> 3 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 /* 31 * X-Powers AXP803/813/818 PMU for Allwinner SoCs 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/eventhandler.h> 40 #include <sys/bus.h> 41 #include <sys/rman.h> 42 #include <sys/kernel.h> 43 #include <sys/reboot.h> 44 #include <sys/gpio.h> 45 #include <sys/module.h> 46 #include <machine/bus.h> 47 48 #include <dev/iicbus/iicbus.h> 49 #include <dev/iicbus/iiconf.h> 50 51 #include <dev/gpio/gpiobusvar.h> 52 53 #include <dev/ofw/ofw_bus.h> 54 #include <dev/ofw/ofw_bus_subr.h> 55 56 #include <dev/extres/regulator/regulator.h> 57 58 #include "gpio_if.h" 59 #include "iicbus_if.h" 60 #include "regdev_if.h" 61 62 MALLOC_DEFINE(M_AXP8XX_REG, "AXP8xx regulator", "AXP8xx power regulator"); 63 64 #define AXP_POWERSRC 0x00 65 #define AXP_POWERSRC_ACIN (1 << 7) 66 #define AXP_POWERSRC_VBUS (1 << 5) 67 #define AXP_POWERSRC_VBAT (1 << 3) 68 #define AXP_POWERSRC_CHARING (1 << 2) 69 #define AXP_POWERSRC_SHORTED (1 << 1) 70 #define AXP_POWERSRC_STARTUP (1 << 0) 71 #define AXP_ICTYPE 0x03 72 #define AXP_POWERCTL1 0x10 73 #define AXP_POWERCTL1_DCDC7 (1 << 6) /* AXP813/818 only */ 74 #define AXP_POWERCTL1_DCDC6 (1 << 5) 75 #define AXP_POWERCTL1_DCDC5 (1 << 4) 76 #define AXP_POWERCTL1_DCDC4 (1 << 3) 77 #define AXP_POWERCTL1_DCDC3 (1 << 2) 78 #define AXP_POWERCTL1_DCDC2 (1 << 1) 79 #define AXP_POWERCTL1_DCDC1 (1 << 0) 80 #define AXP_POWERCTL2 0x12 81 #define AXP_POWERCTL2_DC1SW (1 << 7) /* AXP803 only */ 82 #define AXP_POWERCTL2_DLDO4 (1 << 6) 83 #define AXP_POWERCTL2_DLDO3 (1 << 5) 84 #define AXP_POWERCTL2_DLDO2 (1 << 4) 85 #define AXP_POWERCTL2_DLDO1 (1 << 3) 86 #define AXP_POWERCTL2_ELDO3 (1 << 2) 87 #define AXP_POWERCTL2_ELDO2 (1 << 1) 88 #define AXP_POWERCTL2_ELDO1 (1 << 0) 89 #define AXP_POWERCTL3 0x13 90 #define AXP_POWERCTL3_ALDO3 (1 << 7) 91 #define AXP_POWERCTL3_ALDO2 (1 << 6) 92 #define AXP_POWERCTL3_ALDO1 (1 << 5) 93 #define AXP_POWERCTL3_FLDO3 (1 << 4) /* AXP813/818 only */ 94 #define AXP_POWERCTL3_FLDO2 (1 << 3) 95 #define AXP_POWERCTL3_FLDO1 (1 << 2) 96 #define AXP_VOLTCTL_DLDO1 0x15 97 #define AXP_VOLTCTL_DLDO2 0x16 98 #define AXP_VOLTCTL_DLDO3 0x17 99 #define AXP_VOLTCTL_DLDO4 0x18 100 #define AXP_VOLTCTL_ELDO1 0x19 101 #define AXP_VOLTCTL_ELDO2 0x1A 102 #define AXP_VOLTCTL_ELDO3 0x1B 103 #define AXP_VOLTCTL_FLDO1 0x1C 104 #define AXP_VOLTCTL_FLDO2 0x1D 105 #define AXP_VOLTCTL_DCDC1 0x20 106 #define AXP_VOLTCTL_DCDC2 0x21 107 #define AXP_VOLTCTL_DCDC3 0x22 108 #define AXP_VOLTCTL_DCDC4 0x23 109 #define AXP_VOLTCTL_DCDC5 0x24 110 #define AXP_VOLTCTL_DCDC6 0x25 111 #define AXP_VOLTCTL_DCDC7 0x26 112 #define AXP_VOLTCTL_ALDO1 0x28 113 #define AXP_VOLTCTL_ALDO2 0x29 114 #define AXP_VOLTCTL_ALDO3 0x2A 115 #define AXP_VOLTCTL_STATUS (1 << 7) 116 #define AXP_VOLTCTL_MASK 0x7f 117 #define AXP_POWERBAT 0x32 118 #define AXP_POWERBAT_SHUTDOWN (1 << 7) 119 #define AXP_IRQEN1 0x40 120 #define AXP_IRQEN2 0x41 121 #define AXP_IRQEN3 0x42 122 #define AXP_IRQEN4 0x43 123 #define AXP_IRQEN5 0x44 124 #define AXP_IRQEN5_POKSIRQ (1 << 4) 125 #define AXP_IRQEN6 0x45 126 #define AXP_IRQSTAT5 0x4c 127 #define AXP_IRQSTAT5_POKSIRQ (1 << 4) 128 #define AXP_GPIO0_CTRL 0x90 129 #define AXP_GPIO1_CTRL 0x92 130 #define AXP_GPIO_FUNC (0x7 << 0) 131 #define AXP_GPIO_FUNC_SHIFT 0 132 #define AXP_GPIO_FUNC_DRVLO 0 133 #define AXP_GPIO_FUNC_DRVHI 1 134 #define AXP_GPIO_FUNC_INPUT 2 135 #define AXP_GPIO_SIGBIT 0x94 136 #define AXP_GPIO_PD 0x97 137 138 static const struct { 139 const char *name; 140 uint8_t ctrl_reg; 141 } axp8xx_pins[] = { 142 { "GPIO0", AXP_GPIO0_CTRL }, 143 { "GPIO1", AXP_GPIO1_CTRL }, 144 }; 145 146 enum AXP8XX_TYPE { 147 AXP803 = 1, 148 AXP813, 149 }; 150 151 static struct ofw_compat_data compat_data[] = { 152 { "x-powers,axp803", AXP803 }, 153 { "x-powers,axp813", AXP813 }, 154 { "x-powers,axp818", AXP813 }, 155 { NULL, 0 } 156 }; 157 158 static struct resource_spec axp8xx_spec[] = { 159 { SYS_RES_IRQ, 0, RF_ACTIVE }, 160 { -1, 0 } 161 }; 162 163 struct axp8xx_regdef { 164 intptr_t id; 165 char *name; 166 char *supply_name; 167 uint8_t enable_reg; 168 uint8_t enable_mask; 169 uint8_t voltage_reg; 170 int voltage_min; 171 int voltage_max; 172 int voltage_step1; 173 int voltage_nstep1; 174 int voltage_step2; 175 int voltage_nstep2; 176 }; 177 178 enum axp8xx_reg_id { 179 AXP8XX_REG_ID_DCDC1 = 100, 180 AXP8XX_REG_ID_DCDC2, 181 AXP8XX_REG_ID_DCDC3, 182 AXP8XX_REG_ID_DCDC4, 183 AXP8XX_REG_ID_DCDC5, 184 AXP8XX_REG_ID_DCDC6, 185 AXP813_REG_ID_DCDC7, 186 AXP803_REG_ID_DC1SW, 187 AXP8XX_REG_ID_DLDO1, 188 AXP8XX_REG_ID_DLDO2, 189 AXP8XX_REG_ID_DLDO3, 190 AXP8XX_REG_ID_DLDO4, 191 AXP8XX_REG_ID_ELDO1, 192 AXP8XX_REG_ID_ELDO2, 193 AXP8XX_REG_ID_ELDO3, 194 AXP8XX_REG_ID_ALDO1, 195 AXP8XX_REG_ID_ALDO2, 196 AXP8XX_REG_ID_ALDO3, 197 AXP8XX_REG_ID_FLDO1, 198 AXP8XX_REG_ID_FLDO2, 199 AXP813_REG_ID_FLDO3, 200 }; 201 202 static struct axp8xx_regdef axp803_regdefs[] = { 203 { 204 .id = AXP803_REG_ID_DC1SW, 205 .name = "dc1sw", 206 .enable_reg = AXP_POWERCTL2, 207 .enable_mask = AXP_POWERCTL2_DC1SW, 208 }, 209 }; 210 211 static struct axp8xx_regdef axp813_regdefs[] = { 212 { 213 .id = AXP813_REG_ID_DCDC7, 214 .name = "dcdc7", 215 .enable_reg = AXP_POWERCTL1, 216 .enable_mask = AXP_POWERCTL1_DCDC7, 217 .voltage_reg = AXP_VOLTCTL_DCDC7, 218 .voltage_min = 600, 219 .voltage_max = 1520, 220 .voltage_step1 = 10, 221 .voltage_nstep1 = 50, 222 .voltage_step2 = 20, 223 .voltage_nstep2 = 21, 224 }, 225 }; 226 227 static struct axp8xx_regdef axp8xx_common_regdefs[] = { 228 { 229 .id = AXP8XX_REG_ID_DCDC1, 230 .name = "dcdc1", 231 .enable_reg = AXP_POWERCTL1, 232 .enable_mask = AXP_POWERCTL1_DCDC1, 233 .voltage_reg = AXP_VOLTCTL_DCDC1, 234 .voltage_min = 1600, 235 .voltage_max = 3400, 236 .voltage_step1 = 100, 237 .voltage_nstep1 = 18, 238 }, 239 { 240 .id = AXP8XX_REG_ID_DCDC2, 241 .name = "dcdc2", 242 .enable_reg = AXP_POWERCTL1, 243 .enable_mask = AXP_POWERCTL1_DCDC2, 244 .voltage_reg = AXP_VOLTCTL_DCDC2, 245 .voltage_min = 500, 246 .voltage_max = 1300, 247 .voltage_step1 = 10, 248 .voltage_nstep1 = 70, 249 .voltage_step2 = 20, 250 .voltage_nstep2 = 5, 251 }, 252 { 253 .id = AXP8XX_REG_ID_DCDC3, 254 .name = "dcdc3", 255 .enable_reg = AXP_POWERCTL1, 256 .enable_mask = AXP_POWERCTL1_DCDC3, 257 .voltage_reg = AXP_VOLTCTL_DCDC3, 258 .voltage_min = 500, 259 .voltage_max = 1300, 260 .voltage_step1 = 10, 261 .voltage_nstep1 = 70, 262 .voltage_step2 = 20, 263 .voltage_nstep2 = 5, 264 }, 265 { 266 .id = AXP8XX_REG_ID_DCDC4, 267 .name = "dcdc4", 268 .enable_reg = AXP_POWERCTL1, 269 .enable_mask = AXP_POWERCTL1_DCDC4, 270 .voltage_reg = AXP_VOLTCTL_DCDC4, 271 .voltage_min = 500, 272 .voltage_max = 1300, 273 .voltage_step1 = 10, 274 .voltage_nstep1 = 70, 275 .voltage_step2 = 20, 276 .voltage_nstep2 = 5, 277 }, 278 { 279 .id = AXP8XX_REG_ID_DCDC5, 280 .name = "dcdc5", 281 .enable_reg = AXP_POWERCTL1, 282 .enable_mask = AXP_POWERCTL1_DCDC5, 283 .voltage_reg = AXP_VOLTCTL_DCDC5, 284 .voltage_min = 800, 285 .voltage_max = 1840, 286 .voltage_step1 = 10, 287 .voltage_nstep1 = 42, 288 .voltage_step2 = 20, 289 .voltage_nstep2 = 36, 290 }, 291 { 292 .id = AXP8XX_REG_ID_DCDC6, 293 .name = "dcdc6", 294 .enable_reg = AXP_POWERCTL1, 295 .enable_mask = AXP_POWERCTL1_DCDC6, 296 .voltage_reg = AXP_VOLTCTL_DCDC6, 297 .voltage_min = 600, 298 .voltage_max = 1520, 299 .voltage_step1 = 10, 300 .voltage_nstep1 = 50, 301 .voltage_step2 = 20, 302 .voltage_nstep2 = 21, 303 }, 304 { 305 .id = AXP8XX_REG_ID_DLDO1, 306 .name = "dldo1", 307 .enable_reg = AXP_POWERCTL2, 308 .enable_mask = AXP_POWERCTL2_DLDO1, 309 .voltage_reg = AXP_VOLTCTL_DLDO1, 310 .voltage_min = 700, 311 .voltage_max = 3300, 312 .voltage_step1 = 100, 313 .voltage_nstep1 = 26, 314 }, 315 { 316 .id = AXP8XX_REG_ID_DLDO2, 317 .name = "dldo2", 318 .enable_reg = AXP_POWERCTL2, 319 .enable_mask = AXP_POWERCTL2_DLDO2, 320 .voltage_reg = AXP_VOLTCTL_DLDO2, 321 .voltage_min = 700, 322 .voltage_max = 4200, 323 .voltage_step1 = 100, 324 .voltage_nstep1 = 27, 325 .voltage_step2 = 200, 326 .voltage_nstep2 = 4, 327 }, 328 { 329 .id = AXP8XX_REG_ID_DLDO3, 330 .name = "dldo3", 331 .enable_reg = AXP_POWERCTL2, 332 .enable_mask = AXP_POWERCTL2_DLDO3, 333 .voltage_reg = AXP_VOLTCTL_DLDO3, 334 .voltage_min = 700, 335 .voltage_max = 3300, 336 .voltage_step1 = 100, 337 .voltage_nstep1 = 26, 338 }, 339 { 340 .id = AXP8XX_REG_ID_DLDO4, 341 .name = "dldo4", 342 .enable_reg = AXP_POWERCTL2, 343 .enable_mask = AXP_POWERCTL2_DLDO4, 344 .voltage_reg = AXP_VOLTCTL_DLDO4, 345 .voltage_min = 700, 346 .voltage_max = 3300, 347 .voltage_step1 = 100, 348 .voltage_nstep1 = 26, 349 }, 350 { 351 .id = AXP8XX_REG_ID_ALDO1, 352 .name = "aldo1", 353 .enable_reg = AXP_POWERCTL3, 354 .enable_mask = AXP_POWERCTL3_ALDO1, 355 .voltage_min = 700, 356 .voltage_max = 3300, 357 .voltage_step1 = 100, 358 .voltage_nstep1 = 26, 359 }, 360 { 361 .id = AXP8XX_REG_ID_ALDO2, 362 .name = "aldo2", 363 .enable_reg = AXP_POWERCTL3, 364 .enable_mask = AXP_POWERCTL3_ALDO2, 365 .voltage_min = 700, 366 .voltage_max = 3300, 367 .voltage_step1 = 100, 368 .voltage_nstep1 = 26, 369 }, 370 { 371 .id = AXP8XX_REG_ID_ALDO3, 372 .name = "aldo3", 373 .enable_reg = AXP_POWERCTL3, 374 .enable_mask = AXP_POWERCTL3_ALDO3, 375 .voltage_min = 700, 376 .voltage_max = 3300, 377 .voltage_step1 = 100, 378 .voltage_nstep1 = 26, 379 }, 380 { 381 .id = AXP8XX_REG_ID_ELDO1, 382 .name = "eldo1", 383 .enable_reg = AXP_POWERCTL2, 384 .enable_mask = AXP_POWERCTL2_ELDO1, 385 .voltage_min = 700, 386 .voltage_max = 1900, 387 .voltage_step1 = 50, 388 .voltage_nstep1 = 24, 389 }, 390 { 391 .id = AXP8XX_REG_ID_ELDO2, 392 .name = "eldo2", 393 .enable_reg = AXP_POWERCTL2, 394 .enable_mask = AXP_POWERCTL2_ELDO2, 395 .voltage_min = 700, 396 .voltage_max = 1900, 397 .voltage_step1 = 50, 398 .voltage_nstep1 = 24, 399 }, 400 { 401 .id = AXP8XX_REG_ID_ELDO3, 402 .name = "eldo3", 403 .enable_reg = AXP_POWERCTL2, 404 .enable_mask = AXP_POWERCTL2_ELDO3, 405 .voltage_min = 700, 406 .voltage_max = 1900, 407 .voltage_step1 = 50, 408 .voltage_nstep1 = 24, 409 }, 410 { 411 .id = AXP8XX_REG_ID_FLDO1, 412 .name = "fldo1", 413 .enable_reg = AXP_POWERCTL3, 414 .enable_mask = AXP_POWERCTL3_FLDO1, 415 .voltage_min = 700, 416 .voltage_max = 1450, 417 .voltage_step1 = 50, 418 .voltage_nstep1 = 15, 419 }, 420 { 421 .id = AXP8XX_REG_ID_FLDO2, 422 .name = "fldo2", 423 .enable_reg = AXP_POWERCTL3, 424 .enable_mask = AXP_POWERCTL3_FLDO2, 425 .voltage_min = 700, 426 .voltage_max = 1450, 427 .voltage_step1 = 50, 428 .voltage_nstep1 = 15, 429 }, 430 }; 431 432 struct axp8xx_softc; 433 434 struct axp8xx_reg_sc { 435 struct regnode *regnode; 436 device_t base_dev; 437 struct axp8xx_regdef *def; 438 phandle_t xref; 439 struct regnode_std_param *param; 440 }; 441 442 struct axp8xx_softc { 443 struct resource *res; 444 uint16_t addr; 445 void *ih; 446 device_t gpiodev; 447 struct mtx mtx; 448 int busy; 449 450 int type; 451 452 /* Regulators */ 453 struct axp8xx_reg_sc **regs; 454 int nregs; 455 }; 456 457 #define AXP_LOCK(sc) mtx_lock(&(sc)->mtx) 458 #define AXP_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 459 460 static int 461 axp8xx_read(device_t dev, uint8_t reg, uint8_t *data, uint8_t size) 462 { 463 struct axp8xx_softc *sc; 464 struct iic_msg msg[2]; 465 466 sc = device_get_softc(dev); 467 468 msg[0].slave = sc->addr; 469 msg[0].flags = IIC_M_WR; 470 msg[0].len = 1; 471 msg[0].buf = ® 472 473 msg[1].slave = sc->addr; 474 msg[1].flags = IIC_M_RD; 475 msg[1].len = size; 476 msg[1].buf = data; 477 478 return (iicbus_transfer(dev, msg, 2)); 479 } 480 481 static int 482 axp8xx_write(device_t dev, uint8_t reg, uint8_t val) 483 { 484 struct axp8xx_softc *sc; 485 struct iic_msg msg[2]; 486 487 sc = device_get_softc(dev); 488 489 msg[0].slave = sc->addr; 490 msg[0].flags = IIC_M_WR; 491 msg[0].len = 1; 492 msg[0].buf = ® 493 494 msg[1].slave = sc->addr; 495 msg[1].flags = IIC_M_WR; 496 msg[1].len = 1; 497 msg[1].buf = &val; 498 499 return (iicbus_transfer(dev, msg, 2)); 500 } 501 502 static int 503 axp8xx_regnode_init(struct regnode *regnode) 504 { 505 return (0); 506 } 507 508 static int 509 axp8xx_regnode_enable(struct regnode *regnode, bool enable, int *udelay) 510 { 511 struct axp8xx_reg_sc *sc; 512 uint8_t val; 513 514 sc = regnode_get_softc(regnode); 515 516 if (bootverbose) 517 device_printf(sc->base_dev, "%sable %s (%s)\n", 518 enable ? "En" : "Dis", 519 regnode_get_name(regnode), 520 sc->def->name); 521 522 axp8xx_read(sc->base_dev, sc->def->enable_reg, &val, 1); 523 if (enable) 524 val |= sc->def->enable_mask; 525 else 526 val &= ~sc->def->enable_mask; 527 axp8xx_write(sc->base_dev, sc->def->enable_reg, val); 528 529 *udelay = 0; 530 531 return (0); 532 } 533 534 static void 535 axp8xx_regnode_reg_to_voltage(struct axp8xx_reg_sc *sc, uint8_t val, int *uv) 536 { 537 if (val < sc->def->voltage_nstep1) 538 *uv = sc->def->voltage_min + val * sc->def->voltage_step1; 539 else 540 *uv = sc->def->voltage_min + 541 (sc->def->voltage_nstep1 * sc->def->voltage_step1) + 542 ((val - sc->def->voltage_nstep1) * sc->def->voltage_step2); 543 *uv *= 1000; 544 } 545 546 static int 547 axp8xx_regnode_voltage_to_reg(struct axp8xx_reg_sc *sc, int min_uvolt, 548 int max_uvolt, uint8_t *val) 549 { 550 uint8_t nval; 551 int nstep, uvolt; 552 553 nval = 0; 554 uvolt = sc->def->voltage_min * 1000; 555 556 for (nstep = 0; nstep < sc->def->voltage_nstep1 && uvolt < min_uvolt; 557 nstep++) { 558 ++nval; 559 uvolt += (sc->def->voltage_step1 * 1000); 560 } 561 for (nstep = 0; nstep < sc->def->voltage_nstep2 && uvolt < min_uvolt; 562 nstep++) { 563 ++nval; 564 uvolt += (sc->def->voltage_step2 * 1000); 565 } 566 if (uvolt > max_uvolt) 567 return (EINVAL); 568 569 *val = nval; 570 return (0); 571 } 572 573 static int 574 axp8xx_regnode_set_voltage(struct regnode *regnode, int min_uvolt, 575 int max_uvolt, int *udelay) 576 { 577 struct axp8xx_reg_sc *sc; 578 uint8_t val; 579 580 sc = regnode_get_softc(regnode); 581 582 if (bootverbose) 583 device_printf(sc->base_dev, "Setting %s (%s) to %d<->%d\n", 584 regnode_get_name(regnode), 585 sc->def->name, 586 min_uvolt, max_uvolt); 587 588 if (sc->def->voltage_step1 == 0) 589 return (ENXIO); 590 591 if (axp8xx_regnode_voltage_to_reg(sc, min_uvolt, max_uvolt, &val) != 0) 592 return (ERANGE); 593 594 axp8xx_write(sc->base_dev, sc->def->voltage_reg, val); 595 596 *udelay = 0; 597 598 return (0); 599 } 600 601 static int 602 axp8xx_regnode_get_voltage(struct regnode *regnode, int *uvolt) 603 { 604 struct axp8xx_reg_sc *sc; 605 uint8_t val; 606 607 sc = regnode_get_softc(regnode); 608 609 if (!sc->def->voltage_step1 || !sc->def->voltage_step2) 610 return (ENXIO); 611 612 axp8xx_read(sc->base_dev, sc->def->voltage_reg, &val, 1); 613 axp8xx_regnode_reg_to_voltage(sc, val & AXP_VOLTCTL_MASK, uvolt); 614 615 return (0); 616 } 617 618 static regnode_method_t axp8xx_regnode_methods[] = { 619 /* Regulator interface */ 620 REGNODEMETHOD(regnode_init, axp8xx_regnode_init), 621 REGNODEMETHOD(regnode_enable, axp8xx_regnode_enable), 622 REGNODEMETHOD(regnode_set_voltage, axp8xx_regnode_set_voltage), 623 REGNODEMETHOD(regnode_get_voltage, axp8xx_regnode_get_voltage), 624 REGNODEMETHOD_END 625 }; 626 DEFINE_CLASS_1(axp8xx_regnode, axp8xx_regnode_class, axp8xx_regnode_methods, 627 sizeof(struct axp8xx_reg_sc), regnode_class); 628 629 static void 630 axp8xx_shutdown(void *devp, int howto) 631 { 632 device_t dev; 633 634 if ((howto & RB_POWEROFF) == 0) 635 return; 636 637 dev = devp; 638 639 if (bootverbose) 640 device_printf(dev, "Shutdown Axp8xx\n"); 641 642 axp8xx_write(dev, AXP_POWERBAT, AXP_POWERBAT_SHUTDOWN); 643 } 644 645 static void 646 axp8xx_intr(void *arg) 647 { 648 device_t dev; 649 uint8_t val; 650 int error; 651 652 dev = arg; 653 654 error = axp8xx_read(dev, AXP_IRQSTAT5, &val, 1); 655 if (error != 0) 656 return; 657 658 if (val != 0) { 659 if ((val & AXP_IRQSTAT5_POKSIRQ) != 0) { 660 if (bootverbose) 661 device_printf(dev, "Power button pressed\n"); 662 shutdown_nice(RB_POWEROFF); 663 } 664 /* Acknowledge */ 665 axp8xx_write(dev, AXP_IRQSTAT5, val); 666 } 667 } 668 669 static device_t 670 axp8xx_gpio_get_bus(device_t dev) 671 { 672 struct axp8xx_softc *sc; 673 674 sc = device_get_softc(dev); 675 676 return (sc->gpiodev); 677 } 678 679 static int 680 axp8xx_gpio_pin_max(device_t dev, int *maxpin) 681 { 682 *maxpin = nitems(axp8xx_pins) - 1; 683 684 return (0); 685 } 686 687 static int 688 axp8xx_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 689 { 690 if (pin >= nitems(axp8xx_pins)) 691 return (EINVAL); 692 693 snprintf(name, GPIOMAXNAME, "%s", axp8xx_pins[pin].name); 694 695 return (0); 696 } 697 698 static int 699 axp8xx_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 700 { 701 if (pin >= nitems(axp8xx_pins)) 702 return (EINVAL); 703 704 *caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT; 705 706 return (0); 707 } 708 709 static int 710 axp8xx_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 711 { 712 struct axp8xx_softc *sc; 713 uint8_t data, func; 714 int error; 715 716 if (pin >= nitems(axp8xx_pins)) 717 return (EINVAL); 718 719 sc = device_get_softc(dev); 720 721 AXP_LOCK(sc); 722 error = axp8xx_read(dev, axp8xx_pins[pin].ctrl_reg, &data, 1); 723 if (error == 0) { 724 func = (data & AXP_GPIO_FUNC) >> AXP_GPIO_FUNC_SHIFT; 725 if (func == AXP_GPIO_FUNC_INPUT) 726 *flags = GPIO_PIN_INPUT; 727 else if (func == AXP_GPIO_FUNC_DRVLO || 728 func == AXP_GPIO_FUNC_DRVHI) 729 *flags = GPIO_PIN_OUTPUT; 730 else 731 *flags = 0; 732 } 733 AXP_UNLOCK(sc); 734 735 return (error); 736 } 737 738 static int 739 axp8xx_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 740 { 741 struct axp8xx_softc *sc; 742 uint8_t data; 743 int error; 744 745 if (pin >= nitems(axp8xx_pins)) 746 return (EINVAL); 747 748 sc = device_get_softc(dev); 749 750 AXP_LOCK(sc); 751 error = axp8xx_read(dev, axp8xx_pins[pin].ctrl_reg, &data, 1); 752 if (error == 0) { 753 data &= ~AXP_GPIO_FUNC; 754 if ((flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) != 0) { 755 if ((flags & GPIO_PIN_OUTPUT) == 0) 756 data |= AXP_GPIO_FUNC_INPUT; 757 } 758 error = axp8xx_write(dev, axp8xx_pins[pin].ctrl_reg, data); 759 } 760 AXP_UNLOCK(sc); 761 762 return (error); 763 } 764 765 static int 766 axp8xx_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) 767 { 768 struct axp8xx_softc *sc; 769 uint8_t data, func; 770 int error; 771 772 if (pin >= nitems(axp8xx_pins)) 773 return (EINVAL); 774 775 sc = device_get_softc(dev); 776 777 AXP_LOCK(sc); 778 error = axp8xx_read(dev, axp8xx_pins[pin].ctrl_reg, &data, 1); 779 if (error == 0) { 780 func = (data & AXP_GPIO_FUNC) >> AXP_GPIO_FUNC_SHIFT; 781 switch (func) { 782 case AXP_GPIO_FUNC_DRVLO: 783 *val = 0; 784 break; 785 case AXP_GPIO_FUNC_DRVHI: 786 *val = 1; 787 break; 788 case AXP_GPIO_FUNC_INPUT: 789 error = axp8xx_read(dev, AXP_GPIO_SIGBIT, &data, 1); 790 if (error == 0) 791 *val = (data & (1 << pin)) ? 1 : 0; 792 break; 793 default: 794 error = EIO; 795 break; 796 } 797 } 798 AXP_UNLOCK(sc); 799 800 return (error); 801 } 802 803 static int 804 axp8xx_gpio_pin_set(device_t dev, uint32_t pin, unsigned int val) 805 { 806 struct axp8xx_softc *sc; 807 uint8_t data, func; 808 int error; 809 810 if (pin >= nitems(axp8xx_pins)) 811 return (EINVAL); 812 813 sc = device_get_softc(dev); 814 815 AXP_LOCK(sc); 816 error = axp8xx_read(dev, axp8xx_pins[pin].ctrl_reg, &data, 1); 817 if (error == 0) { 818 func = (data & AXP_GPIO_FUNC) >> AXP_GPIO_FUNC_SHIFT; 819 switch (func) { 820 case AXP_GPIO_FUNC_DRVLO: 821 case AXP_GPIO_FUNC_DRVHI: 822 data &= ~AXP_GPIO_FUNC; 823 data |= (val << AXP_GPIO_FUNC_SHIFT); 824 break; 825 default: 826 error = EIO; 827 break; 828 } 829 } 830 if (error == 0) 831 error = axp8xx_write(dev, axp8xx_pins[pin].ctrl_reg, data); 832 AXP_UNLOCK(sc); 833 834 return (error); 835 } 836 837 838 static int 839 axp8xx_gpio_pin_toggle(device_t dev, uint32_t pin) 840 { 841 struct axp8xx_softc *sc; 842 uint8_t data, func; 843 int error; 844 845 if (pin >= nitems(axp8xx_pins)) 846 return (EINVAL); 847 848 sc = device_get_softc(dev); 849 850 AXP_LOCK(sc); 851 error = axp8xx_read(dev, axp8xx_pins[pin].ctrl_reg, &data, 1); 852 if (error == 0) { 853 func = (data & AXP_GPIO_FUNC) >> AXP_GPIO_FUNC_SHIFT; 854 switch (func) { 855 case AXP_GPIO_FUNC_DRVLO: 856 data &= ~AXP_GPIO_FUNC; 857 data |= (AXP_GPIO_FUNC_DRVHI << AXP_GPIO_FUNC_SHIFT); 858 break; 859 case AXP_GPIO_FUNC_DRVHI: 860 data &= ~AXP_GPIO_FUNC; 861 data |= (AXP_GPIO_FUNC_DRVLO << AXP_GPIO_FUNC_SHIFT); 862 break; 863 default: 864 error = EIO; 865 break; 866 } 867 } 868 if (error == 0) 869 error = axp8xx_write(dev, axp8xx_pins[pin].ctrl_reg, data); 870 AXP_UNLOCK(sc); 871 872 return (error); 873 } 874 875 static int 876 axp8xx_gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, 877 int gcells, pcell_t *gpios, uint32_t *pin, uint32_t *flags) 878 { 879 if (gpios[0] >= nitems(axp8xx_pins)) 880 return (EINVAL); 881 882 *pin = gpios[0]; 883 *flags = gpios[1]; 884 885 return (0); 886 } 887 888 static phandle_t 889 axp8xx_get_node(device_t dev, device_t bus) 890 { 891 return (ofw_bus_get_node(dev)); 892 } 893 894 static struct axp8xx_reg_sc * 895 axp8xx_reg_attach(device_t dev, phandle_t node, 896 struct axp8xx_regdef *def) 897 { 898 struct axp8xx_reg_sc *reg_sc; 899 struct regnode_init_def initdef; 900 struct regnode *regnode; 901 902 memset(&initdef, 0, sizeof(initdef)); 903 regulator_parse_ofw_stdparam(dev, node, &initdef); 904 if (initdef.std_param.min_uvolt == 0) 905 initdef.std_param.min_uvolt = def->voltage_min * 1000; 906 if (initdef.std_param.max_uvolt == 0) 907 initdef.std_param.max_uvolt = def->voltage_max * 1000; 908 initdef.id = def->id; 909 initdef.ofw_node = node; 910 regnode = regnode_create(dev, &axp8xx_regnode_class, &initdef); 911 if (regnode == NULL) { 912 device_printf(dev, "cannot create regulator\n"); 913 return (NULL); 914 } 915 916 reg_sc = regnode_get_softc(regnode); 917 reg_sc->regnode = regnode; 918 reg_sc->base_dev = dev; 919 reg_sc->def = def; 920 reg_sc->xref = OF_xref_from_node(node); 921 reg_sc->param = regnode_get_stdparam(regnode); 922 923 regnode_register(regnode); 924 925 return (reg_sc); 926 } 927 928 static int 929 axp8xx_regdev_map(device_t dev, phandle_t xref, int ncells, pcell_t *cells, 930 intptr_t *num) 931 { 932 struct axp8xx_softc *sc; 933 int i; 934 935 sc = device_get_softc(dev); 936 for (i = 0; i < sc->nregs; i++) { 937 if (sc->regs[i] == NULL) 938 continue; 939 if (sc->regs[i]->xref == xref) { 940 *num = sc->regs[i]->def->id; 941 return (0); 942 } 943 } 944 945 return (ENXIO); 946 } 947 948 static int 949 axp8xx_probe(device_t dev) 950 { 951 if (!ofw_bus_status_okay(dev)) 952 return (ENXIO); 953 954 switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) 955 { 956 case AXP803: 957 device_set_desc(dev, "X-Powers AXP803 Power Management Unit"); 958 break; 959 case AXP813: 960 device_set_desc(dev, "X-Powers AXP813 Power Management Unit"); 961 break; 962 default: 963 return (ENXIO); 964 } 965 966 return (BUS_PROBE_DEFAULT); 967 } 968 969 static int 970 axp8xx_attach(device_t dev) 971 { 972 struct axp8xx_softc *sc; 973 struct axp8xx_reg_sc *reg; 974 uint8_t chip_id; 975 phandle_t rnode, child; 976 int error, i; 977 978 sc = device_get_softc(dev); 979 980 sc->addr = iicbus_get_addr(dev); 981 mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); 982 983 error = bus_alloc_resources(dev, axp8xx_spec, &sc->res); 984 if (error != 0) { 985 device_printf(dev, "cannot allocate resources for device\n"); 986 return (error); 987 } 988 989 if (bootverbose) { 990 axp8xx_read(dev, AXP_ICTYPE, &chip_id, 1); 991 device_printf(dev, "chip ID 0x%02x\n", chip_id); 992 } 993 994 sc->nregs = nitems(axp8xx_common_regdefs); 995 sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 996 switch (sc->type) { 997 case AXP803: 998 sc->nregs += nitems(axp803_regdefs); 999 break; 1000 case AXP813: 1001 sc->nregs += nitems(axp813_regdefs); 1002 break; 1003 } 1004 sc->regs = malloc(sizeof(struct axp8xx_reg_sc *) * sc->nregs, 1005 M_AXP8XX_REG, M_WAITOK | M_ZERO); 1006 1007 /* Attach known regulators that exist in the DT */ 1008 rnode = ofw_bus_find_child(ofw_bus_get_node(dev), "regulators"); 1009 if (rnode > 0) { 1010 for (i = 0; i < sc->nregs; i++) { 1011 char *regname; 1012 struct axp8xx_regdef *regdef; 1013 1014 if (i <= nitems(axp8xx_common_regdefs)) { 1015 regname = axp8xx_common_regdefs[i].name; 1016 regdef = &axp8xx_common_regdefs[i]; 1017 } else { 1018 int off; 1019 1020 off = i - nitems(axp8xx_common_regdefs); 1021 switch (sc->type) { 1022 case AXP803: 1023 regname = axp803_regdefs[off].name; 1024 regdef = &axp803_regdefs[off]; 1025 break; 1026 case AXP813: 1027 regname = axp813_regdefs[off].name; 1028 regdef = &axp813_regdefs[off]; 1029 break; 1030 } 1031 } 1032 child = ofw_bus_find_child(rnode, 1033 regname); 1034 if (child == 0) 1035 continue; 1036 reg = axp8xx_reg_attach(dev, child, 1037 regdef); 1038 if (reg == NULL) { 1039 device_printf(dev, 1040 "cannot attach regulator %s\n", 1041 regname); 1042 return (ENXIO); 1043 } 1044 sc->regs[i] = reg; 1045 } 1046 } 1047 1048 /* Enable IRQ on short power key press */ 1049 axp8xx_write(dev, AXP_IRQEN1, 0); 1050 axp8xx_write(dev, AXP_IRQEN2, 0); 1051 axp8xx_write(dev, AXP_IRQEN3, 0); 1052 axp8xx_write(dev, AXP_IRQEN4, 0); 1053 axp8xx_write(dev, AXP_IRQEN5, AXP_IRQEN5_POKSIRQ); 1054 axp8xx_write(dev, AXP_IRQEN6, 0); 1055 1056 /* Install interrupt handler */ 1057 error = bus_setup_intr(dev, sc->res, INTR_TYPE_MISC | INTR_MPSAFE, 1058 NULL, axp8xx_intr, dev, &sc->ih); 1059 if (error != 0) { 1060 device_printf(dev, "cannot setup interrupt handler\n"); 1061 return (error); 1062 } 1063 1064 EVENTHANDLER_REGISTER(shutdown_final, axp8xx_shutdown, dev, 1065 SHUTDOWN_PRI_LAST); 1066 1067 sc->gpiodev = gpiobus_attach_bus(dev); 1068 1069 return (0); 1070 } 1071 1072 static device_method_t axp8xx_methods[] = { 1073 /* Device interface */ 1074 DEVMETHOD(device_probe, axp8xx_probe), 1075 DEVMETHOD(device_attach, axp8xx_attach), 1076 1077 /* GPIO interface */ 1078 DEVMETHOD(gpio_get_bus, axp8xx_gpio_get_bus), 1079 DEVMETHOD(gpio_pin_max, axp8xx_gpio_pin_max), 1080 DEVMETHOD(gpio_pin_getname, axp8xx_gpio_pin_getname), 1081 DEVMETHOD(gpio_pin_getcaps, axp8xx_gpio_pin_getcaps), 1082 DEVMETHOD(gpio_pin_getflags, axp8xx_gpio_pin_getflags), 1083 DEVMETHOD(gpio_pin_setflags, axp8xx_gpio_pin_setflags), 1084 DEVMETHOD(gpio_pin_get, axp8xx_gpio_pin_get), 1085 DEVMETHOD(gpio_pin_set, axp8xx_gpio_pin_set), 1086 DEVMETHOD(gpio_pin_toggle, axp8xx_gpio_pin_toggle), 1087 DEVMETHOD(gpio_map_gpios, axp8xx_gpio_map_gpios), 1088 1089 /* Regdev interface */ 1090 DEVMETHOD(regdev_map, axp8xx_regdev_map), 1091 1092 /* OFW bus interface */ 1093 DEVMETHOD(ofw_bus_get_node, axp8xx_get_node), 1094 1095 DEVMETHOD_END 1096 }; 1097 1098 static driver_t axp8xx_driver = { 1099 "axp8xx_pmu", 1100 axp8xx_methods, 1101 sizeof(struct axp8xx_softc), 1102 }; 1103 1104 static devclass_t axp8xx_devclass; 1105 extern devclass_t ofwgpiobus_devclass, gpioc_devclass; 1106 extern driver_t ofw_gpiobus_driver, gpioc_driver; 1107 1108 EARLY_DRIVER_MODULE(axp8xx, iicbus, axp8xx_driver, axp8xx_devclass, 0, 0, 1109 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LAST); 1110 EARLY_DRIVER_MODULE(ofw_gpiobus, axp8xx_pmu, ofw_gpiobus_driver, 1111 ofwgpiobus_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LAST); 1112 DRIVER_MODULE(gpioc, axp8xx_pmu, gpioc_driver, gpioc_devclass, 0, 0); 1113 MODULE_VERSION(axp8xx, 1); 1114 MODULE_DEPEND(axp8xx, iicbus, 1, 1, 1); 1115