1 /*- 2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 /* 30 * Allwinner USB PHY 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/bus.h> 39 #include <sys/rman.h> 40 #include <sys/kernel.h> 41 #include <sys/module.h> 42 #include <sys/gpio.h> 43 #include <machine/bus.h> 44 45 #include <dev/ofw/ofw_bus.h> 46 #include <dev/ofw/ofw_bus_subr.h> 47 #include <dev/gpio/gpiobusvar.h> 48 49 #include <dev/extres/clk/clk.h> 50 #include <dev/extres/hwreset/hwreset.h> 51 #include <dev/extres/regulator/regulator.h> 52 #include <dev/extres/phy/phy_usb.h> 53 54 #include "phynode_if.h" 55 56 enum awusbphy_type { 57 AWUSBPHY_TYPE_A10 = 1, 58 AWUSBPHY_TYPE_A13, 59 AWUSBPHY_TYPE_A20, 60 AWUSBPHY_TYPE_A31, 61 AWUSBPHY_TYPE_H3, 62 AWUSBPHY_TYPE_A64, 63 AWUSBPHY_TYPE_A83T 64 }; 65 66 struct aw_usbphy_conf { 67 int num_phys; 68 enum awusbphy_type phy_type; 69 bool pmu_unk1; 70 bool phy0_route; 71 }; 72 73 static const struct aw_usbphy_conf a10_usbphy_conf = { 74 .num_phys = 3, 75 .phy_type = AWUSBPHY_TYPE_A10, 76 .pmu_unk1 = false, 77 .phy0_route = false, 78 }; 79 80 static const struct aw_usbphy_conf a13_usbphy_conf = { 81 .num_phys = 2, 82 .phy_type = AWUSBPHY_TYPE_A13, 83 .pmu_unk1 = false, 84 .phy0_route = false, 85 }; 86 87 static const struct aw_usbphy_conf a20_usbphy_conf = { 88 .num_phys = 3, 89 .phy_type = AWUSBPHY_TYPE_A20, 90 .pmu_unk1 = false, 91 .phy0_route = false, 92 }; 93 94 static const struct aw_usbphy_conf a31_usbphy_conf = { 95 .num_phys = 3, 96 .phy_type = AWUSBPHY_TYPE_A31, 97 .pmu_unk1 = false, 98 .phy0_route = false, 99 }; 100 101 static const struct aw_usbphy_conf h3_usbphy_conf = { 102 .num_phys = 4, 103 .phy_type = AWUSBPHY_TYPE_H3, 104 .pmu_unk1 = true, 105 .phy0_route = false, 106 }; 107 108 static const struct aw_usbphy_conf a64_usbphy_conf = { 109 .num_phys = 2, 110 .phy_type = AWUSBPHY_TYPE_A64, 111 .pmu_unk1 = true, 112 .phy0_route = true, 113 }; 114 115 static const struct aw_usbphy_conf a83t_usbphy_conf = { 116 .num_phys = 3, 117 .phy_type = AWUSBPHY_TYPE_A83T, 118 .pmu_unk1 = false, 119 .phy0_route = false, 120 }; 121 122 static struct ofw_compat_data compat_data[] = { 123 { "allwinner,sun4i-a10-usb-phy", (uintptr_t)&a10_usbphy_conf }, 124 { "allwinner,sun5i-a13-usb-phy", (uintptr_t)&a13_usbphy_conf }, 125 { "allwinner,sun6i-a31-usb-phy", (uintptr_t)&a31_usbphy_conf }, 126 { "allwinner,sun7i-a20-usb-phy", (uintptr_t)&a20_usbphy_conf }, 127 { "allwinner,sun8i-h3-usb-phy", (uintptr_t)&h3_usbphy_conf }, 128 { "allwinner,sun50i-a64-usb-phy", (uintptr_t)&a64_usbphy_conf }, 129 { "allwinner,sun8i-a83t-usb-phy", (uintptr_t)&a83t_usbphy_conf }, 130 { NULL, 0 } 131 }; 132 133 struct awusbphy_softc { 134 struct resource * phy_ctrl; 135 struct resource ** pmu; 136 regulator_t * reg; 137 gpio_pin_t id_det_pin; 138 int id_det_valid; 139 gpio_pin_t vbus_det_pin; 140 int vbus_det_valid; 141 struct aw_usbphy_conf *phy_conf; 142 int mode; 143 }; 144 145 /* Phy class and methods. */ 146 static int awusbphy_phy_enable(struct phynode *phy, bool enable); 147 static int awusbphy_get_mode(struct phynode *phy, int *mode); 148 static int awusbphy_set_mode(struct phynode *phy, int mode); 149 static phynode_usb_method_t awusbphy_phynode_methods[] = { 150 PHYNODEMETHOD(phynode_enable, awusbphy_phy_enable), 151 PHYNODEMETHOD(phynode_usb_get_mode, awusbphy_get_mode), 152 PHYNODEMETHOD(phynode_usb_set_mode, awusbphy_set_mode), 153 154 PHYNODEMETHOD_END 155 }; 156 DEFINE_CLASS_1(awusbphy_phynode, awusbphy_phynode_class, awusbphy_phynode_methods, 157 sizeof(struct phynode_usb_sc), phynode_usb_class); 158 159 #define RD4(res, o) bus_read_4(res, (o)) 160 #define WR4(res, o, v) bus_write_4(res, (o), (v)) 161 #define CLR4(res, o, m) WR4(res, o, RD4(res, o) & ~(m)) 162 #define SET4(res, o, m) WR4(res, o, RD4(res, o) | (m)) 163 164 #define OTG_PHY_CFG 0x20 165 #define OTG_PHY_ROUTE_OTG (1 << 0) 166 #define PMU_IRQ_ENABLE 0x00 167 #define PMU_AHB_INCR8 (1 << 10) 168 #define PMU_AHB_INCR4 (1 << 9) 169 #define PMU_AHB_INCRX_ALIGN (1 << 8) 170 #define PMU_ULPI_BYPASS (1 << 0) 171 #define PMU_UNK_H3 0x10 172 #define PMU_UNK_H3_CLR 0x2 173 #define PHY_CSR 0x00 174 #define ID_PULLUP_EN (1 << 17) 175 #define DPDM_PULLUP_EN (1 << 16) 176 #define FORCE_ID (0x3 << 14) 177 #define FORCE_ID_SHIFT 14 178 #define FORCE_ID_LOW 2 179 #define FORCE_VBUS_VALID (0x3 << 12) 180 #define FORCE_VBUS_VALID_SHIFT 12 181 #define FORCE_VBUS_VALID_HIGH 3 182 #define VBUS_CHANGE_DET (1 << 6) 183 #define ID_CHANGE_DET (1 << 5) 184 #define DPDM_CHANGE_DET (1 << 4) 185 186 static void 187 awusbphy_configure(device_t dev, int phyno) 188 { 189 struct awusbphy_softc *sc; 190 191 sc = device_get_softc(dev); 192 193 if (sc->pmu[phyno] == NULL) 194 return; 195 196 if (sc->phy_conf->pmu_unk1 == true) 197 CLR4(sc->pmu[phyno], PMU_UNK_H3, PMU_UNK_H3_CLR); 198 199 SET4(sc->pmu[phyno], PMU_IRQ_ENABLE, PMU_ULPI_BYPASS | 200 PMU_AHB_INCR8 | PMU_AHB_INCR4 | PMU_AHB_INCRX_ALIGN); 201 } 202 203 static int 204 awusbphy_init(device_t dev) 205 { 206 struct awusbphy_softc *sc; 207 phandle_t node; 208 char pname[20]; 209 int error, off, rid; 210 regulator_t reg; 211 hwreset_t rst; 212 clk_t clk; 213 214 sc = device_get_softc(dev); 215 node = ofw_bus_get_node(dev); 216 217 sc->phy_conf = (struct aw_usbphy_conf *)ofw_bus_search_compatible(dev, compat_data)->ocd_data; 218 219 /* Get phy_ctrl region */ 220 if (ofw_bus_find_string_index(node, "reg-names", "phy_ctrl", &rid) != 0) { 221 device_printf(dev, "Cannot locate phy control resource\n"); 222 return (ENXIO); 223 } 224 sc->phy_ctrl = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 225 RF_ACTIVE); 226 if (sc->phy_ctrl == NULL) { 227 device_printf(dev, "Cannot allocate resource\n"); 228 return (ENXIO); 229 } 230 231 /* Enable clocks */ 232 for (off = 0; clk_get_by_ofw_index(dev, 0, off, &clk) == 0; off++) { 233 error = clk_enable(clk); 234 if (error != 0) { 235 device_printf(dev, "couldn't enable clock %s\n", 236 clk_get_name(clk)); 237 return (error); 238 } 239 } 240 241 /* De-assert resets */ 242 for (off = 0; hwreset_get_by_ofw_idx(dev, 0, off, &rst) == 0; off++) { 243 error = hwreset_deassert(rst); 244 if (error != 0) { 245 device_printf(dev, "couldn't de-assert reset %d\n", 246 off); 247 return (error); 248 } 249 } 250 251 /* Get GPIOs */ 252 error = gpio_pin_get_by_ofw_property(dev, node, "usb0_id_det-gpios", 253 &sc->id_det_pin); 254 if (error == 0) 255 sc->id_det_valid = 1; 256 error = gpio_pin_get_by_ofw_property(dev, node, "usb0_vbus_det-gpios", 257 &sc->vbus_det_pin); 258 if (error == 0) 259 sc->vbus_det_valid = 1; 260 261 sc->reg = malloc(sizeof(*(sc->reg)) * sc->phy_conf->num_phys, M_DEVBUF, 262 M_WAITOK | M_ZERO); 263 sc->pmu = malloc(sizeof(*(sc->pmu)) * sc->phy_conf->num_phys, M_DEVBUF, 264 M_WAITOK | M_ZERO); 265 /* Get regulators */ 266 for (off = 0; off < sc->phy_conf->num_phys; off++) { 267 snprintf(pname, sizeof(pname), "usb%d_vbus-supply", off); 268 if (regulator_get_by_ofw_property(dev, 0, pname, ®) == 0) 269 sc->reg[off] = reg; 270 271 snprintf(pname, sizeof(pname), "pmu%d", off); 272 if (ofw_bus_find_string_index(node, "reg-names", 273 pname, &rid) != 0) 274 continue; 275 276 sc->pmu[off] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 277 RF_ACTIVE); 278 if (sc->pmu[off] == NULL) { 279 device_printf(dev, "Cannot allocate resource\n"); 280 return (ENXIO); 281 } 282 } 283 284 return (0); 285 } 286 287 static int 288 awusbphy_vbus_detect(device_t dev, int *val) 289 { 290 struct awusbphy_softc *sc; 291 bool active; 292 int error; 293 294 sc = device_get_softc(dev); 295 296 if (sc->vbus_det_valid) { 297 error = gpio_pin_is_active(sc->vbus_det_pin, &active); 298 if (error != 0) { 299 device_printf(dev, "Cannot get status of id pin %d\n", 300 error); 301 return (error); 302 } 303 *val = active; 304 return (0); 305 } 306 307 *val = 0; 308 return (0); 309 } 310 311 static int 312 awusbphy_phy_enable(struct phynode *phynode, bool enable) 313 { 314 device_t dev; 315 intptr_t phy; 316 struct awusbphy_softc *sc; 317 regulator_t reg; 318 int error, vbus_det; 319 320 dev = phynode_get_device(phynode); 321 phy = phynode_get_id(phynode); 322 sc = device_get_softc(dev); 323 324 if (phy < 0 || phy >= sc->phy_conf->num_phys) 325 return (ERANGE); 326 327 /* Configure PHY */ 328 awusbphy_configure(dev, phy); 329 330 /* Regulators are optional. If not found, return success. */ 331 reg = sc->reg[phy]; 332 if (reg == NULL) 333 return (0); 334 335 if (phy == 0) { 336 /* If an external vbus is detected, do not enable phy 0 */ 337 error = awusbphy_vbus_detect(dev, &vbus_det); 338 if (error) 339 goto out; 340 341 if (vbus_det == 1) { 342 if (bootverbose) 343 device_printf(dev, "External VBUS detected, not enabling the regulator\n"); 344 345 return (0); 346 } 347 } 348 if (enable) { 349 /* Depending on the PHY we need to route OTG to OHCI/EHCI */ 350 error = regulator_enable(reg); 351 } else 352 error = regulator_disable(reg); 353 354 out: 355 if (error != 0) { 356 device_printf(dev, 357 "couldn't %s regulator for phy %jd\n", 358 enable ? "enable" : "disable", (intmax_t)phy); 359 return (error); 360 } 361 362 return (0); 363 } 364 365 static int 366 awusbphy_get_mode(struct phynode *phynode, int *mode) 367 { 368 struct awusbphy_softc *sc; 369 device_t dev; 370 371 dev = phynode_get_device(phynode); 372 sc = device_get_softc(dev); 373 374 *mode = sc->mode; 375 376 return (0); 377 } 378 379 static int 380 awusbphy_set_mode(struct phynode *phynode, int mode) 381 { 382 device_t dev; 383 intptr_t phy; 384 struct awusbphy_softc *sc; 385 uint32_t val; 386 int error, vbus_det; 387 388 dev = phynode_get_device(phynode); 389 phy = phynode_get_id(phynode); 390 sc = device_get_softc(dev); 391 392 if (phy != 0) { 393 if (mode != PHY_USB_MODE_HOST) 394 return (EINVAL); 395 return (0); 396 } 397 398 switch (mode) { 399 case PHY_USB_MODE_HOST: 400 val = bus_read_4(sc->phy_ctrl, PHY_CSR); 401 val &= ~(VBUS_CHANGE_DET | ID_CHANGE_DET | DPDM_CHANGE_DET); 402 val |= (ID_PULLUP_EN | DPDM_PULLUP_EN); 403 val &= ~FORCE_ID; 404 val |= (FORCE_ID_LOW << FORCE_ID_SHIFT); 405 val &= ~FORCE_VBUS_VALID; 406 val |= (FORCE_VBUS_VALID_HIGH << FORCE_VBUS_VALID_SHIFT); 407 bus_write_4(sc->phy_ctrl, PHY_CSR, val); 408 if (sc->phy_conf->phy0_route == true) { 409 error = awusbphy_vbus_detect(dev, &vbus_det); 410 if (error) 411 goto out; 412 if (vbus_det == 0) 413 CLR4(sc->phy_ctrl, OTG_PHY_CFG, 414 OTG_PHY_ROUTE_OTG); 415 else 416 SET4(sc->phy_ctrl, OTG_PHY_CFG, 417 OTG_PHY_ROUTE_OTG); 418 } 419 break; 420 case PHY_USB_MODE_OTG: 421 /* TODO */ 422 break; 423 } 424 425 sc->mode = mode; 426 427 428 out: 429 return (0); 430 } 431 432 static int 433 awusbphy_probe(device_t dev) 434 { 435 if (!ofw_bus_status_okay(dev)) 436 return (ENXIO); 437 438 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 439 return (ENXIO); 440 441 device_set_desc(dev, "Allwinner USB PHY"); 442 return (BUS_PROBE_DEFAULT); 443 } 444 445 static int 446 awusbphy_attach(device_t dev) 447 { 448 int error; 449 struct phynode *phynode; 450 struct phynode_init_def phy_init; 451 struct awusbphy_softc *sc; 452 int i; 453 454 sc = device_get_softc(dev); 455 error = awusbphy_init(dev); 456 if (error) { 457 device_printf(dev, "failed to initialize USB PHY, error %d\n", 458 error); 459 return (error); 460 } 461 462 /* Create and register phys. */ 463 for (i = 0; i < sc->phy_conf->num_phys; i++) { 464 bzero(&phy_init, sizeof(phy_init)); 465 phy_init.id = i; 466 phy_init.ofw_node = ofw_bus_get_node(dev); 467 phynode = phynode_create(dev, &awusbphy_phynode_class, 468 &phy_init); 469 if (phynode == NULL) { 470 device_printf(dev, "failed to create USB PHY\n"); 471 return (ENXIO); 472 } 473 if (phynode_register(phynode) == NULL) { 474 device_printf(dev, "failed to create USB PHY\n"); 475 return (ENXIO); 476 } 477 } 478 479 return (error); 480 } 481 482 static device_method_t awusbphy_methods[] = { 483 /* Device interface */ 484 DEVMETHOD(device_probe, awusbphy_probe), 485 DEVMETHOD(device_attach, awusbphy_attach), 486 487 DEVMETHOD_END 488 }; 489 490 static driver_t awusbphy_driver = { 491 "awusbphy", 492 awusbphy_methods, 493 sizeof(struct awusbphy_softc) 494 }; 495 496 static devclass_t awusbphy_devclass; 497 /* aw_usbphy needs to come up after regulators/gpio/etc, but before ehci/ohci */ 498 EARLY_DRIVER_MODULE(awusbphy, simplebus, awusbphy_driver, awusbphy_devclass, 499 0, 0, BUS_PASS_SUPPORTDEV + BUS_PASS_ORDER_MIDDLE); 500 MODULE_VERSION(awusbphy, 1); 501