1 /*- 2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 /* 30 * Allwinner USB PHY 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/bus.h> 39 #include <sys/rman.h> 40 #include <sys/kernel.h> 41 #include <sys/module.h> 42 #include <sys/gpio.h> 43 #include <machine/bus.h> 44 45 #include <dev/ofw/ofw_bus.h> 46 #include <dev/ofw/ofw_bus_subr.h> 47 #include <dev/gpio/gpiobusvar.h> 48 49 #include <dev/extres/clk/clk.h> 50 #include <dev/extres/hwreset/hwreset.h> 51 #include <dev/extres/regulator/regulator.h> 52 #include <dev/extres/phy/phy.h> 53 54 #include "phynode_if.h" 55 56 enum awusbphy_type { 57 AWUSBPHY_TYPE_A10 = 1, 58 AWUSBPHY_TYPE_A13, 59 AWUSBPHY_TYPE_A20, 60 AWUSBPHY_TYPE_A31, 61 AWUSBPHY_TYPE_H3, 62 AWUSBPHY_TYPE_A64, 63 AWUSBPHY_TYPE_A83T 64 }; 65 66 struct aw_usbphy_conf { 67 int num_phys; 68 enum awusbphy_type phy_type; 69 bool pmu_unk1; 70 bool phy0_route; 71 }; 72 73 static const struct aw_usbphy_conf a10_usbphy_conf = { 74 .num_phys = 3, 75 .phy_type = AWUSBPHY_TYPE_A10, 76 .pmu_unk1 = false, 77 .phy0_route = false, 78 }; 79 80 static const struct aw_usbphy_conf a13_usbphy_conf = { 81 .num_phys = 2, 82 .phy_type = AWUSBPHY_TYPE_A13, 83 .pmu_unk1 = false, 84 .phy0_route = false, 85 }; 86 87 static const struct aw_usbphy_conf a20_usbphy_conf = { 88 .num_phys = 3, 89 .phy_type = AWUSBPHY_TYPE_A20, 90 .pmu_unk1 = false, 91 .phy0_route = false, 92 }; 93 94 static const struct aw_usbphy_conf a31_usbphy_conf = { 95 .num_phys = 3, 96 .phy_type = AWUSBPHY_TYPE_A31, 97 .pmu_unk1 = false, 98 .phy0_route = false, 99 }; 100 101 static const struct aw_usbphy_conf h3_usbphy_conf = { 102 .num_phys = 4, 103 .phy_type = AWUSBPHY_TYPE_H3, 104 .pmu_unk1 = true, 105 .phy0_route = false, 106 }; 107 108 static const struct aw_usbphy_conf a64_usbphy_conf = { 109 .num_phys = 2, 110 .phy_type = AWUSBPHY_TYPE_A64, 111 .pmu_unk1 = true, 112 .phy0_route = true, 113 }; 114 115 static const struct aw_usbphy_conf a83t_usbphy_conf = { 116 .num_phys = 3, 117 .phy_type = AWUSBPHY_TYPE_A83T, 118 .pmu_unk1 = false, 119 .phy0_route = false, 120 }; 121 122 static struct ofw_compat_data compat_data[] = { 123 { "allwinner,sun4i-a10-usb-phy", (uintptr_t)&a10_usbphy_conf }, 124 { "allwinner,sun5i-a13-usb-phy", (uintptr_t)&a13_usbphy_conf }, 125 { "allwinner,sun6i-a31-usb-phy", (uintptr_t)&a31_usbphy_conf }, 126 { "allwinner,sun7i-a20-usb-phy", (uintptr_t)&a20_usbphy_conf }, 127 { "allwinner,sun8i-h3-usb-phy", (uintptr_t)&h3_usbphy_conf }, 128 { "allwinner,sun50i-a64-usb-phy", (uintptr_t)&a64_usbphy_conf }, 129 { "allwinner,sun8i-a83t-usb-phy", (uintptr_t)&a83t_usbphy_conf }, 130 { NULL, 0 } 131 }; 132 133 struct awusbphy_softc { 134 struct resource * phy_ctrl; 135 struct resource ** pmu; 136 regulator_t * reg; 137 gpio_pin_t id_det_pin; 138 int id_det_valid; 139 gpio_pin_t vbus_det_pin; 140 int vbus_det_valid; 141 struct aw_usbphy_conf *phy_conf; 142 }; 143 144 /* Phy class and methods. */ 145 static int awusbphy_phy_enable(struct phynode *phy, bool enable); 146 static phynode_method_t awusbphy_phynode_methods[] = { 147 PHYNODEMETHOD(phynode_enable, awusbphy_phy_enable), 148 149 PHYNODEMETHOD_END 150 }; 151 DEFINE_CLASS_1(awusbphy_phynode, awusbphy_phynode_class, awusbphy_phynode_methods, 152 0, phynode_class); 153 154 #define RD4(res, o) bus_read_4(res, (o)) 155 #define WR4(res, o, v) bus_write_4(res, (o), (v)) 156 #define CLR4(res, o, m) WR4(res, o, RD4(res, o) & ~(m)) 157 #define SET4(res, o, m) WR4(res, o, RD4(res, o) | (m)) 158 159 #define OTG_PHY_CFG 0x20 160 #define OTG_PHY_ROUTE_OTG (1 << 0) 161 #define PMU_IRQ_ENABLE 0x00 162 #define PMU_AHB_INCR8 (1 << 10) 163 #define PMU_AHB_INCR4 (1 << 9) 164 #define PMU_AHB_INCRX_ALIGN (1 << 8) 165 #define PMU_ULPI_BYPASS (1 << 0) 166 #define PMU_UNK_H3 0x10 167 #define PMU_UNK_H3_CLR 0x2 168 169 static void 170 awusbphy_configure(device_t dev, int phyno) 171 { 172 struct awusbphy_softc *sc; 173 174 sc = device_get_softc(dev); 175 176 if (sc->pmu[phyno] == NULL) 177 return; 178 179 if (sc->phy_conf->pmu_unk1 == true) 180 CLR4(sc->pmu[phyno], PMU_UNK_H3, PMU_UNK_H3_CLR); 181 182 SET4(sc->pmu[phyno], PMU_IRQ_ENABLE, PMU_ULPI_BYPASS | 183 PMU_AHB_INCR8 | PMU_AHB_INCR4 | PMU_AHB_INCRX_ALIGN); 184 } 185 186 static int 187 awusbphy_init(device_t dev) 188 { 189 struct awusbphy_softc *sc; 190 phandle_t node; 191 char pname[20]; 192 int error, off, rid; 193 regulator_t reg; 194 hwreset_t rst; 195 clk_t clk; 196 197 sc = device_get_softc(dev); 198 node = ofw_bus_get_node(dev); 199 200 sc->phy_conf = (struct aw_usbphy_conf *)ofw_bus_search_compatible(dev, compat_data)->ocd_data; 201 202 /* Get phy_ctrl region */ 203 if (ofw_bus_find_string_index(node, "reg-names", "phy_ctrl", &rid) != 0) { 204 device_printf(dev, "Cannot locate phy control resource\n"); 205 return (ENXIO); 206 } 207 sc->phy_ctrl = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 208 RF_ACTIVE); 209 if (sc->phy_ctrl == NULL) { 210 device_printf(dev, "Cannot allocate resource\n"); 211 return (ENXIO); 212 } 213 214 /* Enable clocks */ 215 for (off = 0; clk_get_by_ofw_index(dev, 0, off, &clk) == 0; off++) { 216 error = clk_enable(clk); 217 if (error != 0) { 218 device_printf(dev, "couldn't enable clock %s\n", 219 clk_get_name(clk)); 220 return (error); 221 } 222 } 223 224 /* De-assert resets */ 225 for (off = 0; hwreset_get_by_ofw_idx(dev, 0, off, &rst) == 0; off++) { 226 error = hwreset_deassert(rst); 227 if (error != 0) { 228 device_printf(dev, "couldn't de-assert reset %d\n", 229 off); 230 return (error); 231 } 232 } 233 234 /* Get GPIOs */ 235 error = gpio_pin_get_by_ofw_property(dev, node, "usb0_id_det-gpios", 236 &sc->id_det_pin); 237 if (error == 0) 238 sc->id_det_valid = 1; 239 error = gpio_pin_get_by_ofw_property(dev, node, "usb0_vbus_det-gpios", 240 &sc->vbus_det_pin); 241 if (error == 0) 242 sc->vbus_det_valid = 1; 243 244 sc->reg = malloc(sizeof(*(sc->reg)) * sc->phy_conf->num_phys, M_DEVBUF, 245 M_WAITOK | M_ZERO); 246 sc->pmu = malloc(sizeof(*(sc->pmu)) * sc->phy_conf->num_phys, M_DEVBUF, 247 M_WAITOK | M_ZERO); 248 /* Get regulators */ 249 for (off = 0; off < sc->phy_conf->num_phys; off++) { 250 snprintf(pname, sizeof(pname), "usb%d_vbus-supply", off); 251 if (regulator_get_by_ofw_property(dev, 0, pname, ®) == 0) 252 sc->reg[off] = reg; 253 254 snprintf(pname, sizeof(pname), "pmu%d", off); 255 if (ofw_bus_find_string_index(node, "reg-names", 256 pname, &rid) != 0) 257 continue; 258 259 sc->pmu[off] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 260 RF_ACTIVE); 261 if (sc->pmu[off] == NULL) { 262 device_printf(dev, "Cannot allocate resource\n"); 263 return (ENXIO); 264 } 265 } 266 267 return (0); 268 } 269 270 static int 271 awusbphy_vbus_detect(device_t dev, int *val) 272 { 273 struct awusbphy_softc *sc; 274 bool active; 275 int error; 276 277 sc = device_get_softc(dev); 278 279 if (sc->vbus_det_valid) { 280 error = gpio_pin_is_active(sc->vbus_det_pin, &active); 281 if (error != 0) { 282 device_printf(dev, "Cannot get status of id pin %d\n", 283 error); 284 return (error); 285 } 286 *val = active; 287 return (0); 288 } 289 290 *val = 1; 291 return (0); 292 } 293 294 static int 295 awusbphy_phy_enable(struct phynode *phynode, bool enable) 296 { 297 device_t dev; 298 intptr_t phy; 299 struct awusbphy_softc *sc; 300 regulator_t reg; 301 int error, vbus_det; 302 303 dev = phynode_get_device(phynode); 304 phy = phynode_get_id(phynode); 305 sc = device_get_softc(dev); 306 307 if (phy < 0 || phy >= sc->phy_conf->num_phys) 308 return (ERANGE); 309 310 /* Configure PHY */ 311 awusbphy_configure(dev, phy); 312 313 /* Regulators are optional. If not found, return success. */ 314 reg = sc->reg[phy]; 315 if (reg == NULL) 316 return (0); 317 318 if (enable) { 319 /* If an external vbus is detected, do not enable phy 0 */ 320 if (phy == 0) { 321 error = awusbphy_vbus_detect(dev, &vbus_det); 322 if (error) 323 goto out; 324 325 /* Depending on the PHY we need to route OTG to OHCI/EHCI */ 326 if (sc->phy_conf->phy0_route == true) { 327 if (vbus_det == 0) 328 /* Host mode */ 329 CLR4(sc->phy_ctrl, OTG_PHY_CFG, 330 OTG_PHY_ROUTE_OTG); 331 else 332 /* Peripheral mode */ 333 SET4(sc->phy_ctrl, OTG_PHY_CFG, 334 OTG_PHY_ROUTE_OTG); 335 } 336 if (vbus_det == 1) 337 return (0); 338 } else 339 error = 0; 340 if (error == 0) 341 error = regulator_enable(reg); 342 } else 343 error = regulator_disable(reg); 344 345 out: 346 if (error != 0) { 347 device_printf(dev, 348 "couldn't %s regulator for phy %jd\n", 349 enable ? "enable" : "disable", (intmax_t)phy); 350 return (error); 351 } 352 353 return (0); 354 } 355 356 static int 357 awusbphy_probe(device_t dev) 358 { 359 if (!ofw_bus_status_okay(dev)) 360 return (ENXIO); 361 362 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 363 return (ENXIO); 364 365 device_set_desc(dev, "Allwinner USB PHY"); 366 return (BUS_PROBE_DEFAULT); 367 } 368 369 static int 370 awusbphy_attach(device_t dev) 371 { 372 int error; 373 struct phynode *phynode; 374 struct phynode_init_def phy_init; 375 struct awusbphy_softc *sc; 376 int i; 377 378 sc = device_get_softc(dev); 379 error = awusbphy_init(dev); 380 if (error) { 381 device_printf(dev, "failed to initialize USB PHY, error %d\n", 382 error); 383 return (error); 384 } 385 386 /* Create and register phys. */ 387 for (i = 0; i < sc->phy_conf->num_phys; i++) { 388 bzero(&phy_init, sizeof(phy_init)); 389 phy_init.id = i; 390 phy_init.ofw_node = ofw_bus_get_node(dev); 391 phynode = phynode_create(dev, &awusbphy_phynode_class, 392 &phy_init); 393 if (phynode == NULL) { 394 device_printf(dev, "failed to create USB PHY\n"); 395 return (ENXIO); 396 } 397 if (phynode_register(phynode) == NULL) { 398 device_printf(dev, "failed to create USB PHY\n"); 399 return (ENXIO); 400 } 401 } 402 403 return (error); 404 } 405 406 static device_method_t awusbphy_methods[] = { 407 /* Device interface */ 408 DEVMETHOD(device_probe, awusbphy_probe), 409 DEVMETHOD(device_attach, awusbphy_attach), 410 411 DEVMETHOD_END 412 }; 413 414 static driver_t awusbphy_driver = { 415 "awusbphy", 416 awusbphy_methods, 417 sizeof(struct awusbphy_softc) 418 }; 419 420 static devclass_t awusbphy_devclass; 421 /* aw_usbphy needs to come up after regulators/gpio/etc, but before ehci/ohci */ 422 EARLY_DRIVER_MODULE(awusbphy, simplebus, awusbphy_driver, awusbphy_devclass, 423 0, 0, BUS_PASS_SUPPORTDEV + BUS_PASS_ORDER_MIDDLE); 424 MODULE_VERSION(awusbphy, 1); 425