1 /*- 2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 /* 30 * Allwinner thermal sensor controller 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/eventhandler.h> 39 #include <sys/bus.h> 40 #include <sys/rman.h> 41 #include <sys/kernel.h> 42 #include <sys/sysctl.h> 43 #include <sys/reboot.h> 44 #include <sys/module.h> 45 #include <sys/cpu.h> 46 #include <sys/taskqueue.h> 47 #include <machine/bus.h> 48 49 #include <dev/ofw/ofw_bus.h> 50 #include <dev/ofw/ofw_bus_subr.h> 51 52 #include <dev/extres/clk/clk.h> 53 #include <dev/extres/hwreset/hwreset.h> 54 #include <dev/extres/nvmem/nvmem.h> 55 56 #include <arm/allwinner/aw_sid.h> 57 58 #include "cpufreq_if.h" 59 #include "nvmem_if.h" 60 61 #define THS_CTRL0 0x00 62 #define THS_CTRL1 0x04 63 #define ADC_CALI_EN (1 << 17) 64 #define THS_CTRL2 0x40 65 #define SENSOR_ACQ1_SHIFT 16 66 #define SENSOR2_EN (1 << 2) 67 #define SENSOR1_EN (1 << 1) 68 #define SENSOR0_EN (1 << 0) 69 #define THS_INTC 0x44 70 #define THS_THERMAL_PER_SHIFT 12 71 #define THS_INTS 0x48 72 #define THS2_DATA_IRQ_STS (1 << 10) 73 #define THS1_DATA_IRQ_STS (1 << 9) 74 #define THS0_DATA_IRQ_STS (1 << 8) 75 #define SHUT_INT2_STS (1 << 6) 76 #define SHUT_INT1_STS (1 << 5) 77 #define SHUT_INT0_STS (1 << 4) 78 #define ALARM_INT2_STS (1 << 2) 79 #define ALARM_INT1_STS (1 << 1) 80 #define ALARM_INT0_STS (1 << 0) 81 #define THS_ALARM0_CTRL 0x50 82 #define ALARM_T_HOT_MASK 0xfff 83 #define ALARM_T_HOT_SHIFT 16 84 #define ALARM_T_HYST_MASK 0xfff 85 #define ALARM_T_HYST_SHIFT 0 86 #define THS_SHUTDOWN0_CTRL 0x60 87 #define SHUT_T_HOT_MASK 0xfff 88 #define SHUT_T_HOT_SHIFT 16 89 #define THS_FILTER 0x70 90 #define THS_CALIB0 0x74 91 #define THS_CALIB1 0x78 92 #define THS_DATA0 0x80 93 #define THS_DATA1 0x84 94 #define THS_DATA2 0x88 95 #define DATA_MASK 0xfff 96 97 #define A83T_CLK_RATE 24000000 98 #define A83T_ADC_ACQUIRE_TIME 23 /* 24Mhz/(23 + 1) = 1us */ 99 #define A83T_THERMAL_PER 1 /* 4096 * (1 + 1) / 24Mhz = 341 us */ 100 #define A83T_FILTER 0x5 /* Filter enabled, avg of 4 */ 101 #define A83T_TEMP_BASE 2719000 102 #define A83T_TEMP_MUL 1000 103 #define A83T_TEMP_DIV 14186 104 105 #define A64_CLK_RATE 4000000 106 #define A64_ADC_ACQUIRE_TIME 400 /* 4Mhz/(400 + 1) = 100 us */ 107 #define A64_THERMAL_PER 24 /* 4096 * (24 + 1) / 4Mhz = 25.6 ms */ 108 #define A64_FILTER 0x6 /* Filter enabled, avg of 8 */ 109 #define A64_TEMP_BASE 2170000 110 #define A64_TEMP_MUL 1000 111 #define A64_TEMP_DIV 8560 112 113 #define H3_CLK_RATE 4000000 114 #define H3_ADC_ACQUIRE_TIME 0x3f 115 #define H3_THERMAL_PER 401 116 #define H3_FILTER 0x6 /* Filter enabled, avg of 8 */ 117 #define H3_TEMP_BASE 217 118 #define H3_TEMP_MUL 1000 119 #define H3_TEMP_DIV 8253 120 #define H3_TEMP_MINUS 1794000 121 #define H3_INIT_ALARM 90 /* degC */ 122 #define H3_INIT_SHUT 105 /* degC */ 123 124 #define H5_CLK_RATE 24000000 125 #define H5_ADC_ACQUIRE_TIME 479 /* 24Mhz/479 = 20us */ 126 #define H5_THERMAL_PER 58 /* 4096 * (58 + 1) / 24Mhz = 10ms */ 127 #define H5_FILTER 0x6 /* Filter enabled, avg of 8 */ 128 #define H5_TEMP_BASE 233832448 129 #define H5_TEMP_MUL 124885 130 #define H5_TEMP_DIV 20 131 #define H5_TEMP_BASE_CPU 271581184 132 #define H5_TEMP_MUL_CPU 152253 133 #define H5_TEMP_BASE_GPU 289406976 134 #define H5_TEMP_MUL_GPU 166724 135 #define H5_INIT_CPU_ALARM 80 /* degC */ 136 #define H5_INIT_CPU_SHUT 96 /* degC */ 137 #define H5_INIT_GPU_ALARM 84 /* degC */ 138 #define H5_INIT_GPU_SHUT 100 /* degC */ 139 140 #define TEMP_C_TO_K 273 141 #define SENSOR_ENABLE_ALL (SENSOR0_EN|SENSOR1_EN|SENSOR2_EN) 142 #define SHUT_INT_ALL (SHUT_INT0_STS|SHUT_INT1_STS|SHUT_INT2_STS) 143 #define ALARM_INT_ALL (ALARM_INT0_STS) 144 145 #define MAX_SENSORS 3 146 #define MAX_CF_LEVELS 64 147 148 #define THROTTLE_ENABLE_DEFAULT 1 149 150 /* Enable thermal throttling */ 151 static int aw_thermal_throttle_enable = THROTTLE_ENABLE_DEFAULT; 152 TUNABLE_INT("hw.aw_thermal.throttle_enable", &aw_thermal_throttle_enable); 153 154 struct aw_thermal_sensor { 155 const char *name; 156 const char *desc; 157 int init_alarm; 158 int init_shut; 159 }; 160 161 struct aw_thermal_config { 162 struct aw_thermal_sensor sensors[MAX_SENSORS]; 163 int nsensors; 164 uint64_t clk_rate; 165 uint32_t adc_acquire_time; 166 int adc_cali_en; 167 uint32_t filter; 168 uint32_t thermal_per; 169 int (*to_temp)(uint32_t, int); 170 uint32_t (*to_reg)(int, int); 171 int temp_base; 172 int temp_mul; 173 int temp_div; 174 int calib0, calib1; 175 uint32_t calib0_mask, calib1_mask; 176 }; 177 178 static int 179 a83t_to_temp(uint32_t val, int sensor) 180 { 181 return ((A83T_TEMP_BASE - (val * A83T_TEMP_MUL)) / A83T_TEMP_DIV); 182 } 183 184 static const struct aw_thermal_config a83t_config = { 185 .nsensors = 3, 186 .sensors = { 187 [0] = { 188 .name = "cluster0", 189 .desc = "CPU cluster 0 temperature", 190 }, 191 [1] = { 192 .name = "cluster1", 193 .desc = "CPU cluster 1 temperature", 194 }, 195 [2] = { 196 .name = "gpu", 197 .desc = "GPU temperature", 198 }, 199 }, 200 .clk_rate = A83T_CLK_RATE, 201 .adc_acquire_time = A83T_ADC_ACQUIRE_TIME, 202 .adc_cali_en = 1, 203 .filter = A83T_FILTER, 204 .thermal_per = A83T_THERMAL_PER, 205 .to_temp = a83t_to_temp, 206 .calib0_mask = 0xffffffff, 207 .calib1_mask = 0xffff, 208 }; 209 210 static int 211 a64_to_temp(uint32_t val, int sensor) 212 { 213 return ((A64_TEMP_BASE - (val * A64_TEMP_MUL)) / A64_TEMP_DIV); 214 } 215 216 static const struct aw_thermal_config a64_config = { 217 .nsensors = 3, 218 .sensors = { 219 [0] = { 220 .name = "cpu", 221 .desc = "CPU temperature", 222 }, 223 [1] = { 224 .name = "gpu1", 225 .desc = "GPU temperature 1", 226 }, 227 [2] = { 228 .name = "gpu2", 229 .desc = "GPU temperature 2", 230 }, 231 }, 232 .clk_rate = A64_CLK_RATE, 233 .adc_acquire_time = A64_ADC_ACQUIRE_TIME, 234 .adc_cali_en = 1, 235 .filter = A64_FILTER, 236 .thermal_per = A64_THERMAL_PER, 237 .to_temp = a64_to_temp, 238 .calib0_mask = 0xffffffff, 239 .calib1_mask = 0xffff, 240 }; 241 242 static int 243 h3_to_temp(uint32_t val, int sensor) 244 { 245 return (H3_TEMP_BASE - ((val * H3_TEMP_MUL) / H3_TEMP_DIV)); 246 } 247 248 static uint32_t 249 h3_to_reg(int val, int sensor) 250 { 251 return ((H3_TEMP_MINUS - (val * H3_TEMP_DIV)) / H3_TEMP_MUL); 252 } 253 254 static const struct aw_thermal_config h3_config = { 255 .nsensors = 1, 256 .sensors = { 257 [0] = { 258 .name = "cpu", 259 .desc = "CPU temperature", 260 .init_alarm = H3_INIT_ALARM, 261 .init_shut = H3_INIT_SHUT, 262 }, 263 }, 264 .clk_rate = H3_CLK_RATE, 265 .adc_acquire_time = H3_ADC_ACQUIRE_TIME, 266 .adc_cali_en = 1, 267 .filter = H3_FILTER, 268 .thermal_per = H3_THERMAL_PER, 269 .to_temp = h3_to_temp, 270 .to_reg = h3_to_reg, 271 .calib0_mask = 0xffff, 272 }; 273 274 static int 275 h5_to_temp(uint32_t val, int sensor) 276 { 277 int tmp; 278 279 /* Temp is lower than 70 degrees */ 280 if (val > 0x500) { 281 tmp = H5_TEMP_BASE - (val * H5_TEMP_MUL); 282 tmp >>= H5_TEMP_DIV; 283 return (tmp); 284 } 285 286 if (sensor == 0) 287 tmp = H5_TEMP_BASE_CPU - (val * H5_TEMP_MUL_CPU); 288 else if (sensor == 1) 289 tmp = H5_TEMP_BASE_GPU - (val * H5_TEMP_MUL_GPU); 290 else { 291 printf("Unknown sensor %d\n", sensor); 292 return (val); 293 } 294 295 tmp >>= H5_TEMP_DIV; 296 return (tmp); 297 } 298 299 static uint32_t 300 h5_to_reg(int val, int sensor) 301 { 302 int tmp; 303 304 if (val < 70) { 305 tmp = H5_TEMP_BASE - (val << H5_TEMP_DIV); 306 tmp /= H5_TEMP_MUL; 307 } else { 308 if (sensor == 0) { 309 tmp = H5_TEMP_BASE_CPU - (val << H5_TEMP_DIV); 310 tmp /= H5_TEMP_MUL_CPU; 311 } else if (sensor == 1) { 312 tmp = H5_TEMP_BASE_GPU - (val << H5_TEMP_DIV); 313 tmp /= H5_TEMP_MUL_GPU; 314 } else { 315 printf("Unknown sensor %d\n", sensor); 316 return (val); 317 } 318 } 319 320 return ((uint32_t)tmp); 321 } 322 323 static const struct aw_thermal_config h5_config = { 324 .nsensors = 2, 325 .sensors = { 326 [0] = { 327 .name = "cpu", 328 .desc = "CPU temperature", 329 .init_alarm = H5_INIT_CPU_ALARM, 330 .init_shut = H5_INIT_CPU_SHUT, 331 }, 332 [1] = { 333 .name = "gpu", 334 .desc = "GPU temperature", 335 .init_alarm = H5_INIT_GPU_ALARM, 336 .init_shut = H5_INIT_GPU_SHUT, 337 }, 338 }, 339 .clk_rate = H5_CLK_RATE, 340 .adc_acquire_time = H5_ADC_ACQUIRE_TIME, 341 .filter = H5_FILTER, 342 .thermal_per = H5_THERMAL_PER, 343 .to_temp = h5_to_temp, 344 .to_reg = h5_to_reg, 345 .calib0_mask = 0xffffffff, 346 }; 347 348 static struct ofw_compat_data compat_data[] = { 349 { "allwinner,sun8i-a83t-ths", (uintptr_t)&a83t_config }, 350 { "allwinner,sun8i-h3-ths", (uintptr_t)&h3_config }, 351 { "allwinner,sun50i-a64-ths", (uintptr_t)&a64_config }, 352 { "allwinner,sun50i-h5-ths", (uintptr_t)&h5_config }, 353 { NULL, (uintptr_t)NULL } 354 }; 355 356 #define THS_CONF(d) \ 357 (void *)ofw_bus_search_compatible((d), compat_data)->ocd_data 358 359 struct aw_thermal_softc { 360 device_t dev; 361 struct resource *res[2]; 362 struct aw_thermal_config *conf; 363 364 struct task cf_task; 365 int throttle; 366 int min_freq; 367 struct cf_level levels[MAX_CF_LEVELS]; 368 eventhandler_tag cf_pre_tag; 369 370 clk_t clk_apb; 371 clk_t clk_ths; 372 }; 373 374 static struct resource_spec aw_thermal_spec[] = { 375 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 376 { SYS_RES_IRQ, 0, RF_ACTIVE }, 377 { -1, 0 } 378 }; 379 380 #define RD4(sc, reg) bus_read_4((sc)->res[0], (reg)) 381 #define WR4(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val)) 382 383 static int 384 aw_thermal_init(struct aw_thermal_softc *sc) 385 { 386 phandle_t node; 387 uint32_t calib[2]; 388 int error; 389 390 node = ofw_bus_get_node(sc->dev); 391 if (nvmem_get_cell_len(node, "ths-calib") > sizeof(calib)) { 392 device_printf(sc->dev, "ths-calib nvmem cell is too large\n"); 393 return (ENXIO); 394 } 395 error = nvmem_read_cell_by_name(node, "ths-calib", 396 (void *)&calib, nvmem_get_cell_len(node, "ths-calib")); 397 /* Read calibration settings from EFUSE */ 398 if (error != 0) { 399 device_printf(sc->dev, "Cannot read THS efuse\n"); 400 return (error); 401 } 402 403 calib[0] &= sc->conf->calib0_mask; 404 calib[1] &= sc->conf->calib1_mask; 405 406 /* Write calibration settings to thermal controller */ 407 if (calib[0] != 0) 408 WR4(sc, THS_CALIB0, calib[0]); 409 if (calib[1] != 0) 410 WR4(sc, THS_CALIB1, calib[1]); 411 412 /* Configure ADC acquire time (CLK_IN/(N+1)) and enable sensors */ 413 WR4(sc, THS_CTRL1, ADC_CALI_EN); 414 WR4(sc, THS_CTRL0, sc->conf->adc_acquire_time); 415 WR4(sc, THS_CTRL2, sc->conf->adc_acquire_time << SENSOR_ACQ1_SHIFT); 416 417 /* Set thermal period */ 418 WR4(sc, THS_INTC, sc->conf->thermal_per << THS_THERMAL_PER_SHIFT); 419 420 /* Enable average filter */ 421 WR4(sc, THS_FILTER, sc->conf->filter); 422 423 /* Enable interrupts */ 424 WR4(sc, THS_INTS, RD4(sc, THS_INTS)); 425 WR4(sc, THS_INTC, RD4(sc, THS_INTC) | SHUT_INT_ALL | ALARM_INT_ALL); 426 427 /* Enable sensors */ 428 WR4(sc, THS_CTRL2, RD4(sc, THS_CTRL2) | SENSOR_ENABLE_ALL); 429 430 return (0); 431 } 432 433 static int 434 aw_thermal_gettemp(struct aw_thermal_softc *sc, int sensor) 435 { 436 uint32_t val; 437 438 val = RD4(sc, THS_DATA0 + (sensor * 4)); 439 440 return (sc->conf->to_temp(val, sensor)); 441 } 442 443 static int 444 aw_thermal_getshut(struct aw_thermal_softc *sc, int sensor) 445 { 446 uint32_t val; 447 448 val = RD4(sc, THS_SHUTDOWN0_CTRL + (sensor * 4)); 449 val = (val >> SHUT_T_HOT_SHIFT) & SHUT_T_HOT_MASK; 450 451 return (sc->conf->to_temp(val, sensor)); 452 } 453 454 static void 455 aw_thermal_setshut(struct aw_thermal_softc *sc, int sensor, int temp) 456 { 457 uint32_t val; 458 459 val = RD4(sc, THS_SHUTDOWN0_CTRL + (sensor * 4)); 460 val &= ~(SHUT_T_HOT_MASK << SHUT_T_HOT_SHIFT); 461 val |= (sc->conf->to_reg(temp, sensor) << SHUT_T_HOT_SHIFT); 462 WR4(sc, THS_SHUTDOWN0_CTRL + (sensor * 4), val); 463 } 464 465 static int 466 aw_thermal_gethyst(struct aw_thermal_softc *sc, int sensor) 467 { 468 uint32_t val; 469 470 val = RD4(sc, THS_ALARM0_CTRL + (sensor * 4)); 471 val = (val >> ALARM_T_HYST_SHIFT) & ALARM_T_HYST_MASK; 472 473 return (sc->conf->to_temp(val, sensor)); 474 } 475 476 static int 477 aw_thermal_getalarm(struct aw_thermal_softc *sc, int sensor) 478 { 479 uint32_t val; 480 481 val = RD4(sc, THS_ALARM0_CTRL + (sensor * 4)); 482 val = (val >> ALARM_T_HOT_SHIFT) & ALARM_T_HOT_MASK; 483 484 return (sc->conf->to_temp(val, sensor)); 485 } 486 487 static void 488 aw_thermal_setalarm(struct aw_thermal_softc *sc, int sensor, int temp) 489 { 490 uint32_t val; 491 492 val = RD4(sc, THS_ALARM0_CTRL + (sensor * 4)); 493 val &= ~(ALARM_T_HOT_MASK << ALARM_T_HOT_SHIFT); 494 val |= (sc->conf->to_reg(temp, sensor) << ALARM_T_HOT_SHIFT); 495 WR4(sc, THS_ALARM0_CTRL + (sensor * 4), val); 496 } 497 498 static int 499 aw_thermal_sysctl(SYSCTL_HANDLER_ARGS) 500 { 501 struct aw_thermal_softc *sc; 502 int sensor, val; 503 504 sc = arg1; 505 sensor = arg2; 506 507 val = aw_thermal_gettemp(sc, sensor) + TEMP_C_TO_K; 508 509 return sysctl_handle_opaque(oidp, &val, sizeof(val), req); 510 } 511 512 static void 513 aw_thermal_throttle(struct aw_thermal_softc *sc, int enable) 514 { 515 device_t cf_dev; 516 int count, error; 517 518 if (enable == sc->throttle) 519 return; 520 521 if (enable != 0) { 522 /* Set the lowest available frequency */ 523 cf_dev = devclass_get_device(devclass_find("cpufreq"), 0); 524 if (cf_dev == NULL) 525 return; 526 count = MAX_CF_LEVELS; 527 error = CPUFREQ_LEVELS(cf_dev, sc->levels, &count); 528 if (error != 0 || count == 0) 529 return; 530 sc->min_freq = sc->levels[count - 1].total_set.freq; 531 error = CPUFREQ_SET(cf_dev, &sc->levels[count - 1], 532 CPUFREQ_PRIO_USER); 533 if (error != 0) 534 return; 535 } 536 537 sc->throttle = enable; 538 } 539 540 static void 541 aw_thermal_cf_task(void *arg, int pending) 542 { 543 struct aw_thermal_softc *sc; 544 545 sc = arg; 546 547 aw_thermal_throttle(sc, 1); 548 } 549 550 static void 551 aw_thermal_cf_pre_change(void *arg, const struct cf_level *level, int *status) 552 { 553 struct aw_thermal_softc *sc; 554 int temp_cur, temp_alarm; 555 556 sc = arg; 557 558 if (aw_thermal_throttle_enable == 0 || sc->throttle == 0 || 559 level->total_set.freq == sc->min_freq) 560 return; 561 562 temp_cur = aw_thermal_gettemp(sc, 0); 563 temp_alarm = aw_thermal_getalarm(sc, 0); 564 565 if (temp_cur < temp_alarm) 566 aw_thermal_throttle(sc, 0); 567 else 568 *status = ENXIO; 569 } 570 571 static void 572 aw_thermal_intr(void *arg) 573 { 574 struct aw_thermal_softc *sc; 575 device_t dev; 576 uint32_t ints; 577 578 dev = arg; 579 sc = device_get_softc(dev); 580 581 ints = RD4(sc, THS_INTS); 582 WR4(sc, THS_INTS, ints); 583 584 if ((ints & SHUT_INT_ALL) != 0) { 585 device_printf(dev, 586 "WARNING - current temperature exceeds safe limits\n"); 587 shutdown_nice(RB_POWEROFF); 588 } 589 590 if ((ints & ALARM_INT_ALL) != 0) 591 taskqueue_enqueue(taskqueue_thread, &sc->cf_task); 592 } 593 594 static int 595 aw_thermal_probe(device_t dev) 596 { 597 if (!ofw_bus_status_okay(dev)) 598 return (ENXIO); 599 600 if (THS_CONF(dev) == NULL) 601 return (ENXIO); 602 603 device_set_desc(dev, "Allwinner Thermal Sensor Controller"); 604 return (BUS_PROBE_DEFAULT); 605 } 606 607 static int 608 aw_thermal_attach(device_t dev) 609 { 610 struct aw_thermal_softc *sc; 611 hwreset_t rst; 612 int i, error; 613 void *ih; 614 615 sc = device_get_softc(dev); 616 sc->dev = dev; 617 rst = NULL; 618 ih = NULL; 619 620 sc->conf = THS_CONF(dev); 621 TASK_INIT(&sc->cf_task, 0, aw_thermal_cf_task, sc); 622 623 if (bus_alloc_resources(dev, aw_thermal_spec, sc->res) != 0) { 624 device_printf(dev, "cannot allocate resources for device\n"); 625 return (ENXIO); 626 } 627 628 if (clk_get_by_ofw_name(dev, 0, "apb", &sc->clk_apb) == 0) { 629 error = clk_enable(sc->clk_apb); 630 if (error != 0) { 631 device_printf(dev, "cannot enable apb clock\n"); 632 goto fail; 633 } 634 } 635 636 if (clk_get_by_ofw_name(dev, 0, "ths", &sc->clk_ths) == 0) { 637 error = clk_set_freq(sc->clk_ths, sc->conf->clk_rate, 0); 638 if (error != 0) { 639 device_printf(dev, "cannot set ths clock rate\n"); 640 goto fail; 641 } 642 error = clk_enable(sc->clk_ths); 643 if (error != 0) { 644 device_printf(dev, "cannot enable ths clock\n"); 645 goto fail; 646 } 647 } 648 649 if (hwreset_get_by_ofw_idx(dev, 0, 0, &rst) == 0) { 650 error = hwreset_deassert(rst); 651 if (error != 0) { 652 device_printf(dev, "cannot de-assert reset\n"); 653 goto fail; 654 } 655 } 656 657 error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_MISC | INTR_MPSAFE, 658 NULL, aw_thermal_intr, dev, &ih); 659 if (error != 0) { 660 device_printf(dev, "cannot setup interrupt handler\n"); 661 goto fail; 662 } 663 664 for (i = 0; i < sc->conf->nsensors; i++) { 665 if (sc->conf->sensors[i].init_alarm > 0) 666 aw_thermal_setalarm(sc, i, 667 sc->conf->sensors[i].init_alarm); 668 if (sc->conf->sensors[i].init_shut > 0) 669 aw_thermal_setshut(sc, i, 670 sc->conf->sensors[i].init_shut); 671 } 672 673 if (aw_thermal_init(sc) != 0) 674 goto fail; 675 676 for (i = 0; i < sc->conf->nsensors; i++) 677 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 678 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 679 OID_AUTO, sc->conf->sensors[i].name, 680 CTLTYPE_INT | CTLFLAG_RD, 681 sc, i, aw_thermal_sysctl, "IK0", 682 sc->conf->sensors[i].desc); 683 684 if (bootverbose) 685 for (i = 0; i < sc->conf->nsensors; i++) { 686 device_printf(dev, 687 "%s: alarm %dC hyst %dC shut %dC\n", 688 sc->conf->sensors[i].name, 689 aw_thermal_getalarm(sc, i), 690 aw_thermal_gethyst(sc, i), 691 aw_thermal_getshut(sc, i)); 692 } 693 694 sc->cf_pre_tag = EVENTHANDLER_REGISTER(cpufreq_pre_change, 695 aw_thermal_cf_pre_change, sc, EVENTHANDLER_PRI_FIRST); 696 697 return (0); 698 699 fail: 700 if (ih != NULL) 701 bus_teardown_intr(dev, sc->res[1], ih); 702 if (rst != NULL) 703 hwreset_release(rst); 704 if (sc->clk_apb != NULL) 705 clk_release(sc->clk_apb); 706 if (sc->clk_ths != NULL) 707 clk_release(sc->clk_ths); 708 bus_release_resources(dev, aw_thermal_spec, sc->res); 709 710 return (ENXIO); 711 } 712 713 static device_method_t aw_thermal_methods[] = { 714 /* Device interface */ 715 DEVMETHOD(device_probe, aw_thermal_probe), 716 DEVMETHOD(device_attach, aw_thermal_attach), 717 718 DEVMETHOD_END 719 }; 720 721 static driver_t aw_thermal_driver = { 722 "aw_thermal", 723 aw_thermal_methods, 724 sizeof(struct aw_thermal_softc), 725 }; 726 727 static devclass_t aw_thermal_devclass; 728 729 DRIVER_MODULE(aw_thermal, simplebus, aw_thermal_driver, aw_thermal_devclass, 730 0, 0); 731 MODULE_VERSION(aw_thermal, 1); 732 MODULE_DEPEND(aw_thermal, aw_sid, 1, 1, 1); 733 SIMPLEBUS_PNP_INFO(compat_data); 734