1 /*- 2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 /* 30 * Allwinner thermal sensor controller 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/bus.h> 39 #include <sys/rman.h> 40 #include <sys/kernel.h> 41 #include <sys/sysctl.h> 42 #include <sys/reboot.h> 43 #include <sys/module.h> 44 #include <sys/cpu.h> 45 #include <sys/taskqueue.h> 46 #include <machine/bus.h> 47 48 #include <dev/ofw/ofw_bus.h> 49 #include <dev/ofw/ofw_bus_subr.h> 50 51 #include <dev/extres/clk/clk.h> 52 #include <dev/extres/hwreset/hwreset.h> 53 54 #include <arm/allwinner/aw_sid.h> 55 56 #include "cpufreq_if.h" 57 58 #define THS_CTRL0 0x00 59 #define THS_CTRL1 0x04 60 #define ADC_CALI_EN (1 << 17) 61 #define THS_CTRL2 0x40 62 #define SENSOR_ACQ1_SHIFT 16 63 #define SENSOR2_EN (1 << 2) 64 #define SENSOR1_EN (1 << 1) 65 #define SENSOR0_EN (1 << 0) 66 #define THS_INTC 0x44 67 #define THS_INTS 0x48 68 #define THS2_DATA_IRQ_STS (1 << 10) 69 #define THS1_DATA_IRQ_STS (1 << 9) 70 #define THS0_DATA_IRQ_STS (1 << 8) 71 #define SHUT_INT2_STS (1 << 6) 72 #define SHUT_INT1_STS (1 << 5) 73 #define SHUT_INT0_STS (1 << 4) 74 #define ALARM_INT2_STS (1 << 2) 75 #define ALARM_INT1_STS (1 << 1) 76 #define ALARM_INT0_STS (1 << 0) 77 #define THS_ALARM0_CTRL 0x50 78 #define ALARM_T_HOT_MASK 0xfff 79 #define ALARM_T_HOT_SHIFT 16 80 #define ALARM_T_HYST_MASK 0xfff 81 #define ALARM_T_HYST_SHIFT 0 82 #define THS_SHUTDOWN0_CTRL 0x60 83 #define SHUT_T_HOT_MASK 0xfff 84 #define SHUT_T_HOT_SHIFT 16 85 #define THS_FILTER 0x70 86 #define THS_CALIB0 0x74 87 #define THS_CALIB1 0x78 88 #define THS_DATA0 0x80 89 #define THS_DATA1 0x84 90 #define THS_DATA2 0x88 91 #define DATA_MASK 0xfff 92 93 #define A83T_ADC_ACQUIRE_TIME 0x17 94 #define A83T_FILTER 0x4 95 #define A83T_INTC 0x1000 96 #define A83T_TEMP_BASE 2719000 97 #define A83T_TEMP_MUL 1000 98 #define A83T_TEMP_DIV 14186 99 #define A83T_CLK_RATE 24000000 100 101 #define A64_ADC_ACQUIRE_TIME 0x190 102 #define A64_FILTER 0x6 103 #define A64_INTC 0x18000 104 #define A64_TEMP_BASE 2170000 105 #define A64_TEMP_MUL 1000 106 #define A64_TEMP_DIV 8560 107 #define A64_CLK_RATE 4000000 108 109 #define H3_ADC_ACQUIRE_TIME 0x3f 110 #define H3_FILTER 0x6 111 #define H3_INTC 0x191000 112 #define H3_TEMP_BASE 217 113 #define H3_TEMP_MUL 1000 114 #define H3_TEMP_DIV 8253 115 #define H3_TEMP_MINUS 1794000 116 #define H3_CLK_RATE 4000000 117 #define H3_INIT_ALARM 90 /* degC */ 118 #define H3_INIT_SHUT 105 /* degC */ 119 120 #define TEMP_C_TO_K 273 121 #define SENSOR_ENABLE_ALL (SENSOR0_EN|SENSOR1_EN|SENSOR2_EN) 122 #define SHUT_INT_ALL (SHUT_INT0_STS|SHUT_INT1_STS|SHUT_INT2_STS) 123 #define ALARM_INT_ALL (ALARM_INT0_STS) 124 125 #define MAX_SENSORS 3 126 #define MAX_CF_LEVELS 64 127 128 #define THROTTLE_ENABLE_DEFAULT 1 129 130 /* Enable thermal throttling */ 131 static int aw_thermal_throttle_enable = THROTTLE_ENABLE_DEFAULT; 132 TUNABLE_INT("hw.aw_thermal.throttle_enable", &aw_thermal_throttle_enable); 133 134 struct aw_thermal_sensor { 135 const char *name; 136 const char *desc; 137 int init_alarm; 138 int init_shut; 139 }; 140 141 struct aw_thermal_config { 142 struct aw_thermal_sensor sensors[MAX_SENSORS]; 143 int nsensors; 144 uint64_t clk_rate; 145 uint32_t adc_acquire_time; 146 int adc_cali_en; 147 uint32_t filter; 148 uint32_t intc; 149 int (*to_temp)(uint32_t); 150 uint32_t (*to_reg)(int); 151 int temp_base; 152 int temp_mul; 153 int temp_div; 154 int calib0, calib1; 155 uint32_t calib0_mask, calib1_mask; 156 }; 157 158 static int 159 a83t_to_temp(uint32_t val) 160 { 161 return ((A83T_TEMP_BASE - (val * A83T_TEMP_MUL)) / A83T_TEMP_DIV); 162 } 163 164 static const struct aw_thermal_config a83t_config = { 165 .nsensors = 3, 166 .sensors = { 167 [0] = { 168 .name = "cluster0", 169 .desc = "CPU cluster 0 temperature", 170 }, 171 [1] = { 172 .name = "cluster1", 173 .desc = "CPU cluster 1 temperature", 174 }, 175 [2] = { 176 .name = "gpu", 177 .desc = "GPU temperature", 178 }, 179 }, 180 .clk_rate = A83T_CLK_RATE, 181 .adc_acquire_time = A83T_ADC_ACQUIRE_TIME, 182 .adc_cali_en = 1, 183 .filter = A83T_FILTER, 184 .intc = A83T_INTC, 185 .to_temp = a83t_to_temp, 186 .calib0_mask = 0xffffffff, 187 .calib1_mask = 0xffffffff, 188 }; 189 190 static int 191 a64_to_temp(uint32_t val) 192 { 193 return ((A64_TEMP_BASE - (val * A64_TEMP_MUL)) / A64_TEMP_DIV); 194 } 195 196 static const struct aw_thermal_config a64_config = { 197 .nsensors = 3, 198 .sensors = { 199 [0] = { 200 .name = "cpu", 201 .desc = "CPU temperature", 202 }, 203 [1] = { 204 .name = "gpu1", 205 .desc = "GPU temperature 1", 206 }, 207 [2] = { 208 .name = "gpu2", 209 .desc = "GPU temperature 2", 210 }, 211 }, 212 .clk_rate = A64_CLK_RATE, 213 .adc_acquire_time = A64_ADC_ACQUIRE_TIME, 214 .filter = A64_FILTER, 215 .intc = A64_INTC, 216 .to_temp = a64_to_temp, 217 }; 218 219 static int 220 h3_to_temp(uint32_t val) 221 { 222 return (H3_TEMP_BASE - ((val * H3_TEMP_MUL) / H3_TEMP_DIV)); 223 } 224 225 static uint32_t 226 h3_to_reg(int val) 227 { 228 return ((H3_TEMP_MINUS - (val * H3_TEMP_DIV)) / H3_TEMP_MUL); 229 } 230 231 static const struct aw_thermal_config h3_config = { 232 .nsensors = 1, 233 .sensors = { 234 [0] = { 235 .name = "cpu", 236 .desc = "CPU temperature", 237 .init_alarm = H3_INIT_ALARM, 238 .init_shut = H3_INIT_SHUT, 239 }, 240 }, 241 .clk_rate = H3_CLK_RATE, 242 .adc_acquire_time = H3_ADC_ACQUIRE_TIME, 243 .filter = H3_FILTER, 244 .intc = H3_INTC, 245 .to_temp = h3_to_temp, 246 .to_reg = h3_to_reg, 247 .calib0_mask = 0xfff, 248 }; 249 250 static struct ofw_compat_data compat_data[] = { 251 { "allwinner,sun8i-a83t-ts", (uintptr_t)&a83t_config }, 252 { "allwinner,sun8i-h3-ts", (uintptr_t)&h3_config }, 253 { "allwinner,sun50i-a64-ts", (uintptr_t)&a64_config }, 254 { NULL, (uintptr_t)NULL } 255 }; 256 257 #define THS_CONF(d) \ 258 (void *)ofw_bus_search_compatible((d), compat_data)->ocd_data 259 260 struct aw_thermal_softc { 261 device_t dev; 262 struct resource *res[2]; 263 struct aw_thermal_config *conf; 264 265 struct task cf_task; 266 int throttle; 267 int min_freq; 268 struct cf_level levels[MAX_CF_LEVELS]; 269 eventhandler_tag cf_pre_tag; 270 }; 271 272 static struct resource_spec aw_thermal_spec[] = { 273 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 274 { SYS_RES_IRQ, 0, RF_ACTIVE }, 275 { -1, 0 } 276 }; 277 278 #define RD4(sc, reg) bus_read_4((sc)->res[0], (reg)) 279 #define WR4(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val)) 280 281 static int 282 aw_thermal_init(struct aw_thermal_softc *sc) 283 { 284 uint32_t calib0, calib1; 285 int error; 286 287 if (sc->conf->calib0_mask != 0 || sc->conf->calib1_mask != 0) { 288 /* Read calibration settings from SRAM */ 289 error = aw_sid_read_tscalib(&calib0, &calib1); 290 if (error != 0) 291 return (error); 292 293 calib0 &= sc->conf->calib0_mask; 294 calib1 &= sc->conf->calib1_mask; 295 296 /* Write calibration settings to thermal controller */ 297 if (calib0 != 0) 298 WR4(sc, THS_CALIB0, calib0); 299 if (calib1 != 0) 300 WR4(sc, THS_CALIB1, calib1); 301 } 302 303 /* Configure ADC acquire time (CLK_IN/(N+1)) and enable sensors */ 304 WR4(sc, THS_CTRL1, ADC_CALI_EN); 305 WR4(sc, THS_CTRL0, sc->conf->adc_acquire_time); 306 WR4(sc, THS_CTRL2, sc->conf->adc_acquire_time << SENSOR_ACQ1_SHIFT); 307 308 /* Enable average filter */ 309 WR4(sc, THS_FILTER, sc->conf->filter); 310 311 /* Enable interrupts */ 312 WR4(sc, THS_INTS, RD4(sc, THS_INTS)); 313 WR4(sc, THS_INTC, sc->conf->intc | SHUT_INT_ALL | ALARM_INT_ALL); 314 315 /* Enable sensors */ 316 WR4(sc, THS_CTRL2, RD4(sc, THS_CTRL2) | SENSOR_ENABLE_ALL); 317 318 return (0); 319 } 320 321 static int 322 aw_thermal_gettemp(struct aw_thermal_softc *sc, int sensor) 323 { 324 uint32_t val; 325 326 val = RD4(sc, THS_DATA0 + (sensor * 4)); 327 328 return (sc->conf->to_temp(val)); 329 } 330 331 static int 332 aw_thermal_getshut(struct aw_thermal_softc *sc, int sensor) 333 { 334 uint32_t val; 335 336 val = RD4(sc, THS_SHUTDOWN0_CTRL + (sensor * 4)); 337 val = (val >> SHUT_T_HOT_SHIFT) & SHUT_T_HOT_MASK; 338 339 return (sc->conf->to_temp(val)); 340 } 341 342 static void 343 aw_thermal_setshut(struct aw_thermal_softc *sc, int sensor, int temp) 344 { 345 uint32_t val; 346 347 val = RD4(sc, THS_SHUTDOWN0_CTRL + (sensor * 4)); 348 val &= ~(SHUT_T_HOT_MASK << SHUT_T_HOT_SHIFT); 349 val |= (sc->conf->to_reg(temp) << SHUT_T_HOT_SHIFT); 350 WR4(sc, THS_SHUTDOWN0_CTRL + (sensor * 4), val); 351 } 352 353 static int 354 aw_thermal_gethyst(struct aw_thermal_softc *sc, int sensor) 355 { 356 uint32_t val; 357 358 val = RD4(sc, THS_ALARM0_CTRL + (sensor * 4)); 359 val = (val >> ALARM_T_HYST_SHIFT) & ALARM_T_HYST_MASK; 360 361 return (sc->conf->to_temp(val)); 362 } 363 364 static int 365 aw_thermal_getalarm(struct aw_thermal_softc *sc, int sensor) 366 { 367 uint32_t val; 368 369 val = RD4(sc, THS_ALARM0_CTRL + (sensor * 4)); 370 val = (val >> ALARM_T_HOT_SHIFT) & ALARM_T_HOT_MASK; 371 372 return (sc->conf->to_temp(val)); 373 } 374 375 static void 376 aw_thermal_setalarm(struct aw_thermal_softc *sc, int sensor, int temp) 377 { 378 uint32_t val; 379 380 val = RD4(sc, THS_ALARM0_CTRL + (sensor * 4)); 381 val &= ~(ALARM_T_HOT_MASK << ALARM_T_HOT_SHIFT); 382 val |= (sc->conf->to_reg(temp) << ALARM_T_HOT_SHIFT); 383 WR4(sc, THS_ALARM0_CTRL + (sensor * 4), val); 384 } 385 386 static int 387 aw_thermal_sysctl(SYSCTL_HANDLER_ARGS) 388 { 389 struct aw_thermal_softc *sc; 390 int sensor, val; 391 392 sc = arg1; 393 sensor = arg2; 394 395 val = aw_thermal_gettemp(sc, sensor) + TEMP_C_TO_K; 396 397 return sysctl_handle_opaque(oidp, &val, sizeof(val), req); 398 } 399 400 static void 401 aw_thermal_throttle(struct aw_thermal_softc *sc, int enable) 402 { 403 device_t cf_dev; 404 int count, error; 405 406 if (enable == sc->throttle) 407 return; 408 409 if (enable != 0) { 410 /* Set the lowest available frequency */ 411 cf_dev = devclass_get_device(devclass_find("cpufreq"), 0); 412 if (cf_dev == NULL) 413 return; 414 count = MAX_CF_LEVELS; 415 error = CPUFREQ_LEVELS(cf_dev, sc->levels, &count); 416 if (error != 0 || count == 0) 417 return; 418 sc->min_freq = sc->levels[count - 1].total_set.freq; 419 error = CPUFREQ_SET(cf_dev, &sc->levels[count - 1], 420 CPUFREQ_PRIO_USER); 421 if (error != 0) 422 return; 423 } 424 425 sc->throttle = enable; 426 } 427 428 static void 429 aw_thermal_cf_task(void *arg, int pending) 430 { 431 struct aw_thermal_softc *sc; 432 433 sc = arg; 434 435 aw_thermal_throttle(sc, 1); 436 } 437 438 static void 439 aw_thermal_cf_pre_change(void *arg, const struct cf_level *level, int *status) 440 { 441 struct aw_thermal_softc *sc; 442 int temp_cur, temp_alarm; 443 444 sc = arg; 445 446 if (aw_thermal_throttle_enable == 0 || sc->throttle == 0 || 447 level->total_set.freq == sc->min_freq) 448 return; 449 450 temp_cur = aw_thermal_gettemp(sc, 0); 451 temp_alarm = aw_thermal_getalarm(sc, 0); 452 453 if (temp_cur < temp_alarm) 454 aw_thermal_throttle(sc, 0); 455 else 456 *status = ENXIO; 457 } 458 459 static void 460 aw_thermal_intr(void *arg) 461 { 462 struct aw_thermal_softc *sc; 463 device_t dev; 464 uint32_t ints; 465 466 dev = arg; 467 sc = device_get_softc(dev); 468 469 ints = RD4(sc, THS_INTS); 470 WR4(sc, THS_INTS, ints); 471 472 if ((ints & SHUT_INT_ALL) != 0) { 473 device_printf(dev, 474 "WARNING - current temperature exceeds safe limits\n"); 475 shutdown_nice(RB_POWEROFF); 476 } 477 478 if ((ints & ALARM_INT_ALL) != 0) 479 taskqueue_enqueue(taskqueue_thread, &sc->cf_task); 480 } 481 482 static int 483 aw_thermal_probe(device_t dev) 484 { 485 if (!ofw_bus_status_okay(dev)) 486 return (ENXIO); 487 488 if (THS_CONF(dev) == NULL) 489 return (ENXIO); 490 491 device_set_desc(dev, "Allwinner Thermal Sensor Controller"); 492 return (BUS_PROBE_DEFAULT); 493 } 494 495 static int 496 aw_thermal_attach(device_t dev) 497 { 498 struct aw_thermal_softc *sc; 499 clk_t clk_ahb, clk_ths; 500 hwreset_t rst; 501 int i, error; 502 void *ih; 503 504 sc = device_get_softc(dev); 505 clk_ahb = clk_ths = NULL; 506 rst = NULL; 507 ih = NULL; 508 509 sc->conf = THS_CONF(dev); 510 TASK_INIT(&sc->cf_task, 0, aw_thermal_cf_task, sc); 511 512 if (bus_alloc_resources(dev, aw_thermal_spec, sc->res) != 0) { 513 device_printf(dev, "cannot allocate resources for device\n"); 514 return (ENXIO); 515 } 516 517 if (clk_get_by_ofw_name(dev, 0, "ahb", &clk_ahb) == 0) { 518 error = clk_enable(clk_ahb); 519 if (error != 0) { 520 device_printf(dev, "cannot enable ahb clock\n"); 521 goto fail; 522 } 523 } 524 if (clk_get_by_ofw_name(dev, 0, "ths", &clk_ths) == 0) { 525 error = clk_set_freq(clk_ths, sc->conf->clk_rate, 0); 526 if (error != 0) { 527 device_printf(dev, "cannot set ths clock rate\n"); 528 goto fail; 529 } 530 error = clk_enable(clk_ths); 531 if (error != 0) { 532 device_printf(dev, "cannot enable ths clock\n"); 533 goto fail; 534 } 535 } 536 if (hwreset_get_by_ofw_idx(dev, 0, 0, &rst) == 0) { 537 error = hwreset_deassert(rst); 538 if (error != 0) { 539 device_printf(dev, "cannot de-assert reset\n"); 540 goto fail; 541 } 542 } 543 544 error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_MISC | INTR_MPSAFE, 545 NULL, aw_thermal_intr, dev, &ih); 546 if (error != 0) { 547 device_printf(dev, "cannot setup interrupt handler\n"); 548 goto fail; 549 } 550 551 for (i = 0; i < sc->conf->nsensors; i++) { 552 if (sc->conf->sensors[i].init_alarm > 0) 553 aw_thermal_setalarm(sc, i, 554 sc->conf->sensors[i].init_alarm); 555 if (sc->conf->sensors[i].init_shut > 0) 556 aw_thermal_setshut(sc, i, 557 sc->conf->sensors[i].init_shut); 558 } 559 560 if (aw_thermal_init(sc) != 0) 561 goto fail; 562 563 for (i = 0; i < sc->conf->nsensors; i++) 564 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 565 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 566 OID_AUTO, sc->conf->sensors[i].name, 567 CTLTYPE_INT | CTLFLAG_RD, 568 sc, i, aw_thermal_sysctl, "IK0", 569 sc->conf->sensors[i].desc); 570 571 if (bootverbose) 572 for (i = 0; i < sc->conf->nsensors; i++) { 573 device_printf(dev, 574 "#%d: alarm %dC hyst %dC shut %dC\n", i, 575 aw_thermal_getalarm(sc, i), 576 aw_thermal_gethyst(sc, i), 577 aw_thermal_getshut(sc, i)); 578 } 579 580 sc->cf_pre_tag = EVENTHANDLER_REGISTER(cpufreq_pre_change, 581 aw_thermal_cf_pre_change, sc, EVENTHANDLER_PRI_FIRST); 582 583 return (0); 584 585 fail: 586 if (ih != NULL) 587 bus_teardown_intr(dev, sc->res[1], ih); 588 if (rst != NULL) 589 hwreset_release(rst); 590 if (clk_ahb != NULL) 591 clk_release(clk_ahb); 592 if (clk_ths != NULL) 593 clk_release(clk_ths); 594 bus_release_resources(dev, aw_thermal_spec, sc->res); 595 596 return (ENXIO); 597 } 598 599 static device_method_t aw_thermal_methods[] = { 600 /* Device interface */ 601 DEVMETHOD(device_probe, aw_thermal_probe), 602 DEVMETHOD(device_attach, aw_thermal_attach), 603 604 DEVMETHOD_END 605 }; 606 607 static driver_t aw_thermal_driver = { 608 "aw_thermal", 609 aw_thermal_methods, 610 sizeof(struct aw_thermal_softc), 611 }; 612 613 static devclass_t aw_thermal_devclass; 614 615 DRIVER_MODULE(aw_thermal, simplebus, aw_thermal_driver, aw_thermal_devclass, 616 0, 0); 617 MODULE_VERSION(aw_thermal, 1); 618