1 /*- 2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 /* 30 * Allwinner RSB (Reduced Serial Bus) and P2WI (Push-Pull Two Wire Interface) 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/bus.h> 39 #include <sys/rman.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/module.h> 43 #include <sys/mutex.h> 44 #include <machine/bus.h> 45 46 #include <dev/ofw/ofw_bus.h> 47 #include <dev/ofw/ofw_bus_subr.h> 48 49 #include <dev/iicbus/iiconf.h> 50 #include <dev/iicbus/iicbus.h> 51 52 #include <dev/extres/clk/clk.h> 53 #include <dev/extres/hwreset/hwreset.h> 54 55 #include "iicbus_if.h" 56 57 #define RSB_CTRL 0x00 58 #define START_TRANS (1 << 7) 59 #define GLOBAL_INT_ENB (1 << 1) 60 #define SOFT_RESET (1 << 0) 61 #define RSB_CCR 0x04 62 #define RSB_INTE 0x08 63 #define RSB_INTS 0x0c 64 #define INT_TRANS_ERR_ID(x) (((x) >> 8) & 0xf) 65 #define INT_LOAD_BSY (1 << 2) 66 #define INT_TRANS_ERR (1 << 1) 67 #define INT_TRANS_OVER (1 << 0) 68 #define INT_MASK (INT_LOAD_BSY|INT_TRANS_ERR|INT_TRANS_OVER) 69 #define RSB_DADDR0 0x10 70 #define RSB_DADDR1 0x14 71 #define RSB_DLEN 0x18 72 #define DLEN_READ (1 << 4) 73 #define RSB_DATA0 0x1c 74 #define RSB_DATA1 0x20 75 #define RSB_CMD 0x2c 76 #define CMD_SRTA 0xe8 77 #define CMD_RD8 0x8b 78 #define CMD_RD16 0x9c 79 #define CMD_RD32 0xa6 80 #define CMD_WR8 0x4e 81 #define CMD_WR16 0x59 82 #define CMD_WR32 0x63 83 #define RSB_DAR 0x30 84 #define DAR_RTA (0xff << 16) 85 #define DAR_RTA_SHIFT 16 86 #define DAR_DA (0xffff << 0) 87 #define DAR_DA_SHIFT 0 88 89 #define RSB_MAXLEN 8 90 #define RSB_RESET_RETRY 100 91 #define RSB_I2C_TIMEOUT hz 92 93 #define RSB_ADDR_PMIC_PRIMARY 0x3a3 94 #define RSB_ADDR_PMIC_SECONDARY 0x745 95 #define RSB_ADDR_PERIPH_IC 0xe89 96 97 #define A31_P2WI 1 98 #define A23_RSB 2 99 100 static struct ofw_compat_data compat_data[] = { 101 { "allwinner,sun6i-a31-p2wi", A31_P2WI }, 102 { "allwinner,sun8i-a23-rsb", A23_RSB }, 103 { NULL, 0 } 104 }; 105 106 static struct resource_spec rsb_spec[] = { 107 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 108 { -1, 0 } 109 }; 110 111 /* 112 * Device address to Run-time address mappings. 113 * 114 * Run-time address (RTA) is an 8-bit value used to address the device during 115 * a read or write transaction. The following are valid RTAs: 116 * 0x17 0x2d 0x3a 0x4e 0x59 0x63 0x74 0x8b 0x9c 0xa6 0xb1 0xc5 0xd2 0xe8 0xff 117 * 118 * Allwinner uses RTA 0x2d for the primary PMIC, 0x3a for the secondary PMIC, 119 * and 0x4e for the peripheral IC (where applicable). 120 */ 121 static const struct { 122 uint16_t addr; 123 uint8_t rta; 124 } rsb_rtamap[] = { 125 { .addr = RSB_ADDR_PMIC_PRIMARY, .rta = 0x2d }, 126 { .addr = RSB_ADDR_PMIC_SECONDARY, .rta = 0x3a }, 127 { .addr = RSB_ADDR_PERIPH_IC, .rta = 0x4e }, 128 { .addr = 0, .rta = 0 } 129 }; 130 131 struct rsb_softc { 132 struct resource *res; 133 struct mtx mtx; 134 clk_t clk; 135 hwreset_t rst; 136 device_t iicbus; 137 int busy; 138 uint32_t status; 139 uint16_t cur_addr; 140 int type; 141 142 struct iic_msg *msg; 143 }; 144 145 #define RSB_LOCK(sc) mtx_lock(&(sc)->mtx) 146 #define RSB_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 147 #define RSB_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED) 148 #define RSB_READ(sc, reg) bus_read_4((sc)->res, (reg)) 149 #define RSB_WRITE(sc, reg, val) bus_write_4((sc)->res, (reg), (val)) 150 151 static phandle_t 152 rsb_get_node(device_t bus, device_t dev) 153 { 154 return (ofw_bus_get_node(bus)); 155 } 156 157 static int 158 rsb_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) 159 { 160 struct rsb_softc *sc; 161 int retry; 162 163 sc = device_get_softc(dev); 164 165 RSB_LOCK(sc); 166 167 /* Write soft-reset bit and wait for it to self-clear. */ 168 RSB_WRITE(sc, RSB_CTRL, SOFT_RESET); 169 for (retry = RSB_RESET_RETRY; retry > 0; retry--) 170 if ((RSB_READ(sc, RSB_CTRL) & SOFT_RESET) == 0) 171 break; 172 173 RSB_UNLOCK(sc); 174 175 if (retry == 0) { 176 device_printf(dev, "soft reset timeout\n"); 177 return (ETIMEDOUT); 178 } 179 180 return (IIC_ENOADDR); 181 } 182 183 static uint32_t 184 rsb_encode(const uint8_t *buf, u_int len, u_int off) 185 { 186 uint32_t val; 187 u_int n; 188 189 val = 0; 190 for (n = off; n < MIN(len, 4 + off); n++) 191 val |= ((uint32_t)buf[n] << ((n - off) * NBBY)); 192 193 return val; 194 } 195 196 static void 197 rsb_decode(const uint32_t val, uint8_t *buf, u_int len, u_int off) 198 { 199 u_int n; 200 201 for (n = off; n < MIN(len, 4 + off); n++) 202 buf[n] = (val >> ((n - off) * NBBY)) & 0xff; 203 } 204 205 static int 206 rsb_start(device_t dev) 207 { 208 struct rsb_softc *sc; 209 int error, retry; 210 211 sc = device_get_softc(dev); 212 213 RSB_ASSERT_LOCKED(sc); 214 215 /* Start the transfer */ 216 RSB_WRITE(sc, RSB_CTRL, GLOBAL_INT_ENB | START_TRANS); 217 218 /* Wait for transfer to complete */ 219 error = ETIMEDOUT; 220 for (retry = RSB_I2C_TIMEOUT; retry > 0; retry--) { 221 sc->status |= RSB_READ(sc, RSB_INTS); 222 if ((sc->status & INT_TRANS_OVER) != 0) { 223 error = 0; 224 break; 225 } 226 DELAY((1000 * hz) / RSB_I2C_TIMEOUT); 227 } 228 if (error == 0 && (sc->status & INT_TRANS_OVER) == 0) { 229 device_printf(dev, "transfer error, status 0x%08x\n", 230 sc->status); 231 error = EIO; 232 } 233 234 return (error); 235 236 } 237 238 static int 239 rsb_set_rta(device_t dev, uint16_t addr) 240 { 241 struct rsb_softc *sc; 242 uint8_t rta; 243 int i; 244 245 sc = device_get_softc(dev); 246 247 RSB_ASSERT_LOCKED(sc); 248 249 /* Lookup run-time address for given device address */ 250 for (rta = 0, i = 0; rsb_rtamap[i].rta != 0; i++) 251 if (rsb_rtamap[i].addr == addr) { 252 rta = rsb_rtamap[i].rta; 253 break; 254 } 255 if (rta == 0) { 256 device_printf(dev, "RTA not known for address %#x\n", addr); 257 return (ENXIO); 258 } 259 260 /* Set run-time address */ 261 RSB_WRITE(sc, RSB_INTS, RSB_READ(sc, RSB_INTS)); 262 RSB_WRITE(sc, RSB_DAR, (addr << DAR_DA_SHIFT) | (rta << DAR_RTA_SHIFT)); 263 RSB_WRITE(sc, RSB_CMD, CMD_SRTA); 264 265 return (rsb_start(dev)); 266 } 267 268 static int 269 rsb_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) 270 { 271 struct rsb_softc *sc; 272 uint32_t daddr[2], data[2], dlen; 273 uint16_t device_addr; 274 uint8_t cmd; 275 int error; 276 277 sc = device_get_softc(dev); 278 279 /* 280 * P2WI and RSB are not really I2C or SMBus controllers, so there are 281 * some restrictions imposed by the driver. 282 * 283 * Transfers must contain exactly two messages. The first is always 284 * a write, containing a single data byte offset. Data will either 285 * be read from or written to the corresponding data byte in the 286 * second message. The slave address in both messages must be the 287 * same. 288 */ 289 if (nmsgs != 2 || (msgs[0].flags & IIC_M_RD) == IIC_M_RD || 290 (msgs[0].slave >> 1) != (msgs[1].slave >> 1) || 291 msgs[0].len != 1 || msgs[1].len > RSB_MAXLEN) 292 return (EINVAL); 293 294 /* The RSB controller can read or write 1, 2, or 4 bytes at a time. */ 295 if (sc->type == A23_RSB) { 296 if ((msgs[1].flags & IIC_M_RD) != 0) { 297 switch (msgs[1].len) { 298 case 1: 299 cmd = CMD_RD8; 300 break; 301 case 2: 302 cmd = CMD_RD16; 303 break; 304 case 4: 305 cmd = CMD_RD32; 306 break; 307 default: 308 return (EINVAL); 309 } 310 } else { 311 switch (msgs[1].len) { 312 case 1: 313 cmd = CMD_WR8; 314 break; 315 case 2: 316 cmd = CMD_WR16; 317 break; 318 case 4: 319 cmd = CMD_WR32; 320 break; 321 default: 322 return (EINVAL); 323 } 324 } 325 } 326 327 RSB_LOCK(sc); 328 while (sc->busy) 329 mtx_sleep(sc, &sc->mtx, 0, "i2cbuswait", 0); 330 sc->busy = 1; 331 sc->status = 0; 332 333 /* Select current run-time address if necessary */ 334 if (sc->type == A23_RSB) { 335 device_addr = msgs[0].slave >> 1; 336 if (sc->cur_addr != device_addr) { 337 error = rsb_set_rta(dev, device_addr); 338 if (error != 0) 339 goto done; 340 sc->cur_addr = device_addr; 341 sc->status = 0; 342 } 343 } 344 345 /* Clear interrupt status */ 346 RSB_WRITE(sc, RSB_INTS, RSB_READ(sc, RSB_INTS)); 347 348 /* Program data access address registers */ 349 daddr[0] = rsb_encode(msgs[0].buf, msgs[0].len, 0); 350 RSB_WRITE(sc, RSB_DADDR0, daddr[0]); 351 352 /* Write data */ 353 if ((msgs[1].flags & IIC_M_RD) == 0) { 354 data[0] = rsb_encode(msgs[1].buf, msgs[1].len, 0); 355 RSB_WRITE(sc, RSB_DATA0, data[0]); 356 } 357 358 /* Set command type for RSB */ 359 if (sc->type == A23_RSB) 360 RSB_WRITE(sc, RSB_CMD, cmd); 361 362 /* Program data length register and transfer direction */ 363 dlen = msgs[0].len - 1; 364 if ((msgs[1].flags & IIC_M_RD) == IIC_M_RD) 365 dlen |= DLEN_READ; 366 RSB_WRITE(sc, RSB_DLEN, dlen); 367 368 /* Start transfer */ 369 error = rsb_start(dev); 370 if (error != 0) 371 goto done; 372 373 /* Read data */ 374 if ((msgs[1].flags & IIC_M_RD) == IIC_M_RD) { 375 data[0] = RSB_READ(sc, RSB_DATA0); 376 rsb_decode(data[0], msgs[1].buf, msgs[1].len, 0); 377 } 378 379 done: 380 sc->msg = NULL; 381 sc->busy = 0; 382 wakeup(sc); 383 RSB_UNLOCK(sc); 384 385 return (error); 386 } 387 388 static int 389 rsb_probe(device_t dev) 390 { 391 if (!ofw_bus_status_okay(dev)) 392 return (ENXIO); 393 394 switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) { 395 case A23_RSB: 396 device_set_desc(dev, "Allwinner RSB"); 397 break; 398 case A31_P2WI: 399 device_set_desc(dev, "Allwinner P2WI"); 400 break; 401 default: 402 return (ENXIO); 403 } 404 405 return (BUS_PROBE_DEFAULT); 406 } 407 408 static int 409 rsb_attach(device_t dev) 410 { 411 struct rsb_softc *sc; 412 int error; 413 414 sc = device_get_softc(dev); 415 mtx_init(&sc->mtx, device_get_nameunit(dev), "rsb", MTX_DEF); 416 417 sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 418 419 if (clk_get_by_ofw_index(dev, 0, 0, &sc->clk) == 0) { 420 error = clk_enable(sc->clk); 421 if (error != 0) { 422 device_printf(dev, "cannot enable clock\n"); 423 goto fail; 424 } 425 } 426 if (hwreset_get_by_ofw_idx(dev, 0, 0, &sc->rst) == 0) { 427 error = hwreset_deassert(sc->rst); 428 if (error != 0) { 429 device_printf(dev, "cannot de-assert reset\n"); 430 goto fail; 431 } 432 } 433 434 if (bus_alloc_resources(dev, rsb_spec, &sc->res) != 0) { 435 device_printf(dev, "cannot allocate resources for device\n"); 436 error = ENXIO; 437 goto fail; 438 } 439 440 sc->iicbus = device_add_child(dev, "iicbus", -1); 441 if (sc->iicbus == NULL) { 442 device_printf(dev, "cannot add iicbus child device\n"); 443 error = ENXIO; 444 goto fail; 445 } 446 447 bus_generic_attach(dev); 448 449 return (0); 450 451 fail: 452 bus_release_resources(dev, rsb_spec, &sc->res); 453 if (sc->rst != NULL) 454 hwreset_release(sc->rst); 455 if (sc->clk != NULL) 456 clk_release(sc->clk); 457 mtx_destroy(&sc->mtx); 458 return (error); 459 } 460 461 static device_method_t rsb_methods[] = { 462 /* Device interface */ 463 DEVMETHOD(device_probe, rsb_probe), 464 DEVMETHOD(device_attach, rsb_attach), 465 466 /* Bus interface */ 467 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 468 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 469 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), 470 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 471 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 472 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 473 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 474 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 475 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 476 477 /* OFW methods */ 478 DEVMETHOD(ofw_bus_get_node, rsb_get_node), 479 480 /* iicbus interface */ 481 DEVMETHOD(iicbus_callback, iicbus_null_callback), 482 DEVMETHOD(iicbus_reset, rsb_reset), 483 DEVMETHOD(iicbus_transfer, rsb_transfer), 484 485 DEVMETHOD_END 486 }; 487 488 static driver_t rsb_driver = { 489 "iichb", 490 rsb_methods, 491 sizeof(struct rsb_softc), 492 }; 493 494 static devclass_t rsb_devclass; 495 496 EARLY_DRIVER_MODULE(iicbus, rsb, iicbus_driver, iicbus_devclass, 0, 0, 497 BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE); 498 EARLY_DRIVER_MODULE(rsb, simplebus, rsb_driver, rsb_devclass, 0, 0, 499 BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE); 500 MODULE_VERSION(rsb, 1); 501 MODULE_DEPEND(rsb, iicbus, 1, 1, 1); 502 SIMPLEBUS_PNP_INFO(compat_data); 503