1 /*- 2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca> 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 18 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 19 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 20 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 21 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 /* 27 * Allwinner RSB (Reduced Serial Bus) and P2WI (Push-Pull Two Wire Interface) 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/rman.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/module.h> 40 #include <sys/mutex.h> 41 #include <machine/bus.h> 42 43 #include <dev/ofw/ofw_bus.h> 44 #include <dev/ofw/ofw_bus_subr.h> 45 46 #include <dev/iicbus/iiconf.h> 47 #include <dev/iicbus/iicbus.h> 48 49 #include <dev/extres/clk/clk.h> 50 #include <dev/extres/hwreset/hwreset.h> 51 52 #include "iicbus_if.h" 53 54 #define RSB_CTRL 0x00 55 #define START_TRANS (1 << 7) 56 #define GLOBAL_INT_ENB (1 << 1) 57 #define SOFT_RESET (1 << 0) 58 #define RSB_CCR 0x04 59 #define RSB_INTE 0x08 60 #define RSB_INTS 0x0c 61 #define INT_TRANS_ERR_ID(x) (((x) >> 8) & 0xf) 62 #define INT_LOAD_BSY (1 << 2) 63 #define INT_TRANS_ERR (1 << 1) 64 #define INT_TRANS_OVER (1 << 0) 65 #define INT_MASK (INT_LOAD_BSY|INT_TRANS_ERR|INT_TRANS_OVER) 66 #define RSB_DADDR0 0x10 67 #define RSB_DADDR1 0x14 68 #define RSB_DLEN 0x18 69 #define DLEN_READ (1 << 4) 70 #define RSB_DATA0 0x1c 71 #define RSB_DATA1 0x20 72 #define RSB_PMCR 0x28 73 #define RSB_PMCR_START (1 << 31) 74 #define RSB_PMCR_DATA(x) (x << 16) 75 #define RSB_PMCR_REG(x) (x << 8) 76 #define RSB_CMD 0x2c 77 #define CMD_SRTA 0xe8 78 #define CMD_RD8 0x8b 79 #define CMD_RD16 0x9c 80 #define CMD_RD32 0xa6 81 #define CMD_WR8 0x4e 82 #define CMD_WR16 0x59 83 #define CMD_WR32 0x63 84 #define RSB_DAR 0x30 85 #define DAR_RTA (0xff << 16) 86 #define DAR_RTA_SHIFT 16 87 #define DAR_DA (0xffff << 0) 88 #define DAR_DA_SHIFT 0 89 90 #define RSB_MAXLEN 8 91 #define RSB_RESET_RETRY 100 92 #define RSB_I2C_TIMEOUT hz 93 94 #define RSB_ADDR_PMIC_PRIMARY 0x3a3 95 #define RSB_ADDR_PMIC_SECONDARY 0x745 96 #define RSB_ADDR_PERIPH_IC 0xe89 97 98 #define PMIC_MODE_REG 0x3e 99 #define PMIC_MODE_I2C 0x00 100 #define PMIC_MODE_RSB 0x7c 101 102 #define A31_P2WI 1 103 #define A23_RSB 2 104 105 static struct ofw_compat_data compat_data[] = { 106 { "allwinner,sun6i-a31-p2wi", A31_P2WI }, 107 { "allwinner,sun8i-a23-rsb", A23_RSB }, 108 { NULL, 0 } 109 }; 110 111 static struct resource_spec rsb_spec[] = { 112 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 113 { -1, 0 } 114 }; 115 116 /* 117 * Device address to Run-time address mappings. 118 * 119 * Run-time address (RTA) is an 8-bit value used to address the device during 120 * a read or write transaction. The following are valid RTAs: 121 * 0x17 0x2d 0x3a 0x4e 0x59 0x63 0x74 0x8b 0x9c 0xa6 0xb1 0xc5 0xd2 0xe8 0xff 122 * 123 * Allwinner uses RTA 0x2d for the primary PMIC, 0x3a for the secondary PMIC, 124 * and 0x4e for the peripheral IC (where applicable). 125 */ 126 static const struct { 127 uint16_t addr; 128 uint8_t rta; 129 } rsb_rtamap[] = { 130 { .addr = RSB_ADDR_PMIC_PRIMARY, .rta = 0x2d }, 131 { .addr = RSB_ADDR_PMIC_SECONDARY, .rta = 0x3a }, 132 { .addr = RSB_ADDR_PERIPH_IC, .rta = 0x4e }, 133 { .addr = 0, .rta = 0 } 134 }; 135 136 struct rsb_softc { 137 struct resource *res; 138 struct mtx mtx; 139 clk_t clk; 140 hwreset_t rst; 141 device_t iicbus; 142 int busy; 143 uint32_t status; 144 uint16_t cur_addr; 145 int type; 146 147 struct iic_msg *msg; 148 }; 149 150 #define RSB_LOCK(sc) mtx_lock(&(sc)->mtx) 151 #define RSB_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 152 #define RSB_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED) 153 #define RSB_READ(sc, reg) bus_read_4((sc)->res, (reg)) 154 #define RSB_WRITE(sc, reg, val) bus_write_4((sc)->res, (reg), (val)) 155 156 static phandle_t 157 rsb_get_node(device_t bus, device_t dev) 158 { 159 return (ofw_bus_get_node(bus)); 160 } 161 162 static int 163 rsb_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) 164 { 165 struct rsb_softc *sc; 166 int retry; 167 168 sc = device_get_softc(dev); 169 170 RSB_LOCK(sc); 171 172 /* Write soft-reset bit and wait for it to self-clear. */ 173 RSB_WRITE(sc, RSB_CTRL, SOFT_RESET); 174 for (retry = RSB_RESET_RETRY; retry > 0; retry--) 175 if ((RSB_READ(sc, RSB_CTRL) & SOFT_RESET) == 0) 176 break; 177 178 RSB_UNLOCK(sc); 179 180 if (retry == 0) { 181 device_printf(dev, "soft reset timeout\n"); 182 return (ETIMEDOUT); 183 } 184 185 return (IIC_ENOADDR); 186 } 187 188 static uint32_t 189 rsb_encode(const uint8_t *buf, u_int len, u_int off) 190 { 191 uint32_t val; 192 u_int n; 193 194 val = 0; 195 for (n = off; n < MIN(len, 4 + off); n++) 196 val |= ((uint32_t)buf[n] << ((n - off) * NBBY)); 197 198 return val; 199 } 200 201 static void 202 rsb_decode(const uint32_t val, uint8_t *buf, u_int len, u_int off) 203 { 204 u_int n; 205 206 for (n = off; n < MIN(len, 4 + off); n++) 207 buf[n] = (val >> ((n - off) * NBBY)) & 0xff; 208 } 209 210 static int 211 rsb_start(device_t dev) 212 { 213 struct rsb_softc *sc; 214 int error, retry; 215 216 sc = device_get_softc(dev); 217 218 RSB_ASSERT_LOCKED(sc); 219 220 /* Start the transfer */ 221 RSB_WRITE(sc, RSB_CTRL, GLOBAL_INT_ENB | START_TRANS); 222 223 /* Wait for transfer to complete */ 224 error = ETIMEDOUT; 225 for (retry = RSB_I2C_TIMEOUT; retry > 0; retry--) { 226 sc->status |= RSB_READ(sc, RSB_INTS); 227 if ((sc->status & INT_TRANS_OVER) != 0) { 228 error = 0; 229 break; 230 } 231 DELAY((1000 * hz) / RSB_I2C_TIMEOUT); 232 } 233 if (error == 0 && (sc->status & INT_TRANS_OVER) == 0) { 234 device_printf(dev, "transfer error, status 0x%08x\n", 235 sc->status); 236 error = EIO; 237 } 238 239 return (error); 240 241 } 242 243 static int 244 rsb_set_rta(device_t dev, uint16_t addr) 245 { 246 struct rsb_softc *sc; 247 uint8_t rta; 248 int i; 249 250 sc = device_get_softc(dev); 251 252 RSB_ASSERT_LOCKED(sc); 253 254 /* Lookup run-time address for given device address */ 255 for (rta = 0, i = 0; rsb_rtamap[i].rta != 0; i++) 256 if (rsb_rtamap[i].addr == addr) { 257 rta = rsb_rtamap[i].rta; 258 break; 259 } 260 if (rta == 0) { 261 device_printf(dev, "RTA not known for address %#x\n", addr); 262 return (ENXIO); 263 } 264 265 /* Set run-time address */ 266 RSB_WRITE(sc, RSB_INTS, RSB_READ(sc, RSB_INTS)); 267 RSB_WRITE(sc, RSB_DAR, (addr << DAR_DA_SHIFT) | (rta << DAR_RTA_SHIFT)); 268 RSB_WRITE(sc, RSB_CMD, CMD_SRTA); 269 270 return (rsb_start(dev)); 271 } 272 273 static int 274 rsb_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) 275 { 276 struct rsb_softc *sc; 277 uint32_t daddr[2], data[2], dlen; 278 uint16_t device_addr; 279 uint8_t cmd; 280 int error; 281 282 sc = device_get_softc(dev); 283 284 /* 285 * P2WI and RSB are not really I2C or SMBus controllers, so there are 286 * some restrictions imposed by the driver. 287 * 288 * Transfers must contain exactly two messages. The first is always 289 * a write, containing a single data byte offset. Data will either 290 * be read from or written to the corresponding data byte in the 291 * second message. The slave address in both messages must be the 292 * same. 293 */ 294 if (nmsgs != 2 || (msgs[0].flags & IIC_M_RD) == IIC_M_RD || 295 (msgs[0].slave >> 1) != (msgs[1].slave >> 1) || 296 msgs[0].len != 1 || msgs[1].len > RSB_MAXLEN) 297 return (EINVAL); 298 299 /* The RSB controller can read or write 1, 2, or 4 bytes at a time. */ 300 if (sc->type == A23_RSB) { 301 if ((msgs[1].flags & IIC_M_RD) != 0) { 302 switch (msgs[1].len) { 303 case 1: 304 cmd = CMD_RD8; 305 break; 306 case 2: 307 cmd = CMD_RD16; 308 break; 309 case 4: 310 cmd = CMD_RD32; 311 break; 312 default: 313 return (EINVAL); 314 } 315 } else { 316 switch (msgs[1].len) { 317 case 1: 318 cmd = CMD_WR8; 319 break; 320 case 2: 321 cmd = CMD_WR16; 322 break; 323 case 4: 324 cmd = CMD_WR32; 325 break; 326 default: 327 return (EINVAL); 328 } 329 } 330 } 331 332 RSB_LOCK(sc); 333 while (sc->busy) 334 mtx_sleep(sc, &sc->mtx, 0, "i2cbuswait", 0); 335 sc->busy = 1; 336 sc->status = 0; 337 338 /* Select current run-time address if necessary */ 339 if (sc->type == A23_RSB) { 340 device_addr = msgs[0].slave >> 1; 341 if (sc->cur_addr != device_addr) { 342 error = rsb_set_rta(dev, device_addr); 343 if (error != 0) 344 goto done; 345 sc->cur_addr = device_addr; 346 sc->status = 0; 347 } 348 } 349 350 /* Clear interrupt status */ 351 RSB_WRITE(sc, RSB_INTS, RSB_READ(sc, RSB_INTS)); 352 353 /* Program data access address registers */ 354 daddr[0] = rsb_encode(msgs[0].buf, msgs[0].len, 0); 355 RSB_WRITE(sc, RSB_DADDR0, daddr[0]); 356 357 /* Write data */ 358 if ((msgs[1].flags & IIC_M_RD) == 0) { 359 data[0] = rsb_encode(msgs[1].buf, msgs[1].len, 0); 360 RSB_WRITE(sc, RSB_DATA0, data[0]); 361 } 362 363 /* Set command type for RSB */ 364 if (sc->type == A23_RSB) 365 RSB_WRITE(sc, RSB_CMD, cmd); 366 367 /* Program data length register and transfer direction */ 368 dlen = msgs[0].len - 1; 369 if ((msgs[1].flags & IIC_M_RD) == IIC_M_RD) 370 dlen |= DLEN_READ; 371 RSB_WRITE(sc, RSB_DLEN, dlen); 372 373 /* Start transfer */ 374 error = rsb_start(dev); 375 if (error != 0) 376 goto done; 377 378 /* Read data */ 379 if ((msgs[1].flags & IIC_M_RD) == IIC_M_RD) { 380 data[0] = RSB_READ(sc, RSB_DATA0); 381 rsb_decode(data[0], msgs[1].buf, msgs[1].len, 0); 382 } 383 384 done: 385 sc->msg = NULL; 386 sc->busy = 0; 387 wakeup(sc); 388 RSB_UNLOCK(sc); 389 390 return (error); 391 } 392 393 static int 394 rsb_probe(device_t dev) 395 { 396 if (!ofw_bus_status_okay(dev)) 397 return (ENXIO); 398 399 switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) { 400 case A23_RSB: 401 device_set_desc(dev, "Allwinner RSB"); 402 break; 403 case A31_P2WI: 404 device_set_desc(dev, "Allwinner P2WI"); 405 break; 406 default: 407 return (ENXIO); 408 } 409 410 return (BUS_PROBE_DEFAULT); 411 } 412 413 static int 414 rsb_attach(device_t dev) 415 { 416 struct rsb_softc *sc; 417 int error; 418 419 sc = device_get_softc(dev); 420 mtx_init(&sc->mtx, device_get_nameunit(dev), "rsb", MTX_DEF); 421 422 sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 423 424 if (clk_get_by_ofw_index(dev, 0, 0, &sc->clk) == 0) { 425 error = clk_enable(sc->clk); 426 if (error != 0) { 427 device_printf(dev, "cannot enable clock\n"); 428 goto fail; 429 } 430 } 431 if (hwreset_get_by_ofw_idx(dev, 0, 0, &sc->rst) == 0) { 432 error = hwreset_deassert(sc->rst); 433 if (error != 0) { 434 device_printf(dev, "cannot de-assert reset\n"); 435 goto fail; 436 } 437 } 438 439 if (bus_alloc_resources(dev, rsb_spec, &sc->res) != 0) { 440 device_printf(dev, "cannot allocate resources for device\n"); 441 error = ENXIO; 442 goto fail; 443 } 444 445 /* Set the PMIC into RSB mode as ATF might have leave it in I2C mode */ 446 RSB_WRITE(sc, RSB_PMCR, RSB_PMCR_REG(PMIC_MODE_REG) | RSB_PMCR_DATA(PMIC_MODE_RSB) | RSB_PMCR_START); 447 448 sc->iicbus = device_add_child(dev, "iicbus", -1); 449 if (sc->iicbus == NULL) { 450 device_printf(dev, "cannot add iicbus child device\n"); 451 error = ENXIO; 452 goto fail; 453 } 454 455 bus_generic_attach(dev); 456 457 return (0); 458 459 fail: 460 bus_release_resources(dev, rsb_spec, &sc->res); 461 if (sc->rst != NULL) 462 hwreset_release(sc->rst); 463 if (sc->clk != NULL) 464 clk_release(sc->clk); 465 mtx_destroy(&sc->mtx); 466 return (error); 467 } 468 469 static device_method_t rsb_methods[] = { 470 /* Device interface */ 471 DEVMETHOD(device_probe, rsb_probe), 472 DEVMETHOD(device_attach, rsb_attach), 473 474 /* Bus interface */ 475 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 476 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 477 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), 478 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 479 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 480 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 481 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 482 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 483 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 484 485 /* OFW methods */ 486 DEVMETHOD(ofw_bus_get_node, rsb_get_node), 487 488 /* iicbus interface */ 489 DEVMETHOD(iicbus_callback, iicbus_null_callback), 490 DEVMETHOD(iicbus_reset, rsb_reset), 491 DEVMETHOD(iicbus_transfer, rsb_transfer), 492 493 DEVMETHOD_END 494 }; 495 496 static driver_t rsb_driver = { 497 "iichb", 498 rsb_methods, 499 sizeof(struct rsb_softc), 500 }; 501 502 EARLY_DRIVER_MODULE(iicbus, rsb, iicbus_driver, 0, 0, 503 BUS_PASS_SUPPORTDEV + BUS_PASS_ORDER_MIDDLE); 504 EARLY_DRIVER_MODULE(rsb, simplebus, rsb_driver, 0, 0, 505 BUS_PASS_SUPPORTDEV + BUS_PASS_ORDER_MIDDLE); 506 MODULE_VERSION(rsb, 1); 507 MODULE_DEPEND(rsb, iicbus, 1, 1, 1); 508 SIMPLEBUS_PNP_INFO(compat_data); 509