14b9a54a9SJared McNeill /*- 24b9a54a9SJared McNeill * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca> 34b9a54a9SJared McNeill * All rights reserved. 44b9a54a9SJared McNeill * 54b9a54a9SJared McNeill * Redistribution and use in source and binary forms, with or without 64b9a54a9SJared McNeill * modification, are permitted provided that the following conditions 74b9a54a9SJared McNeill * are met: 84b9a54a9SJared McNeill * 1. Redistributions of source code must retain the above copyright 94b9a54a9SJared McNeill * notice, this list of conditions and the following disclaimer. 104b9a54a9SJared McNeill * 2. Redistributions in binary form must reproduce the above copyright 114b9a54a9SJared McNeill * notice, this list of conditions and the following disclaimer in the 124b9a54a9SJared McNeill * documentation and/or other materials provided with the distribution. 134b9a54a9SJared McNeill * 144b9a54a9SJared McNeill * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 154b9a54a9SJared McNeill * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 164b9a54a9SJared McNeill * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 174b9a54a9SJared McNeill * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 184b9a54a9SJared McNeill * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 194b9a54a9SJared McNeill * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 204b9a54a9SJared McNeill * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 214b9a54a9SJared McNeill * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 224b9a54a9SJared McNeill * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 234b9a54a9SJared McNeill * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 244b9a54a9SJared McNeill * SUCH DAMAGE. 254b9a54a9SJared McNeill * 264b9a54a9SJared McNeill * $FreeBSD$ 274b9a54a9SJared McNeill */ 284b9a54a9SJared McNeill 294b9a54a9SJared McNeill /* 304b9a54a9SJared McNeill * Allwinner RSB (Reduced Serial Bus) 314b9a54a9SJared McNeill */ 324b9a54a9SJared McNeill 334b9a54a9SJared McNeill #include <sys/cdefs.h> 344b9a54a9SJared McNeill __FBSDID("$FreeBSD$"); 354b9a54a9SJared McNeill 364b9a54a9SJared McNeill #include <sys/param.h> 374b9a54a9SJared McNeill #include <sys/systm.h> 384b9a54a9SJared McNeill #include <sys/bus.h> 394b9a54a9SJared McNeill #include <sys/rman.h> 404b9a54a9SJared McNeill #include <sys/kernel.h> 41*37cc9a03SJared McNeill #include <sys/proc.h> 424b9a54a9SJared McNeill #include <sys/module.h> 434b9a54a9SJared McNeill #include <machine/bus.h> 444b9a54a9SJared McNeill 454b9a54a9SJared McNeill #include <dev/ofw/ofw_bus.h> 464b9a54a9SJared McNeill #include <dev/ofw/ofw_bus_subr.h> 474b9a54a9SJared McNeill 484b9a54a9SJared McNeill #include <dev/iicbus/iiconf.h> 494b9a54a9SJared McNeill #include <dev/iicbus/iicbus.h> 504b9a54a9SJared McNeill 514b9a54a9SJared McNeill #include <dev/extres/clk/clk.h> 524b9a54a9SJared McNeill #include <dev/extres/hwreset/hwreset.h> 534b9a54a9SJared McNeill 544b9a54a9SJared McNeill #include "iicbus_if.h" 554b9a54a9SJared McNeill 564b9a54a9SJared McNeill #define RSB_CTRL 0x00 574b9a54a9SJared McNeill #define START_TRANS (1 << 7) 584b9a54a9SJared McNeill #define GLOBAL_INT_ENB (1 << 1) 594b9a54a9SJared McNeill #define SOFT_RESET (1 << 0) 604b9a54a9SJared McNeill #define RSB_CCR 0x04 614b9a54a9SJared McNeill #define RSB_INTE 0x08 624b9a54a9SJared McNeill #define RSB_INTS 0x0c 634b9a54a9SJared McNeill #define INT_TRANS_ERR_ID(x) (((x) >> 8) & 0xf) 644b9a54a9SJared McNeill #define INT_LOAD_BSY (1 << 2) 654b9a54a9SJared McNeill #define INT_TRANS_ERR (1 << 1) 664b9a54a9SJared McNeill #define INT_TRANS_OVER (1 << 0) 674b9a54a9SJared McNeill #define INT_MASK (INT_LOAD_BSY|INT_TRANS_ERR|INT_TRANS_OVER) 684b9a54a9SJared McNeill #define RSB_DADDR0 0x10 694b9a54a9SJared McNeill #define RSB_DADDR1 0x14 704b9a54a9SJared McNeill #define RSB_DLEN 0x18 714b9a54a9SJared McNeill #define DLEN_READ (1 << 4) 724b9a54a9SJared McNeill #define RSB_DATA0 0x1c 734b9a54a9SJared McNeill #define RSB_DATA1 0x20 744b9a54a9SJared McNeill #define RSB_CMD 0x2c 754b9a54a9SJared McNeill #define CMD_SRTA 0xe8 764b9a54a9SJared McNeill #define CMD_RD8 0x8b 774b9a54a9SJared McNeill #define CMD_RD16 0x9c 784b9a54a9SJared McNeill #define CMD_RD32 0xa6 794b9a54a9SJared McNeill #define CMD_WR8 0x4e 804b9a54a9SJared McNeill #define CMD_WR16 0x59 814b9a54a9SJared McNeill #define CMD_WR32 0x63 824b9a54a9SJared McNeill #define RSB_DAR 0x30 834b9a54a9SJared McNeill #define DAR_RTA (0xff << 16) 844b9a54a9SJared McNeill #define DAR_RTA_SHIFT 16 854b9a54a9SJared McNeill #define DAR_DA (0xffff << 0) 864b9a54a9SJared McNeill #define DAR_DA_SHIFT 0 874b9a54a9SJared McNeill 884b9a54a9SJared McNeill #define RSB_MAXLEN 8 894b9a54a9SJared McNeill #define RSB_RESET_RETRY 100 904b9a54a9SJared McNeill #define RSB_I2C_TIMEOUT hz 914b9a54a9SJared McNeill 924b9a54a9SJared McNeill #define RSB_ADDR_PMIC_PRIMARY 0x3a3 934b9a54a9SJared McNeill #define RSB_ADDR_PMIC_SECONDARY 0x745 944b9a54a9SJared McNeill #define RSB_ADDR_PERIPH_IC 0xe89 954b9a54a9SJared McNeill 964b9a54a9SJared McNeill static struct ofw_compat_data compat_data[] = { 974b9a54a9SJared McNeill { "allwinner,sun8i-a23-rsb", 1 }, 984b9a54a9SJared McNeill { NULL, 0 } 994b9a54a9SJared McNeill }; 1004b9a54a9SJared McNeill 1014b9a54a9SJared McNeill static struct resource_spec rsb_spec[] = { 1024b9a54a9SJared McNeill { SYS_RES_MEMORY, 0, RF_ACTIVE }, 1034b9a54a9SJared McNeill { SYS_RES_IRQ, 0, RF_ACTIVE }, 1044b9a54a9SJared McNeill { -1, 0 } 1054b9a54a9SJared McNeill }; 1064b9a54a9SJared McNeill 1074b9a54a9SJared McNeill /* 1084b9a54a9SJared McNeill * Device address to Run-time address mappings. 1094b9a54a9SJared McNeill * 1104b9a54a9SJared McNeill * Run-time address (RTA) is an 8-bit value used to address the device during 1114b9a54a9SJared McNeill * a read or write transaction. The following are valid RTAs: 1124b9a54a9SJared McNeill * 0x17 0x2d 0x3a 0x4e 0x59 0x63 0x74 0x8b 0x9c 0xa6 0xb1 0xc5 0xd2 0xe8 0xff 1134b9a54a9SJared McNeill * 1144b9a54a9SJared McNeill * Allwinner uses RTA 0x2d for the primary PMIC, 0x3a for the secondary PMIC, 1154b9a54a9SJared McNeill * and 0x4e for the peripheral IC (where applicable). 1164b9a54a9SJared McNeill */ 1174b9a54a9SJared McNeill static const struct { 1184b9a54a9SJared McNeill uint16_t addr; 1194b9a54a9SJared McNeill uint8_t rta; 1204b9a54a9SJared McNeill } rsb_rtamap[] = { 1214b9a54a9SJared McNeill { .addr = RSB_ADDR_PMIC_PRIMARY, .rta = 0x2d }, 1224b9a54a9SJared McNeill { .addr = RSB_ADDR_PMIC_SECONDARY, .rta = 0x3a }, 1234b9a54a9SJared McNeill { .addr = RSB_ADDR_PERIPH_IC, .rta = 0x4e }, 1244b9a54a9SJared McNeill { .addr = 0, .rta = 0 } 1254b9a54a9SJared McNeill }; 1264b9a54a9SJared McNeill 1274b9a54a9SJared McNeill struct rsb_softc { 1284b9a54a9SJared McNeill struct resource *res[2]; 1294b9a54a9SJared McNeill struct mtx mtx; 1304b9a54a9SJared McNeill clk_t clk; 1314b9a54a9SJared McNeill hwreset_t rst; 1324b9a54a9SJared McNeill device_t iicbus; 1334b9a54a9SJared McNeill void *ih; 1344b9a54a9SJared McNeill int busy; 1354b9a54a9SJared McNeill uint32_t status; 1364b9a54a9SJared McNeill uint16_t cur_addr; 1374b9a54a9SJared McNeill 1384b9a54a9SJared McNeill struct iic_msg *msg; 1394b9a54a9SJared McNeill }; 1404b9a54a9SJared McNeill 1414b9a54a9SJared McNeill #define RSB_LOCK(sc) mtx_lock(&(sc)->mtx) 1424b9a54a9SJared McNeill #define RSB_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 1434b9a54a9SJared McNeill #define RSB_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED) 1444b9a54a9SJared McNeill #define RSB_READ(sc, reg) bus_read_4((sc)->res[0], (reg)) 1454b9a54a9SJared McNeill #define RSB_WRITE(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val)) 1464b9a54a9SJared McNeill 1474b9a54a9SJared McNeill static phandle_t 1484b9a54a9SJared McNeill rsb_get_node(device_t bus, device_t dev) 1494b9a54a9SJared McNeill { 1504b9a54a9SJared McNeill return (ofw_bus_get_node(bus)); 1514b9a54a9SJared McNeill } 1524b9a54a9SJared McNeill 1534b9a54a9SJared McNeill static int 1544b9a54a9SJared McNeill rsb_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) 1554b9a54a9SJared McNeill { 1564b9a54a9SJared McNeill struct rsb_softc *sc; 1574b9a54a9SJared McNeill int retry; 1584b9a54a9SJared McNeill 1594b9a54a9SJared McNeill sc = device_get_softc(dev); 1604b9a54a9SJared McNeill 1614b9a54a9SJared McNeill RSB_LOCK(sc); 1624b9a54a9SJared McNeill 1634b9a54a9SJared McNeill /* Write soft-reset bit and wait for it to self-clear. */ 1644b9a54a9SJared McNeill RSB_WRITE(sc, RSB_CTRL, SOFT_RESET); 1654b9a54a9SJared McNeill for (retry = RSB_RESET_RETRY; retry > 0; retry--) 1664b9a54a9SJared McNeill if ((RSB_READ(sc, RSB_CTRL) & SOFT_RESET) == 0) 1674b9a54a9SJared McNeill break; 1684b9a54a9SJared McNeill 1694b9a54a9SJared McNeill RSB_UNLOCK(sc); 1704b9a54a9SJared McNeill 1714b9a54a9SJared McNeill if (retry == 0) { 1724b9a54a9SJared McNeill device_printf(dev, "soft reset timeout\n"); 1734b9a54a9SJared McNeill return (ETIMEDOUT); 1744b9a54a9SJared McNeill } 1754b9a54a9SJared McNeill 1764b9a54a9SJared McNeill return (IIC_ENOADDR); 1774b9a54a9SJared McNeill } 1784b9a54a9SJared McNeill 1794b9a54a9SJared McNeill static uint32_t 1804b9a54a9SJared McNeill rsb_encode(const uint8_t *buf, u_int len, u_int off) 1814b9a54a9SJared McNeill { 1824b9a54a9SJared McNeill uint32_t val; 1834b9a54a9SJared McNeill u_int n; 1844b9a54a9SJared McNeill 1854b9a54a9SJared McNeill val = 0; 1864b9a54a9SJared McNeill for (n = off; n < MIN(len, 4 + off); n++) 1874b9a54a9SJared McNeill val |= ((uint32_t)buf[n] << ((n - off) * NBBY)); 1884b9a54a9SJared McNeill 1894b9a54a9SJared McNeill return val; 1904b9a54a9SJared McNeill } 1914b9a54a9SJared McNeill 1924b9a54a9SJared McNeill static void 1934b9a54a9SJared McNeill rsb_decode(const uint32_t val, uint8_t *buf, u_int len, u_int off) 1944b9a54a9SJared McNeill { 1954b9a54a9SJared McNeill u_int n; 1964b9a54a9SJared McNeill 1974b9a54a9SJared McNeill for (n = off; n < MIN(len, 4 + off); n++) 1984b9a54a9SJared McNeill buf[n] = (val >> ((n - off) * NBBY)) & 0xff; 1994b9a54a9SJared McNeill } 2004b9a54a9SJared McNeill 2014b9a54a9SJared McNeill static int 2024b9a54a9SJared McNeill rsb_start(device_t dev) 2034b9a54a9SJared McNeill { 2044b9a54a9SJared McNeill struct rsb_softc *sc; 205*37cc9a03SJared McNeill int error, retry, polling; 2064b9a54a9SJared McNeill 2074b9a54a9SJared McNeill sc = device_get_softc(dev); 208*37cc9a03SJared McNeill polling = cold || !THREAD_CAN_SLEEP(); 2094b9a54a9SJared McNeill 2104b9a54a9SJared McNeill RSB_ASSERT_LOCKED(sc); 2114b9a54a9SJared McNeill 2124b9a54a9SJared McNeill /* Enable interrupts */ 213*37cc9a03SJared McNeill if (!polling) 2144b9a54a9SJared McNeill RSB_WRITE(sc, RSB_INTE, INT_MASK); 2154b9a54a9SJared McNeill 2164b9a54a9SJared McNeill /* Start the transfer */ 2174b9a54a9SJared McNeill RSB_WRITE(sc, RSB_CTRL, GLOBAL_INT_ENB | START_TRANS); 2184b9a54a9SJared McNeill 2194b9a54a9SJared McNeill /* Wait for transfer to complete */ 220*37cc9a03SJared McNeill if (polling) { 2214b9a54a9SJared McNeill error = ETIMEDOUT; 2224b9a54a9SJared McNeill for (retry = RSB_I2C_TIMEOUT; retry > 0; retry--) { 2234b9a54a9SJared McNeill sc->status |= RSB_READ(sc, RSB_INTS); 2244b9a54a9SJared McNeill if ((sc->status & INT_TRANS_OVER) != 0) { 2254b9a54a9SJared McNeill error = 0; 2264b9a54a9SJared McNeill break; 2274b9a54a9SJared McNeill } 2284b9a54a9SJared McNeill DELAY((1000 * hz) / RSB_I2C_TIMEOUT); 2294b9a54a9SJared McNeill } 2304b9a54a9SJared McNeill } else { 2314b9a54a9SJared McNeill error = mtx_sleep(sc, &sc->mtx, 0, "i2ciowait", 2324b9a54a9SJared McNeill RSB_I2C_TIMEOUT); 2334b9a54a9SJared McNeill } 2344b9a54a9SJared McNeill if (error == 0 && (sc->status & INT_TRANS_OVER) == 0) { 2354b9a54a9SJared McNeill device_printf(dev, "transfer error, status 0x%08x\n", 2364b9a54a9SJared McNeill sc->status); 2374b9a54a9SJared McNeill error = EIO; 2384b9a54a9SJared McNeill } 2394b9a54a9SJared McNeill 2404b9a54a9SJared McNeill /* Disable interrupts */ 2414b9a54a9SJared McNeill RSB_WRITE(sc, RSB_INTE, 0); 2424b9a54a9SJared McNeill 2434b9a54a9SJared McNeill return (error); 2444b9a54a9SJared McNeill 2454b9a54a9SJared McNeill } 2464b9a54a9SJared McNeill 2474b9a54a9SJared McNeill static int 2484b9a54a9SJared McNeill rsb_set_rta(device_t dev, uint16_t addr) 2494b9a54a9SJared McNeill { 2504b9a54a9SJared McNeill struct rsb_softc *sc; 2514b9a54a9SJared McNeill uint8_t rta; 2524b9a54a9SJared McNeill int i; 2534b9a54a9SJared McNeill 2544b9a54a9SJared McNeill sc = device_get_softc(dev); 2554b9a54a9SJared McNeill 2564b9a54a9SJared McNeill RSB_ASSERT_LOCKED(sc); 2574b9a54a9SJared McNeill 2584b9a54a9SJared McNeill /* Lookup run-time address for given device address */ 2594b9a54a9SJared McNeill for (rta = 0, i = 0; rsb_rtamap[i].rta != 0; i++) 2604b9a54a9SJared McNeill if (rsb_rtamap[i].addr == addr) { 2614b9a54a9SJared McNeill rta = rsb_rtamap[i].rta; 2624b9a54a9SJared McNeill break; 2634b9a54a9SJared McNeill } 2644b9a54a9SJared McNeill if (rta == 0) { 2654b9a54a9SJared McNeill device_printf(dev, "RTA not known for address %#x\n", addr); 2664b9a54a9SJared McNeill return (ENXIO); 2674b9a54a9SJared McNeill } 2684b9a54a9SJared McNeill 2694b9a54a9SJared McNeill /* Set run-time address */ 2704b9a54a9SJared McNeill RSB_WRITE(sc, RSB_INTS, RSB_READ(sc, RSB_INTS)); 2714b9a54a9SJared McNeill RSB_WRITE(sc, RSB_DAR, (addr << DAR_DA_SHIFT) | (rta << DAR_RTA_SHIFT)); 2724b9a54a9SJared McNeill RSB_WRITE(sc, RSB_CMD, CMD_SRTA); 2734b9a54a9SJared McNeill 2744b9a54a9SJared McNeill return (rsb_start(dev)); 2754b9a54a9SJared McNeill } 2764b9a54a9SJared McNeill 2774b9a54a9SJared McNeill static int 2784b9a54a9SJared McNeill rsb_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) 2794b9a54a9SJared McNeill { 2804b9a54a9SJared McNeill struct rsb_softc *sc; 2814b9a54a9SJared McNeill uint32_t daddr[2], data[2], dlen; 2824b9a54a9SJared McNeill uint16_t device_addr; 2834b9a54a9SJared McNeill uint8_t cmd; 2844b9a54a9SJared McNeill int error; 2854b9a54a9SJared McNeill 2864b9a54a9SJared McNeill sc = device_get_softc(dev); 2874b9a54a9SJared McNeill 2884b9a54a9SJared McNeill /* 2894b9a54a9SJared McNeill * RSB is not really an I2C or SMBus controller, so there are some 2904b9a54a9SJared McNeill * restrictions imposed by the driver. 2914b9a54a9SJared McNeill * 2924b9a54a9SJared McNeill * Transfers must contain exactly two messages. The first is always 2934b9a54a9SJared McNeill * a write, containing a single data byte offset. Data will either 2944b9a54a9SJared McNeill * be read from or written to the corresponding data byte in the 2954b9a54a9SJared McNeill * second message. The slave address in both messages must be the 2964b9a54a9SJared McNeill * same. 2974b9a54a9SJared McNeill */ 2984b9a54a9SJared McNeill if (nmsgs != 2 || (msgs[0].flags & IIC_M_RD) == IIC_M_RD || 2994b9a54a9SJared McNeill (msgs[0].slave >> 1) != (msgs[1].slave >> 1) || 3004b9a54a9SJared McNeill msgs[0].len != 1 || msgs[1].len > RSB_MAXLEN) 3014b9a54a9SJared McNeill return (EINVAL); 3024b9a54a9SJared McNeill 3034b9a54a9SJared McNeill /* The controller can read or write 1, 2, or 4 bytes at a time. */ 3044b9a54a9SJared McNeill if ((msgs[1].flags & IIC_M_RD) != 0) { 3054b9a54a9SJared McNeill switch (msgs[1].len) { 3064b9a54a9SJared McNeill case 1: 3074b9a54a9SJared McNeill cmd = CMD_RD8; 3084b9a54a9SJared McNeill break; 3094b9a54a9SJared McNeill case 2: 3104b9a54a9SJared McNeill cmd = CMD_RD16; 3114b9a54a9SJared McNeill break; 3124b9a54a9SJared McNeill case 4: 3134b9a54a9SJared McNeill cmd = CMD_RD32; 3144b9a54a9SJared McNeill break; 3154b9a54a9SJared McNeill default: 3164b9a54a9SJared McNeill return (EINVAL); 3174b9a54a9SJared McNeill } 3184b9a54a9SJared McNeill } else { 3194b9a54a9SJared McNeill switch (msgs[1].len) { 3204b9a54a9SJared McNeill case 1: 3214b9a54a9SJared McNeill cmd = CMD_WR8; 3224b9a54a9SJared McNeill break; 3234b9a54a9SJared McNeill case 2: 3244b9a54a9SJared McNeill cmd = CMD_WR16; 3254b9a54a9SJared McNeill break; 3264b9a54a9SJared McNeill case 4: 3274b9a54a9SJared McNeill cmd = CMD_WR32; 3284b9a54a9SJared McNeill break; 3294b9a54a9SJared McNeill default: 3304b9a54a9SJared McNeill return (EINVAL); 3314b9a54a9SJared McNeill } 3324b9a54a9SJared McNeill } 3334b9a54a9SJared McNeill 3344b9a54a9SJared McNeill RSB_LOCK(sc); 3354b9a54a9SJared McNeill while (sc->busy) 3364b9a54a9SJared McNeill mtx_sleep(sc, &sc->mtx, 0, "i2cbuswait", 0); 3374b9a54a9SJared McNeill sc->busy = 1; 3384b9a54a9SJared McNeill sc->status = 0; 3394b9a54a9SJared McNeill 3404b9a54a9SJared McNeill /* Select current run-time address if necessary */ 3414b9a54a9SJared McNeill device_addr = msgs[0].slave >> 1; 3424b9a54a9SJared McNeill if (sc->cur_addr != device_addr) { 3434b9a54a9SJared McNeill error = rsb_set_rta(dev, device_addr); 3444b9a54a9SJared McNeill if (error != 0) 3454b9a54a9SJared McNeill goto done; 3464b9a54a9SJared McNeill sc->cur_addr = device_addr; 3474b9a54a9SJared McNeill sc->status = 0; 3484b9a54a9SJared McNeill } 3494b9a54a9SJared McNeill 3504b9a54a9SJared McNeill /* Clear interrupt status */ 3514b9a54a9SJared McNeill RSB_WRITE(sc, RSB_INTS, RSB_READ(sc, RSB_INTS)); 3524b9a54a9SJared McNeill 3534b9a54a9SJared McNeill /* Program data access address registers */ 3544b9a54a9SJared McNeill daddr[0] = rsb_encode(msgs[0].buf, msgs[0].len, 0); 3554b9a54a9SJared McNeill RSB_WRITE(sc, RSB_DADDR0, daddr[0]); 3564b9a54a9SJared McNeill 3574b9a54a9SJared McNeill /* Write data */ 3584b9a54a9SJared McNeill if ((msgs[1].flags & IIC_M_RD) == 0) { 3594b9a54a9SJared McNeill data[0] = rsb_encode(msgs[1].buf, msgs[1].len, 0); 3604b9a54a9SJared McNeill RSB_WRITE(sc, RSB_DATA0, data[0]); 3614b9a54a9SJared McNeill } 3624b9a54a9SJared McNeill 3634b9a54a9SJared McNeill /* Set command type */ 3644b9a54a9SJared McNeill RSB_WRITE(sc, RSB_CMD, cmd); 3654b9a54a9SJared McNeill 3664b9a54a9SJared McNeill /* Program data length register and transfer direction */ 3674b9a54a9SJared McNeill dlen = msgs[0].len - 1; 3684b9a54a9SJared McNeill if ((msgs[1].flags & IIC_M_RD) == IIC_M_RD) 3694b9a54a9SJared McNeill dlen |= DLEN_READ; 3704b9a54a9SJared McNeill RSB_WRITE(sc, RSB_DLEN, dlen); 3714b9a54a9SJared McNeill 3724b9a54a9SJared McNeill /* Start transfer */ 3734b9a54a9SJared McNeill error = rsb_start(dev); 3744b9a54a9SJared McNeill if (error != 0) 3754b9a54a9SJared McNeill goto done; 3764b9a54a9SJared McNeill 3774b9a54a9SJared McNeill /* Read data */ 3784b9a54a9SJared McNeill if ((msgs[1].flags & IIC_M_RD) == IIC_M_RD) { 3794b9a54a9SJared McNeill data[0] = RSB_READ(sc, RSB_DATA0); 3804b9a54a9SJared McNeill rsb_decode(data[0], msgs[1].buf, msgs[1].len, 0); 3814b9a54a9SJared McNeill } 3824b9a54a9SJared McNeill 3834b9a54a9SJared McNeill done: 3844b9a54a9SJared McNeill sc->msg = NULL; 3854b9a54a9SJared McNeill sc->busy = 0; 3864b9a54a9SJared McNeill wakeup(sc); 3874b9a54a9SJared McNeill RSB_UNLOCK(sc); 3884b9a54a9SJared McNeill 3894b9a54a9SJared McNeill return (error); 3904b9a54a9SJared McNeill } 3914b9a54a9SJared McNeill 3924b9a54a9SJared McNeill static void 3934b9a54a9SJared McNeill rsb_intr(void *arg) 3944b9a54a9SJared McNeill { 3954b9a54a9SJared McNeill struct rsb_softc *sc; 3964b9a54a9SJared McNeill uint32_t val; 3974b9a54a9SJared McNeill 3984b9a54a9SJared McNeill sc = arg; 3994b9a54a9SJared McNeill 4004b9a54a9SJared McNeill RSB_LOCK(sc); 4014b9a54a9SJared McNeill val = RSB_READ(sc, RSB_INTS); 4024b9a54a9SJared McNeill RSB_WRITE(sc, RSB_INTS, val); 4034b9a54a9SJared McNeill sc->status |= val; 4044b9a54a9SJared McNeill if ((sc->status & INT_MASK) != 0) 4054b9a54a9SJared McNeill wakeup(sc); 4064b9a54a9SJared McNeill RSB_UNLOCK(sc); 4074b9a54a9SJared McNeill } 4084b9a54a9SJared McNeill 4094b9a54a9SJared McNeill static int 4104b9a54a9SJared McNeill rsb_probe(device_t dev) 4114b9a54a9SJared McNeill { 4124b9a54a9SJared McNeill if (!ofw_bus_status_okay(dev)) 4134b9a54a9SJared McNeill return (ENXIO); 4144b9a54a9SJared McNeill 4154b9a54a9SJared McNeill if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 4164b9a54a9SJared McNeill return (ENXIO); 4174b9a54a9SJared McNeill 4184b9a54a9SJared McNeill device_set_desc(dev, "Allwinner RSB"); 4194b9a54a9SJared McNeill return (BUS_PROBE_DEFAULT); 4204b9a54a9SJared McNeill } 4214b9a54a9SJared McNeill 4224b9a54a9SJared McNeill static int 4234b9a54a9SJared McNeill rsb_attach(device_t dev) 4244b9a54a9SJared McNeill { 4254b9a54a9SJared McNeill struct rsb_softc *sc; 4264b9a54a9SJared McNeill int error; 4274b9a54a9SJared McNeill 4284b9a54a9SJared McNeill sc = device_get_softc(dev); 4294b9a54a9SJared McNeill mtx_init(&sc->mtx, device_get_nameunit(dev), "rsb", MTX_DEF); 4304b9a54a9SJared McNeill 4314b9a54a9SJared McNeill if (clk_get_by_ofw_index(dev, 0, &sc->clk) == 0) { 4324b9a54a9SJared McNeill error = clk_enable(sc->clk); 4334b9a54a9SJared McNeill if (error != 0) { 4344b9a54a9SJared McNeill device_printf(dev, "cannot enable clock\n"); 4354b9a54a9SJared McNeill goto fail; 4364b9a54a9SJared McNeill } 4374b9a54a9SJared McNeill } 4384b9a54a9SJared McNeill if (hwreset_get_by_ofw_idx(dev, 0, &sc->rst) == 0) { 4394b9a54a9SJared McNeill error = hwreset_deassert(sc->rst); 4404b9a54a9SJared McNeill if (error != 0) { 4414b9a54a9SJared McNeill device_printf(dev, "cannot de-assert reset\n"); 4424b9a54a9SJared McNeill goto fail; 4434b9a54a9SJared McNeill } 4444b9a54a9SJared McNeill } 4454b9a54a9SJared McNeill 4464b9a54a9SJared McNeill if (bus_alloc_resources(dev, rsb_spec, sc->res) != 0) { 4474b9a54a9SJared McNeill device_printf(dev, "cannot allocate resources for device\n"); 4484b9a54a9SJared McNeill error = ENXIO; 4494b9a54a9SJared McNeill goto fail; 4504b9a54a9SJared McNeill } 4514b9a54a9SJared McNeill 4524b9a54a9SJared McNeill error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_MISC | INTR_MPSAFE, 4534b9a54a9SJared McNeill NULL, rsb_intr, sc, &sc->ih); 4544b9a54a9SJared McNeill if (error != 0) { 4554b9a54a9SJared McNeill device_printf(dev, "cannot setup interrupt handler\n"); 4564b9a54a9SJared McNeill goto fail; 4574b9a54a9SJared McNeill } 4584b9a54a9SJared McNeill 4594b9a54a9SJared McNeill sc->iicbus = device_add_child(dev, "iicbus", -1); 4604b9a54a9SJared McNeill if (sc->iicbus == NULL) { 4614b9a54a9SJared McNeill device_printf(dev, "cannot add iicbus child device\n"); 4624b9a54a9SJared McNeill error = ENXIO; 4634b9a54a9SJared McNeill goto fail; 4644b9a54a9SJared McNeill } 4654b9a54a9SJared McNeill 4664b9a54a9SJared McNeill bus_generic_attach(dev); 4674b9a54a9SJared McNeill 4684b9a54a9SJared McNeill return (0); 4694b9a54a9SJared McNeill 4704b9a54a9SJared McNeill fail: 4714b9a54a9SJared McNeill if (sc->ih != NULL) 4724b9a54a9SJared McNeill bus_teardown_intr(dev, sc->res[1], sc->ih); 4734b9a54a9SJared McNeill bus_release_resources(dev, rsb_spec, sc->res); 4744b9a54a9SJared McNeill if (sc->rst != NULL) 4754b9a54a9SJared McNeill hwreset_release(sc->rst); 4764b9a54a9SJared McNeill if (sc->clk != NULL) 4774b9a54a9SJared McNeill clk_release(sc->clk); 4784b9a54a9SJared McNeill mtx_destroy(&sc->mtx); 4794b9a54a9SJared McNeill return (error); 4804b9a54a9SJared McNeill } 4814b9a54a9SJared McNeill 4824b9a54a9SJared McNeill static device_method_t rsb_methods[] = { 4834b9a54a9SJared McNeill /* Device interface */ 4844b9a54a9SJared McNeill DEVMETHOD(device_probe, rsb_probe), 4854b9a54a9SJared McNeill DEVMETHOD(device_attach, rsb_attach), 4864b9a54a9SJared McNeill 487*37cc9a03SJared McNeill /* Bus interface */ 488*37cc9a03SJared McNeill DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 489*37cc9a03SJared McNeill DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 490*37cc9a03SJared McNeill DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), 491*37cc9a03SJared McNeill DEVMETHOD(bus_release_resource, bus_generic_release_resource), 492*37cc9a03SJared McNeill DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 493*37cc9a03SJared McNeill DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 494*37cc9a03SJared McNeill DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 495*37cc9a03SJared McNeill DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 496*37cc9a03SJared McNeill DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 497*37cc9a03SJared McNeill 4984b9a54a9SJared McNeill /* OFW methods */ 4994b9a54a9SJared McNeill DEVMETHOD(ofw_bus_get_node, rsb_get_node), 5004b9a54a9SJared McNeill 5014b9a54a9SJared McNeill /* iicbus interface */ 5024b9a54a9SJared McNeill DEVMETHOD(iicbus_callback, iicbus_null_callback), 5034b9a54a9SJared McNeill DEVMETHOD(iicbus_reset, rsb_reset), 5044b9a54a9SJared McNeill DEVMETHOD(iicbus_transfer, rsb_transfer), 5054b9a54a9SJared McNeill 5064b9a54a9SJared McNeill DEVMETHOD_END 5074b9a54a9SJared McNeill }; 5084b9a54a9SJared McNeill 5094b9a54a9SJared McNeill static driver_t rsb_driver = { 5104b9a54a9SJared McNeill "iichb", 5114b9a54a9SJared McNeill rsb_methods, 5124b9a54a9SJared McNeill sizeof(struct rsb_softc), 5134b9a54a9SJared McNeill }; 5144b9a54a9SJared McNeill 5154b9a54a9SJared McNeill static devclass_t rsb_devclass; 5164b9a54a9SJared McNeill 5174b9a54a9SJared McNeill DRIVER_MODULE(iicbus, rsb, iicbus_driver, iicbus_devclass, 0, 0); 5184b9a54a9SJared McNeill DRIVER_MODULE(rsb, simplebus, rsb_driver, rsb_devclass, 0, 0); 5194b9a54a9SJared McNeill MODULE_VERSION(rsb, 1); 520