1 /*- 2 * Copyright (c) 2016 Emmanuel Vadot <manu@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_platform.h" 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/kernel.h> 36 #include <sys/module.h> 37 #include <sys/proc.h> 38 #include <sys/rman.h> 39 #include <machine/bus.h> 40 #include <machine/intr.h> 41 42 #include <dev/fdt/fdt_common.h> 43 #include <dev/ofw/openfirm.h> 44 #include <dev/ofw/ofw_bus.h> 45 #include <dev/ofw/ofw_bus_subr.h> 46 47 #include <dt-bindings/interrupt-controller/irq.h> 48 49 #include "pic_if.h" 50 51 #define NMI_IRQ_CTRL_REG 0x0 52 #define NMI_IRQ_LOW_LEVEL 0x0 53 #define NMI_IRQ_LOW_EDGE 0x1 54 #define NMI_IRQ_HIGH_LEVEL 0x2 55 #define NMI_IRQ_HIGH_EDGE 0x3 56 #define NMI_IRQ_PENDING_REG 0x4 57 #define NMI_IRQ_ACK (1U << 0) 58 #define A20_NMI_IRQ_ENABLE_REG 0x8 59 #define A31_NMI_IRQ_ENABLE_REG 0x34 60 #define NMI_IRQ_ENABLE (1U << 0) 61 62 #define SC_NMI_READ(_sc, _reg) bus_read_4(_sc->res[0], _reg) 63 #define SC_NMI_WRITE(_sc, _reg, _val) bus_write_4(_sc->res[0], _reg, _val) 64 65 static struct resource_spec aw_nmi_res_spec[] = { 66 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 67 { SYS_RES_IRQ, 0, RF_ACTIVE }, 68 { -1, 0, 0 } 69 }; 70 71 struct aw_nmi_intr { 72 struct intr_irqsrc isrc; 73 u_int irq; 74 enum intr_polarity pol; 75 enum intr_trigger tri; 76 }; 77 78 struct aw_nmi_softc { 79 device_t dev; 80 struct resource * res[2]; 81 void * intrcookie; 82 struct aw_nmi_intr intr; 83 uint8_t enable_reg; 84 }; 85 86 #define A20_NMI 1 87 #define A31_NMI 2 88 89 static struct ofw_compat_data compat_data[] = { 90 {"allwinner,sun7i-a20-sc-nmi", A20_NMI}, 91 {"allwinner,sun6i-a31-sc-nmi", A31_NMI}, 92 93 {NULL, 0}, 94 }; 95 96 static int 97 aw_nmi_intr(void *arg) 98 { 99 struct aw_nmi_softc *sc; 100 101 sc = arg; 102 103 if (SC_NMI_READ(sc, NMI_IRQ_PENDING_REG) == 0) { 104 device_printf(sc->dev, "Spurious interrupt\n"); 105 return (FILTER_HANDLED); 106 } 107 108 if (intr_isrc_dispatch(&sc->intr.isrc, curthread->td_intr_frame) != 0) { 109 SC_NMI_WRITE(sc, sc->enable_reg, !NMI_IRQ_ENABLE); 110 device_printf(sc->dev, "Stray interrupt, NMI disabled\n"); 111 } 112 113 return (FILTER_HANDLED); 114 } 115 116 static void 117 aw_nmi_enable_intr(device_t dev, struct intr_irqsrc *isrc) 118 { 119 struct aw_nmi_softc *sc; 120 121 sc = device_get_softc(dev); 122 123 SC_NMI_WRITE(sc, sc->enable_reg, NMI_IRQ_ENABLE); 124 } 125 126 static void 127 aw_nmi_disable_intr(device_t dev, struct intr_irqsrc *isrc) 128 { 129 struct aw_nmi_softc *sc; 130 131 sc = device_get_softc(dev); 132 133 SC_NMI_WRITE(sc, sc->enable_reg, !NMI_IRQ_ENABLE); 134 } 135 136 static int 137 aw_nmi_map_fdt(device_t dev, u_int ncells, pcell_t *cells, u_int *irqp, 138 enum intr_polarity *polp, enum intr_trigger *trigp) 139 { 140 u_int irq, tripol; 141 enum intr_polarity pol; 142 enum intr_trigger trig; 143 144 if (ncells != 2) { 145 device_printf(dev, "Invalid #interrupt-cells\n"); 146 return (EINVAL); 147 } 148 149 irq = cells[0]; 150 if (irq != 0) { 151 device_printf(dev, "Controller only support irq 0\n"); 152 return (EINVAL); 153 } 154 155 tripol = cells[1]; 156 157 switch (tripol) { 158 case IRQ_TYPE_EDGE_RISING: 159 trig = INTR_TRIGGER_EDGE; 160 pol = INTR_POLARITY_HIGH; 161 break; 162 case IRQ_TYPE_EDGE_FALLING: 163 trig = INTR_TRIGGER_EDGE; 164 pol = INTR_POLARITY_LOW; 165 break; 166 case IRQ_TYPE_LEVEL_HIGH: 167 trig = INTR_TRIGGER_LEVEL; 168 pol = INTR_POLARITY_HIGH; 169 break; 170 case IRQ_TYPE_LEVEL_LOW: 171 trig = INTR_TRIGGER_LEVEL; 172 pol = INTR_POLARITY_LOW; 173 break; 174 default: 175 device_printf(dev, "unsupported trigger/polarity 0x%2x\n", 176 tripol); 177 return (ENOTSUP); 178 } 179 180 *irqp = irq; 181 if (polp != NULL) 182 *polp = pol; 183 if (trigp != NULL) 184 *trigp = trig; 185 return (0); 186 } 187 188 static int 189 aw_nmi_map_intr(device_t dev, struct intr_map_data *data, 190 struct intr_irqsrc **isrcp) 191 { 192 struct intr_map_data_fdt *daf; 193 struct aw_nmi_softc *sc; 194 int error; 195 u_int irq; 196 197 if (data->type != INTR_MAP_DATA_FDT) 198 return (ENOTSUP); 199 200 sc = device_get_softc(dev); 201 daf = (struct intr_map_data_fdt *)data; 202 203 error = aw_nmi_map_fdt(dev, daf->ncells, daf->cells, &irq, NULL, NULL); 204 if (error == 0) 205 *isrcp = &sc->intr.isrc; 206 207 return (error); 208 } 209 210 static int 211 aw_nmi_setup_intr(device_t dev, struct intr_irqsrc *isrc, 212 struct resource *res, struct intr_map_data *data) 213 { 214 struct intr_map_data_fdt *daf; 215 struct aw_nmi_softc *sc; 216 struct aw_nmi_intr *nmi_intr; 217 int error, icfg; 218 u_int irq; 219 enum intr_trigger trig; 220 enum intr_polarity pol; 221 222 /* Get config for interrupt. */ 223 if (data == NULL || data->type != INTR_MAP_DATA_FDT) 224 return (ENOTSUP); 225 226 sc = device_get_softc(dev); 227 nmi_intr = (struct aw_nmi_intr *)isrc; 228 daf = (struct intr_map_data_fdt *)data; 229 230 error = aw_nmi_map_fdt(dev, daf->ncells, daf->cells, &irq, &pol, &trig); 231 if (error != 0) 232 return (error); 233 if (nmi_intr->irq != irq) 234 return (EINVAL); 235 236 /* Compare config if this is not first setup. */ 237 if (isrc->isrc_handlers != 0) { 238 if (pol != nmi_intr->pol || trig != nmi_intr->tri) 239 return (EINVAL); 240 else 241 return (0); 242 } 243 244 nmi_intr->pol = pol; 245 nmi_intr->tri = trig; 246 247 if (trig == INTR_TRIGGER_LEVEL) { 248 if (pol == INTR_POLARITY_LOW) 249 icfg = NMI_IRQ_LOW_LEVEL; 250 else 251 icfg = NMI_IRQ_HIGH_LEVEL; 252 } else { 253 if (pol == INTR_POLARITY_HIGH) 254 icfg = NMI_IRQ_HIGH_EDGE; 255 else 256 icfg = NMI_IRQ_LOW_EDGE; 257 } 258 259 SC_NMI_WRITE(sc, NMI_IRQ_CTRL_REG, icfg); 260 261 return (0); 262 } 263 264 static int 265 aw_nmi_teardown_intr(device_t dev, struct intr_irqsrc *isrc, 266 struct resource *res, struct intr_map_data *data) 267 { 268 struct aw_nmi_softc *sc; 269 270 sc = device_get_softc(dev); 271 272 if (isrc->isrc_handlers == 0) { 273 sc->intr.pol = INTR_POLARITY_CONFORM; 274 sc->intr.tri = INTR_TRIGGER_CONFORM; 275 276 SC_NMI_WRITE(sc, sc->enable_reg, !NMI_IRQ_ENABLE); 277 } 278 279 return (0); 280 } 281 282 static void 283 aw_nmi_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 284 { 285 struct aw_nmi_softc *sc; 286 287 sc = device_get_softc(dev); 288 aw_nmi_disable_intr(dev, isrc); 289 SC_NMI_WRITE(sc, NMI_IRQ_PENDING_REG, NMI_IRQ_ACK); 290 } 291 292 static void 293 aw_nmi_post_ithread(device_t dev, struct intr_irqsrc *isrc) 294 { 295 296 arm_irq_memory_barrier(0); 297 aw_nmi_enable_intr(dev, isrc); 298 } 299 300 static void 301 aw_nmi_post_filter(device_t dev, struct intr_irqsrc *isrc) 302 { 303 struct aw_nmi_softc *sc; 304 305 sc = device_get_softc(dev); 306 307 arm_irq_memory_barrier(0); 308 SC_NMI_WRITE(sc, NMI_IRQ_PENDING_REG, NMI_IRQ_ACK); 309 } 310 311 static int 312 aw_nmi_probe(device_t dev) 313 { 314 315 if (!ofw_bus_status_okay(dev)) 316 return (ENXIO); 317 318 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 319 return (ENXIO); 320 device_set_desc(dev, "Allwinner NMI Controller"); 321 return (BUS_PROBE_DEFAULT); 322 } 323 324 static int 325 aw_nmi_attach(device_t dev) 326 { 327 struct aw_nmi_softc *sc; 328 phandle_t xref; 329 330 sc = device_get_softc(dev); 331 sc->dev = dev; 332 333 if (bus_alloc_resources(dev, aw_nmi_res_spec, sc->res) != 0) { 334 device_printf(dev, "can't allocate device resources\n"); 335 return (ENXIO); 336 } 337 if ((bus_setup_intr(dev, sc->res[1], INTR_TYPE_MISC, 338 aw_nmi_intr, NULL, sc, &sc->intrcookie))) { 339 device_printf(dev, "unable to register interrupt handler\n"); 340 bus_release_resources(dev, aw_nmi_res_spec, sc->res); 341 return (ENXIO); 342 } 343 344 switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) { 345 case A20_NMI: 346 sc->enable_reg = A20_NMI_IRQ_ENABLE_REG; 347 break; 348 case A31_NMI: 349 sc->enable_reg = A31_NMI_IRQ_ENABLE_REG; 350 break; 351 } 352 353 /* Disable and clear interrupts */ 354 SC_NMI_WRITE(sc, sc->enable_reg, !NMI_IRQ_ENABLE); 355 SC_NMI_WRITE(sc, NMI_IRQ_PENDING_REG, NMI_IRQ_ACK); 356 357 xref = OF_xref_from_node(ofw_bus_get_node(dev)); 358 /* Register our isrc */ 359 sc->intr.irq = 0; 360 sc->intr.pol = INTR_POLARITY_CONFORM; 361 sc->intr.tri = INTR_TRIGGER_CONFORM; 362 if (intr_isrc_register(&sc->intr.isrc, sc->dev, 0, "%s,%u", 363 device_get_nameunit(sc->dev), sc->intr.irq) != 0) 364 goto error; 365 366 if (intr_pic_register(dev, (intptr_t)xref) == NULL) { 367 device_printf(dev, "could not register pic\n"); 368 goto error; 369 } 370 return (0); 371 372 error: 373 bus_teardown_intr(dev, sc->res[1], sc->intrcookie); 374 bus_release_resources(dev, aw_nmi_res_spec, sc->res); 375 return (ENXIO); 376 } 377 378 static device_method_t aw_nmi_methods[] = { 379 DEVMETHOD(device_probe, aw_nmi_probe), 380 DEVMETHOD(device_attach, aw_nmi_attach), 381 382 /* Interrupt controller interface */ 383 DEVMETHOD(pic_disable_intr, aw_nmi_disable_intr), 384 DEVMETHOD(pic_enable_intr, aw_nmi_enable_intr), 385 DEVMETHOD(pic_map_intr, aw_nmi_map_intr), 386 DEVMETHOD(pic_setup_intr, aw_nmi_setup_intr), 387 DEVMETHOD(pic_teardown_intr, aw_nmi_teardown_intr), 388 DEVMETHOD(pic_post_filter, aw_nmi_post_filter), 389 DEVMETHOD(pic_post_ithread, aw_nmi_post_ithread), 390 DEVMETHOD(pic_pre_ithread, aw_nmi_pre_ithread), 391 392 {0, 0}, 393 }; 394 395 static driver_t aw_nmi_driver = { 396 "aw_nmi", 397 aw_nmi_methods, 398 sizeof(struct aw_nmi_softc), 399 }; 400 401 static devclass_t aw_nmi_devclass; 402 403 EARLY_DRIVER_MODULE(aw_nmi, simplebus, aw_nmi_driver, 404 aw_nmi_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE); 405