1 /*- 2 * Copyright (c) 2016 Emmanuel Vadot <manu@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_platform.h" 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/kernel.h> 36 #include <sys/module.h> 37 #include <sys/proc.h> 38 #include <sys/rman.h> 39 #include <machine/bus.h> 40 #include <machine/intr.h> 41 42 #include <dev/fdt/fdt_intr.h> 43 #include <dev/ofw/openfirm.h> 44 #include <dev/ofw/ofw_bus.h> 45 #include <dev/ofw/ofw_bus_subr.h> 46 47 #include "pic_if.h" 48 49 #define NMI_IRQ_CTRL_REG 0x0 50 #define NMI_IRQ_LOW_LEVEL 0x0 51 #define NMI_IRQ_LOW_EDGE 0x1 52 #define NMI_IRQ_HIGH_LEVEL 0x2 53 #define NMI_IRQ_HIGH_EDGE 0x3 54 #define NMI_IRQ_PENDING_REG 0x4 55 #define NMI_IRQ_ACK (1U << 0) 56 #define A20_NMI_IRQ_ENABLE_REG 0x8 57 #define A31_NMI_IRQ_ENABLE_REG 0x34 58 #define NMI_IRQ_ENABLE (1U << 0) 59 60 #define SC_NMI_READ(_sc, _reg) bus_read_4(_sc->res[0], _reg) 61 #define SC_NMI_WRITE(_sc, _reg, _val) bus_write_4(_sc->res[0], _reg, _val) 62 63 static struct resource_spec aw_nmi_res_spec[] = { 64 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 65 { SYS_RES_IRQ, 0, RF_ACTIVE }, 66 { -1, 0, 0 } 67 }; 68 69 struct aw_nmi_intr { 70 struct intr_irqsrc isrc; 71 u_int irq; 72 enum intr_polarity pol; 73 enum intr_trigger tri; 74 }; 75 76 struct aw_nmi_softc { 77 device_t dev; 78 struct resource * res[2]; 79 void * intrcookie; 80 struct aw_nmi_intr intr; 81 uint8_t enable_reg; 82 }; 83 84 #define A20_NMI 1 85 #define A31_NMI 2 86 87 static struct ofw_compat_data compat_data[] = { 88 {"allwinner,sun7i-a20-sc-nmi", A20_NMI}, 89 {"allwinner,sun6i-a31-sc-nmi", A31_NMI}, 90 91 {NULL, 0}, 92 }; 93 94 static int 95 aw_nmi_intr(void *arg) 96 { 97 struct aw_nmi_softc *sc; 98 99 sc = arg; 100 101 if (SC_NMI_READ(sc, NMI_IRQ_PENDING_REG) == 0) { 102 device_printf(sc->dev, "Spurious interrupt\n"); 103 return (FILTER_HANDLED); 104 } 105 106 if (intr_isrc_dispatch(&sc->intr.isrc, curthread->td_intr_frame) != 0) { 107 SC_NMI_WRITE(sc, sc->enable_reg, !NMI_IRQ_ENABLE); 108 device_printf(sc->dev, "Stray interrupt, NMI disabled\n"); 109 } 110 111 return (FILTER_HANDLED); 112 } 113 114 static void 115 aw_nmi_enable_intr(device_t dev, struct intr_irqsrc *isrc) 116 { 117 struct aw_nmi_softc *sc; 118 119 sc = device_get_softc(dev); 120 121 SC_NMI_WRITE(sc, sc->enable_reg, NMI_IRQ_ENABLE); 122 } 123 124 static void 125 aw_nmi_disable_intr(device_t dev, struct intr_irqsrc *isrc) 126 { 127 struct aw_nmi_softc *sc; 128 129 sc = device_get_softc(dev); 130 131 SC_NMI_WRITE(sc, sc->enable_reg, !NMI_IRQ_ENABLE); 132 } 133 134 static int 135 aw_nmi_map_fdt(device_t dev, u_int ncells, pcell_t *cells, u_int *irqp, 136 enum intr_polarity *polp, enum intr_trigger *trigp) 137 { 138 u_int irq, tripol; 139 enum intr_polarity pol; 140 enum intr_trigger trig; 141 142 if (ncells != 2) { 143 device_printf(dev, "Invalid #interrupt-cells\n"); 144 return (EINVAL); 145 } 146 147 irq = cells[0]; 148 if (irq != 0) { 149 device_printf(dev, "Controller only support irq 0\n"); 150 return (EINVAL); 151 } 152 153 tripol = cells[1]; 154 155 switch (tripol) { 156 case FDT_INTR_EDGE_RISING: 157 trig = INTR_TRIGGER_EDGE; 158 pol = INTR_POLARITY_HIGH; 159 break; 160 case FDT_INTR_EDGE_FALLING: 161 trig = INTR_TRIGGER_EDGE; 162 pol = INTR_POLARITY_LOW; 163 break; 164 case FDT_INTR_LEVEL_HIGH: 165 trig = INTR_TRIGGER_LEVEL; 166 pol = INTR_POLARITY_HIGH; 167 break; 168 case FDT_INTR_LEVEL_LOW: 169 trig = INTR_TRIGGER_LEVEL; 170 pol = INTR_POLARITY_LOW; 171 break; 172 default: 173 device_printf(dev, "unsupported trigger/polarity 0x%2x\n", 174 tripol); 175 return (ENOTSUP); 176 } 177 178 *irqp = irq; 179 if (polp != NULL) 180 *polp = pol; 181 if (trigp != NULL) 182 *trigp = trig; 183 return (0); 184 } 185 186 static int 187 aw_nmi_map_intr(device_t dev, struct intr_map_data *data, 188 struct intr_irqsrc **isrcp) 189 { 190 struct intr_map_data_fdt *daf; 191 struct aw_nmi_softc *sc; 192 int error; 193 u_int irq; 194 195 if (data->type != INTR_MAP_DATA_FDT) 196 return (ENOTSUP); 197 198 sc = device_get_softc(dev); 199 daf = (struct intr_map_data_fdt *)data; 200 201 error = aw_nmi_map_fdt(dev, daf->ncells, daf->cells, &irq, NULL, NULL); 202 if (error == 0) 203 *isrcp = &sc->intr.isrc; 204 205 return (error); 206 } 207 208 static int 209 aw_nmi_setup_intr(device_t dev, struct intr_irqsrc *isrc, 210 struct resource *res, struct intr_map_data *data) 211 { 212 struct intr_map_data_fdt *daf; 213 struct aw_nmi_softc *sc; 214 struct aw_nmi_intr *nmi_intr; 215 int error, icfg; 216 u_int irq; 217 enum intr_trigger trig; 218 enum intr_polarity pol; 219 220 /* Get config for interrupt. */ 221 if (data == NULL || data->type != INTR_MAP_DATA_FDT) 222 return (ENOTSUP); 223 224 sc = device_get_softc(dev); 225 nmi_intr = (struct aw_nmi_intr *)isrc; 226 daf = (struct intr_map_data_fdt *)data; 227 228 error = aw_nmi_map_fdt(dev, daf->ncells, daf->cells, &irq, &pol, &trig); 229 if (error != 0) 230 return (error); 231 if (nmi_intr->irq != irq) 232 return (EINVAL); 233 234 /* Compare config if this is not first setup. */ 235 if (isrc->isrc_handlers != 0) { 236 if (pol != nmi_intr->pol || trig != nmi_intr->tri) 237 return (EINVAL); 238 else 239 return (0); 240 } 241 242 nmi_intr->pol = pol; 243 nmi_intr->tri = trig; 244 245 if (trig == INTR_TRIGGER_LEVEL) { 246 if (pol == INTR_POLARITY_LOW) 247 icfg = NMI_IRQ_LOW_LEVEL; 248 else 249 icfg = NMI_IRQ_HIGH_LEVEL; 250 } else { 251 if (pol == INTR_POLARITY_HIGH) 252 icfg = NMI_IRQ_HIGH_EDGE; 253 else 254 icfg = NMI_IRQ_LOW_EDGE; 255 } 256 257 SC_NMI_WRITE(sc, NMI_IRQ_CTRL_REG, icfg); 258 259 return (0); 260 } 261 262 static int 263 aw_nmi_teardown_intr(device_t dev, struct intr_irqsrc *isrc, 264 struct resource *res, struct intr_map_data *data) 265 { 266 struct aw_nmi_softc *sc; 267 268 sc = device_get_softc(dev); 269 270 if (isrc->isrc_handlers == 0) { 271 sc->intr.pol = INTR_POLARITY_CONFORM; 272 sc->intr.tri = INTR_TRIGGER_CONFORM; 273 274 SC_NMI_WRITE(sc, sc->enable_reg, !NMI_IRQ_ENABLE); 275 } 276 277 return (0); 278 } 279 280 static void 281 aw_nmi_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 282 { 283 struct aw_nmi_softc *sc; 284 285 sc = device_get_softc(dev); 286 aw_nmi_disable_intr(dev, isrc); 287 SC_NMI_WRITE(sc, NMI_IRQ_PENDING_REG, NMI_IRQ_ACK); 288 } 289 290 static void 291 aw_nmi_post_ithread(device_t dev, struct intr_irqsrc *isrc) 292 { 293 294 arm_irq_memory_barrier(0); 295 aw_nmi_enable_intr(dev, isrc); 296 } 297 298 static void 299 aw_nmi_post_filter(device_t dev, struct intr_irqsrc *isrc) 300 { 301 struct aw_nmi_softc *sc; 302 303 sc = device_get_softc(dev); 304 305 arm_irq_memory_barrier(0); 306 SC_NMI_WRITE(sc, NMI_IRQ_PENDING_REG, NMI_IRQ_ACK); 307 } 308 309 static int 310 aw_nmi_probe(device_t dev) 311 { 312 313 if (!ofw_bus_status_okay(dev)) 314 return (ENXIO); 315 316 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 317 return (ENXIO); 318 device_set_desc(dev, "Allwinner NMI Controller"); 319 return (BUS_PROBE_DEFAULT); 320 } 321 322 static int 323 aw_nmi_attach(device_t dev) 324 { 325 struct aw_nmi_softc *sc; 326 phandle_t xref; 327 328 sc = device_get_softc(dev); 329 sc->dev = dev; 330 331 if (bus_alloc_resources(dev, aw_nmi_res_spec, sc->res) != 0) { 332 device_printf(dev, "can't allocate device resources\n"); 333 return (ENXIO); 334 } 335 if ((bus_setup_intr(dev, sc->res[1], INTR_TYPE_MISC, 336 aw_nmi_intr, NULL, sc, &sc->intrcookie))) { 337 device_printf(dev, "unable to register interrupt handler\n"); 338 bus_release_resources(dev, aw_nmi_res_spec, sc->res); 339 return (ENXIO); 340 } 341 342 switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) { 343 case A20_NMI: 344 sc->enable_reg = A20_NMI_IRQ_ENABLE_REG; 345 break; 346 case A31_NMI: 347 sc->enable_reg = A31_NMI_IRQ_ENABLE_REG; 348 break; 349 } 350 351 /* Disable and clear interrupts */ 352 SC_NMI_WRITE(sc, sc->enable_reg, !NMI_IRQ_ENABLE); 353 SC_NMI_WRITE(sc, NMI_IRQ_PENDING_REG, NMI_IRQ_ACK); 354 355 xref = OF_xref_from_node(ofw_bus_get_node(dev)); 356 /* Register our isrc */ 357 sc->intr.irq = 0; 358 sc->intr.pol = INTR_POLARITY_CONFORM; 359 sc->intr.tri = INTR_TRIGGER_CONFORM; 360 if (intr_isrc_register(&sc->intr.isrc, sc->dev, 0, "%s,%u", 361 device_get_nameunit(sc->dev), sc->intr.irq) != 0) 362 goto error; 363 364 if (intr_pic_register(dev, (intptr_t)xref) == NULL) { 365 device_printf(dev, "could not register pic\n"); 366 goto error; 367 } 368 return (0); 369 370 error: 371 bus_teardown_intr(dev, sc->res[1], sc->intrcookie); 372 bus_release_resources(dev, aw_nmi_res_spec, sc->res); 373 return (ENXIO); 374 } 375 376 static device_method_t aw_nmi_methods[] = { 377 DEVMETHOD(device_probe, aw_nmi_probe), 378 DEVMETHOD(device_attach, aw_nmi_attach), 379 380 /* Interrupt controller interface */ 381 DEVMETHOD(pic_disable_intr, aw_nmi_disable_intr), 382 DEVMETHOD(pic_enable_intr, aw_nmi_enable_intr), 383 DEVMETHOD(pic_map_intr, aw_nmi_map_intr), 384 DEVMETHOD(pic_setup_intr, aw_nmi_setup_intr), 385 DEVMETHOD(pic_teardown_intr, aw_nmi_teardown_intr), 386 DEVMETHOD(pic_post_filter, aw_nmi_post_filter), 387 DEVMETHOD(pic_post_ithread, aw_nmi_post_ithread), 388 DEVMETHOD(pic_pre_ithread, aw_nmi_pre_ithread), 389 390 {0, 0}, 391 }; 392 393 static driver_t aw_nmi_driver = { 394 "aw_nmi", 395 aw_nmi_methods, 396 sizeof(struct aw_nmi_softc), 397 }; 398 399 static devclass_t aw_nmi_devclass; 400 401 EARLY_DRIVER_MODULE(aw_nmi, simplebus, aw_nmi_driver, 402 aw_nmi_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE); 403