1 /*- 2 * Copyright (c) 2014 Ganbold Tsagaankhuu <ganbold@freebsd.org> 3 * Copyright (c) 2016 Emmanuel Vadot <manu@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/kernel.h> 34 #include <sys/lock.h> 35 #include <sys/mutex.h> 36 #include <sys/smp.h> 37 38 #include <vm/vm.h> 39 #include <vm/pmap.h> 40 41 #include <machine/cpu.h> 42 #include <machine/smp.h> 43 #include <machine/fdt.h> 44 #include <machine/intr.h> 45 #include <machine/platformvar.h> 46 47 #include <arm/allwinner/aw_mp.h> 48 #include <arm/allwinner/aw_machdep.h> 49 50 /* Register for all dual-core SoC */ 51 #define A20_CPUCFG_BASE 0x01c25c00 52 /* Register for all quad-core SoC */ 53 #define CPUCFG_BASE 0x01f01c00 54 #define CPUCFG_SIZE 0x400 55 #define PRCM_BASE 0x01f01400 56 #define PRCM_SIZE 0x800 57 /* Register for multi-cluster SoC */ 58 #define CPUXCFG_BASE 0x01700000 59 #define CPUXCFG_SIZE 0x400 60 61 #define CPU_OFFSET 0x40 62 #define CPU_OFFSET_CTL 0x04 63 #define CPU_OFFSET_STATUS 0x08 64 #define CPU_RST_CTL(cpuid) ((cpuid + 1) * CPU_OFFSET) 65 #define CPU_CTL(cpuid) (((cpuid + 1) * CPU_OFFSET) + CPU_OFFSET_CTL) 66 #define CPU_STATUS(cpuid) (((cpuid + 1) * CPU_OFFSET) + CPU_OFFSET_STATUS) 67 68 #define CPU_RESET (1 << 0) 69 #define CPU_CORE_RESET (1 << 1) 70 71 #define CPUCFG_GENCTL 0x184 72 #define CPUCFG_P_REG0 0x1a4 73 74 #define A20_CPU1_PWR_CLAMP 0x1b0 75 #define CPU_PWR_CLAMP_REG 0x140 76 #define CPU_PWR_CLAMP(cpu) ((cpu * 4) + CPU_PWR_CLAMP_REG) 77 #define CPU_PWR_CLAMP_STEPS 8 78 79 #define A20_CPU1_PWROFF_REG 0x1b4 80 #define CPU_PWROFF 0x100 81 82 #define CPUCFG_DBGCTL0 0x1e0 83 #define CPUCFG_DBGCTL1 0x1e4 84 85 #define CPUS_CL_RST(cl) (0x30 + (cl) * 0x4) 86 #define CPUX_CL_CTRL0(cl) (0x0 + (cl) * 0x10) 87 #define CPUX_CL_CTRL1(cl) (0x4 + (cl) * 0x10) 88 #define CPUX_CL_CPU_STATUS(cl) (0x30 + (cl) * 0x4) 89 #define CPUX_CL_RST(cl) (0x80 + (cl) * 0x4) 90 #define PRCM_CL_PWROFF(cl) (0x100 + (cl) * 0x4) 91 #define PRCM_CL_PWR_CLAMP(cl, cpu) (0x140 + (cl) * 0x4 + (cpu) * 0x4) 92 93 void 94 aw_mp_setmaxid(platform_t plat) 95 { 96 int ncpu; 97 uint32_t reg; 98 99 if (mp_ncpus != 0) 100 return; 101 102 reg = cp15_l2ctlr_get(); 103 ncpu = CPUV7_L2CTLR_NPROC(reg); 104 105 mp_ncpus = ncpu; 106 mp_maxid = ncpu - 1; 107 } 108 109 void 110 aw_mp_start_ap(platform_t plat) 111 { 112 bus_space_handle_t cpucfg; 113 bus_space_handle_t prcm; 114 int i, j, soc_family; 115 uint32_t val; 116 117 soc_family = allwinner_soc_family(); 118 if (soc_family == ALLWINNERSOC_SUN7I) { 119 if (bus_space_map(fdtbus_bs_tag, A20_CPUCFG_BASE, CPUCFG_SIZE, 120 0, &cpucfg) != 0) 121 panic("Couldn't map the CPUCFG\n"); 122 } else { 123 if (bus_space_map(fdtbus_bs_tag, CPUCFG_BASE, CPUCFG_SIZE, 124 0, &cpucfg) != 0) 125 panic("Couldn't map the CPUCFG\n"); 126 if (bus_space_map(fdtbus_bs_tag, PRCM_BASE, PRCM_SIZE, 0, 127 &prcm) != 0) 128 panic("Couldn't map the PRCM\n"); 129 } 130 131 dcache_wbinv_poc_all(); 132 133 bus_space_write_4(fdtbus_bs_tag, cpucfg, CPUCFG_P_REG0, 134 pmap_kextract((vm_offset_t)mpentry)); 135 136 /* 137 * Assert nCOREPORESET low and set L1RSTDISABLE low. 138 * Ensure DBGPWRDUP is set to LOW to prevent any external 139 * debug access to the processor. 140 */ 141 for (i = 1; i < mp_ncpus; i++) 142 bus_space_write_4(fdtbus_bs_tag, cpucfg, CPU_RST_CTL(i), 0); 143 144 /* Set L1RSTDISABLE low */ 145 val = bus_space_read_4(fdtbus_bs_tag, cpucfg, CPUCFG_GENCTL); 146 for (i = 1; i < mp_ncpus; i++) 147 val &= ~(1 << i); 148 bus_space_write_4(fdtbus_bs_tag, cpucfg, CPUCFG_GENCTL, val); 149 150 /* Set DBGPWRDUP low */ 151 val = bus_space_read_4(fdtbus_bs_tag, cpucfg, CPUCFG_DBGCTL1); 152 for (i = 1; i < mp_ncpus; i++) 153 val &= ~(1 << i); 154 bus_space_write_4(fdtbus_bs_tag, cpucfg, CPUCFG_DBGCTL1, val); 155 156 /* Release power clamp */ 157 for (i = 1; i < mp_ncpus; i++) 158 for (j = 0; j <= CPU_PWR_CLAMP_STEPS; j++) { 159 if (soc_family != ALLWINNERSOC_SUN7I) { 160 bus_space_write_4(fdtbus_bs_tag, prcm, 161 CPU_PWR_CLAMP(i), 0xff >> j); 162 } else { 163 bus_space_write_4(fdtbus_bs_tag, 164 cpucfg, A20_CPU1_PWR_CLAMP, 0xff >> j); 165 } 166 } 167 DELAY(10000); 168 169 /* Clear power-off gating */ 170 if (soc_family != ALLWINNERSOC_SUN7I) { 171 val = bus_space_read_4(fdtbus_bs_tag, prcm, CPU_PWROFF); 172 for (i = 0; i < mp_ncpus; i++) 173 val &= ~(1 << i); 174 bus_space_write_4(fdtbus_bs_tag, prcm, CPU_PWROFF, val); 175 } else { 176 val = bus_space_read_4(fdtbus_bs_tag, 177 cpucfg, A20_CPU1_PWROFF_REG); 178 val &= ~(1 << 0); 179 bus_space_write_4(fdtbus_bs_tag, cpucfg, 180 A20_CPU1_PWROFF_REG, val); 181 } 182 DELAY(1000); 183 184 /* De-assert cpu core reset */ 185 for (i = 1; i < mp_ncpus; i++) 186 bus_space_write_4(fdtbus_bs_tag, cpucfg, CPU_RST_CTL(i), 187 CPU_RESET | CPU_CORE_RESET); 188 189 /* Assert DBGPWRDUP signal */ 190 val = bus_space_read_4(fdtbus_bs_tag, cpucfg, CPUCFG_DBGCTL1); 191 for (i = 1; i < mp_ncpus; i++) 192 val |= (1 << i); 193 bus_space_write_4(fdtbus_bs_tag, cpucfg, CPUCFG_DBGCTL1, val); 194 195 dsb(); 196 sev(); 197 bus_space_unmap(fdtbus_bs_tag, cpucfg, CPUCFG_SIZE); 198 if (soc_family != ALLWINNERSOC_SUN7I) 199 bus_space_unmap(fdtbus_bs_tag, prcm, PRCM_SIZE); 200 } 201 202 static void 203 aw_mc_mp_start_cpu(bus_space_handle_t cpuscfg, bus_space_handle_t cpuxcfg, 204 bus_space_handle_t prcm, int cluster, int cpu) 205 { 206 uint32_t val; 207 int i; 208 209 /* Assert core reset */ 210 val = bus_space_read_4(fdtbus_bs_tag, cpuxcfg, CPUX_CL_RST(cluster)); 211 val &= ~(1 << cpu); 212 bus_space_write_4(fdtbus_bs_tag, cpuxcfg, CPUX_CL_RST(cluster), val); 213 214 /* Assert power-on reset */ 215 val = bus_space_read_4(fdtbus_bs_tag, cpuscfg, CPUS_CL_RST(cluster)); 216 val &= ~(1 << cpu); 217 bus_space_write_4(fdtbus_bs_tag, cpuscfg, CPUS_CL_RST(cluster), val); 218 219 /* Disable automatic L1 cache invalidate at reset */ 220 val = bus_space_read_4(fdtbus_bs_tag, cpuxcfg, CPUX_CL_CTRL0(cluster)); 221 val &= ~(1 << cpu); 222 bus_space_write_4(fdtbus_bs_tag, cpuxcfg, CPUX_CL_CTRL0(cluster), val); 223 224 /* Release power clamp */ 225 for (i = 0; i <= CPU_PWR_CLAMP_STEPS; i++) 226 bus_space_write_4(fdtbus_bs_tag, prcm, 227 PRCM_CL_PWR_CLAMP(cluster, cpu), 0xff >> i); 228 while (bus_space_read_4(fdtbus_bs_tag, prcm, 229 PRCM_CL_PWR_CLAMP(cluster, cpu)) != 0) 230 ; 231 232 /* Clear power-off gating */ 233 val = bus_space_read_4(fdtbus_bs_tag, prcm, PRCM_CL_PWROFF(cluster)); 234 val &= ~(1 << cpu); 235 bus_space_write_4(fdtbus_bs_tag, prcm, PRCM_CL_PWROFF(cluster), val); 236 237 /* De-assert power-on reset */ 238 val = bus_space_read_4(fdtbus_bs_tag, cpuscfg, CPUS_CL_RST(cluster)); 239 val |= (1 << cpu); 240 bus_space_write_4(fdtbus_bs_tag, cpuscfg, CPUS_CL_RST(cluster), val); 241 242 /* De-assert core reset */ 243 val = bus_space_read_4(fdtbus_bs_tag, cpuxcfg, CPUX_CL_RST(cluster)); 244 val |= (1 << cpu); 245 bus_space_write_4(fdtbus_bs_tag, cpuxcfg, CPUX_CL_RST(cluster), val); 246 } 247 248 static void 249 aw_mc_mp_start_ap(bus_space_handle_t cpuscfg, bus_space_handle_t cpuxcfg, 250 bus_space_handle_t prcm) 251 { 252 int cluster, cpu; 253 254 KASSERT(mp_ncpus <= 4, ("multiple clusters not yet supported")); 255 256 dcache_wbinv_poc_all(); 257 258 bus_space_write_4(fdtbus_bs_tag, cpuscfg, CPUCFG_P_REG0, 259 pmap_kextract((vm_offset_t)mpentry)); 260 261 cluster = 0; 262 for (cpu = 1; cpu < mp_ncpus; cpu++) 263 aw_mc_mp_start_cpu(cpuscfg, cpuxcfg, prcm, cluster, cpu); 264 } 265 266 void 267 a83t_mp_start_ap(platform_t plat) 268 { 269 bus_space_handle_t cpuscfg, cpuxcfg, prcm; 270 271 if (bus_space_map(fdtbus_bs_tag, CPUCFG_BASE, CPUCFG_SIZE, 272 0, &cpuscfg) != 0) 273 panic("Couldn't map the CPUCFG\n"); 274 if (bus_space_map(fdtbus_bs_tag, CPUXCFG_BASE, CPUXCFG_SIZE, 275 0, &cpuxcfg) != 0) 276 panic("Couldn't map the CPUXCFG\n"); 277 if (bus_space_map(fdtbus_bs_tag, PRCM_BASE, PRCM_SIZE, 0, 278 &prcm) != 0) 279 panic("Couldn't map the PRCM\n"); 280 281 aw_mc_mp_start_ap(cpuscfg, cpuxcfg, prcm); 282 dsb(); 283 sev(); 284 bus_space_unmap(fdtbus_bs_tag, cpuxcfg, CPUXCFG_SIZE); 285 bus_space_unmap(fdtbus_bs_tag, cpuscfg, CPUCFG_SIZE); 286 bus_space_unmap(fdtbus_bs_tag, prcm, PRCM_SIZE); 287 } 288