1 /*- 2 * Copyright (c) 2014 Ganbold Tsagaankhuu <ganbold@freebsd.org> 3 * Copyright (c) 2016 Emmanuel Vadot <manu@bidouilliste.com> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/kernel.h> 34 #include <sys/lock.h> 35 #include <sys/mutex.h> 36 #include <sys/smp.h> 37 38 #include <vm/vm.h> 39 #include <vm/pmap.h> 40 41 #include <machine/cpu.h> 42 #include <machine/cpu-v6.h> 43 #include <machine/smp.h> 44 #include <machine/fdt.h> 45 #include <machine/intr.h> 46 #include <machine/platformvar.h> 47 48 #include <arm/allwinner/aw_mp.h> 49 #include <arm/allwinner/allwinner_machdep.h> 50 51 /* Register for all dual-core SoC */ 52 #define A20_CPUCFG_BASE 0x01c25c00 53 /* Register for all quad-core SoC */ 54 #define CPUCFG_BASE 0x01f01c00 55 #define CPUCFG_SIZE 0x400 56 #define PRCM_BASE 0x01f01400 57 #define PRCM_SIZE 0x800 58 59 #define CPU_OFFSET 0x40 60 #define CPU_OFFSET_CTL 0x04 61 #define CPU_OFFSET_STATUS 0x08 62 #define CPU_RST_CTL(cpuid) ((cpuid + 1) * CPU_OFFSET) 63 #define CPU_CTL(cpuid) (((cpuid + 1) * CPU_OFFSET) + CPU_OFFSET_CTL) 64 #define CPU_STATUS(cpuid) (((cpuid + 1) * CPU_OFFSET) + CPU_OFFSET_STATUS) 65 66 #define CPU_RESET (1 << 0) 67 #define CPU_CORE_RESET (1 << 1) 68 69 #define CPUCFG_GENCTL 0x184 70 #define CPUCFG_P_REG0 0x1a4 71 72 #define A20_CPU1_PWR_CLAMP 0x1b0 73 #define CPU_PWR_CLAMP_REG 0x140 74 #define CPU_PWR_CLAMP(cpu) ((cpu * 4) + CPU_PWR_CLAMP_REG) 75 #define CPU_PWR_CLAMP_STEPS 8 76 77 #define A20_CPU1_PWROFF_REG 0x1b4 78 #define CPU_PWROFF 0x100 79 80 #define CPUCFG_DBGCTL0 0x1e0 81 #define CPUCFG_DBGCTL1 0x1e4 82 83 void 84 aw_mp_setmaxid(platform_t plat) 85 { 86 int ncpu; 87 uint32_t reg; 88 89 if (mp_ncpus != 0) 90 return; 91 92 reg = cp15_l2ctlr_get(); 93 ncpu = CPUV7_L2CTLR_NPROC(reg); 94 95 mp_ncpus = ncpu; 96 mp_maxid = ncpu - 1; 97 } 98 99 static void 100 aw_common_mp_start_ap(bus_space_handle_t cpucfg, bus_space_handle_t prcm) 101 { 102 int i, j; 103 uint32_t val; 104 105 dcache_wbinv_poc_all(); 106 107 bus_space_write_4(fdtbus_bs_tag, cpucfg, CPUCFG_P_REG0, 108 pmap_kextract((vm_offset_t)mpentry)); 109 110 /* 111 * Assert nCOREPORESET low and set L1RSTDISABLE low. 112 * Ensure DBGPWRDUP is set to LOW to prevent any external 113 * debug access to the processor. 114 */ 115 for (i = 1; i < mp_ncpus; i++) 116 bus_space_write_4(fdtbus_bs_tag, cpucfg, CPU_RST_CTL(i), 0); 117 118 /* Set L1RSTDISABLE low */ 119 val = bus_space_read_4(fdtbus_bs_tag, cpucfg, CPUCFG_GENCTL); 120 for (i = 1; i < mp_ncpus; i++) 121 val &= ~(1 << i); 122 bus_space_write_4(fdtbus_bs_tag, cpucfg, CPUCFG_GENCTL, val); 123 124 /* Set DBGPWRDUP low */ 125 val = bus_space_read_4(fdtbus_bs_tag, cpucfg, CPUCFG_DBGCTL1); 126 for (i = 1; i < mp_ncpus; i++) 127 val &= ~(1 << i); 128 bus_space_write_4(fdtbus_bs_tag, cpucfg, CPUCFG_DBGCTL1, val); 129 130 /* Release power clamp */ 131 for (i = 1; i < mp_ncpus; i++) 132 for (j = 0; j <= CPU_PWR_CLAMP_STEPS; j++) { 133 if (prcm) { 134 bus_space_write_4(fdtbus_bs_tag, prcm, 135 CPU_PWR_CLAMP(i), 0xff >> j); 136 } else { 137 bus_space_write_4(fdtbus_bs_tag, 138 cpucfg, A20_CPU1_PWR_CLAMP, 0xff >> j); 139 } 140 } 141 DELAY(10000); 142 143 /* Clear power-off gating */ 144 if (prcm) { 145 val = bus_space_read_4(fdtbus_bs_tag, prcm, CPU_PWROFF); 146 for (i = 0; i < mp_ncpus; i++) 147 val &= ~(1 << i); 148 bus_space_write_4(fdtbus_bs_tag, prcm, CPU_PWROFF, val); 149 } else { 150 val = bus_space_read_4(fdtbus_bs_tag, 151 cpucfg, A20_CPU1_PWROFF_REG); 152 val &= ~(1 << 0); 153 bus_space_write_4(fdtbus_bs_tag, cpucfg, 154 A20_CPU1_PWROFF_REG, val); 155 } 156 DELAY(1000); 157 158 /* De-assert cpu core reset */ 159 for (i = 1; i < mp_ncpus; i++) 160 bus_space_write_4(fdtbus_bs_tag, cpucfg, CPU_RST_CTL(i), 161 CPU_RESET | CPU_CORE_RESET); 162 163 /* Assert DBGPWRDUP signal */ 164 val = bus_space_read_4(fdtbus_bs_tag, cpucfg, CPUCFG_DBGCTL1); 165 for (i = 1; i < mp_ncpus; i++) 166 val |= (1 << i); 167 bus_space_write_4(fdtbus_bs_tag, cpucfg, CPUCFG_DBGCTL1, val); 168 169 armv7_sev(); 170 bus_space_unmap(fdtbus_bs_tag, cpucfg, CPUCFG_SIZE); 171 } 172 173 void 174 a20_mp_start_ap(platform_t plat) 175 { 176 bus_space_handle_t cpucfg; 177 178 if (bus_space_map(fdtbus_bs_tag, A20_CPUCFG_BASE, CPUCFG_SIZE, 179 0, &cpucfg) != 0) 180 panic("Couldn't map the CPUCFG\n"); 181 182 aw_common_mp_start_ap(cpucfg, 0); 183 armv7_sev(); 184 bus_space_unmap(fdtbus_bs_tag, cpucfg, CPUCFG_SIZE); 185 } 186 187 void 188 a31_mp_start_ap(platform_t plat) 189 { 190 bus_space_handle_t cpucfg; 191 bus_space_handle_t prcm; 192 193 if (bus_space_map(fdtbus_bs_tag, CPUCFG_BASE, CPUCFG_SIZE, 194 0, &cpucfg) != 0) 195 panic("Couldn't map the CPUCFG\n"); 196 if (bus_space_map(fdtbus_bs_tag, PRCM_BASE, PRCM_SIZE, 0, 197 &prcm) != 0) 198 panic("Couldn't map the PRCM\n"); 199 200 aw_common_mp_start_ap(cpucfg, prcm); 201 armv7_sev(); 202 bus_space_unmap(fdtbus_bs_tag, cpucfg, CPUCFG_SIZE); 203 bus_space_unmap(fdtbus_bs_tag, prcm, PRCM_SIZE); 204 } 205