1 /*- 2 * Copyright (c) 2013 Alexander Fedorov <alexander.fedorov@rtlservice.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef _AW_MMC_H_ 30 #define _AW_MMC_H_ 31 32 #define AW_MMC_GCTL 0x00 /* Control Register */ 33 #define AW_MMC_CKCR 0x04 /* Clock Control Register */ 34 #define AW_MMC_TMOR 0x08 /* Timeout Register */ 35 #define AW_MMC_BWDR 0x0C /* Bus Width Register */ 36 #define AW_MMC_BKSR 0x10 /* Block Size Register */ 37 #define AW_MMC_BYCR 0x14 /* Byte Count Register */ 38 #define AW_MMC_CMDR 0x18 /* Command Register */ 39 #define AW_MMC_CAGR 0x1C /* Argument Register */ 40 #define AW_MMC_RESP0 0x20 /* Response Register 0 */ 41 #define AW_MMC_RESP1 0x24 /* Response Register 1 */ 42 #define AW_MMC_RESP2 0x28 /* Response Register 2 */ 43 #define AW_MMC_RESP3 0x2C /* Response Register 3 */ 44 #define AW_MMC_IMKR 0x30 /* Interrupt Mask Register */ 45 #define AW_MMC_MISR 0x34 /* Masked Interrupt Status Register */ 46 #define AW_MMC_RISR 0x38 /* Raw Interrupt Status Register */ 47 #define AW_MMC_STAR 0x3C /* Status Register */ 48 #define AW_MMC_FWLR 0x40 /* FIFO Threshold Watermark Register */ 49 #define AW_MMC_FUNS 0x44 /* Function Select Register */ 50 #define AW_MMC_HWRST 0x78 /* Hardware reset (not documented) */ 51 #define AW_MMC_DMAC 0x80 /* IDMAC Control Register */ 52 #define AW_MMC_DLBA 0x84 /* IDMAC Desc List Base Address Reg */ 53 #define AW_MMC_IDST 0x88 /* IDMAC Status Register */ 54 #define AW_MMC_IDIE 0x8C /* IDMAC Interrupt Enable Register */ 55 #define AW_MMC_FIFO 0x100 /* FIFO Access Address (A10/A20) */ 56 #define A31_MMC_FIFO 0x200 /* FIFO Access Address (A31) */ 57 58 /* AW_MMC_GCTL */ 59 #define AW_MMC_CTRL_SOFT_RST (1U << 0) 60 #define AW_MMC_CTRL_FIFO_RST (1U << 1) 61 #define AW_MMC_CTRL_DMA_RST (1U << 2) 62 #define AW_MMC_CTRL_INT_ENB (1U << 4) 63 #define AW_MMC_CTRL_DMA_ENB (1U << 5) 64 #define AW_MMC_CTRL_CD_DBC_ENB (1U << 8) 65 #define AW_MMC_CTRL_DDR_MOD_SEL (1U << 10) 66 #define AW_MMC_CTRL_FIFO_AC_MOD (1U << 31) 67 #define AW_MMC_RESET \ 68 (AW_MMC_CTRL_SOFT_RST | AW_MMC_CTRL_FIFO_RST | AW_MMC_CTRL_DMA_RST) 69 70 /* AW_MMC_CKCR */ 71 #define AW_MMC_CKCR_CCLK_ENB (1U << 16) 72 #define AW_MMC_CKCR_CCLK_CTRL (1U << 17) 73 #define AW_MMC_CKCR_CCLK_DIV 0xff 74 75 /* AW_MMC_TMOR */ 76 #define AW_MMC_TMOR_RTO_LMT_SHIFT(x) x /* Response timeout limit */ 77 #define AW_MMC_TMOR_RTO_LMT_MASK 0xff 78 #define AW_MMC_TMOR_DTO_LMT_SHIFT(x) (x << 8) /* Data timeout limit */ 79 #define AW_MMC_TMOR_DTO_LMT_MASK 0xffffff 80 81 /* AW_MMC_BWDR */ 82 #define AW_MMC_BWDR1 0 83 #define AW_MMC_BWDR4 1 84 #define AW_MMC_BWDR8 2 85 86 /* AW_MMC_CMDR */ 87 #define AW_MMC_CMDR_RESP_RCV (1U << 6) 88 #define AW_MMC_CMDR_LONG_RESP (1U << 7) 89 #define AW_MMC_CMDR_CHK_RESP_CRC (1U << 8) 90 #define AW_MMC_CMDR_DATA_TRANS (1U << 9) 91 #define AW_MMC_CMDR_DIR_WRITE (1U << 10) 92 #define AW_MMC_CMDR_TRANS_MODE_STREAM (1U << 11) 93 #define AW_MMC_CMDR_STOP_CMD_FLAG (1U << 12) 94 #define AW_MMC_CMDR_WAIT_PRE_OVER (1U << 13) 95 #define AW_MMC_CMDR_STOP_ABT_CMD (1U << 14) 96 #define AW_MMC_CMDR_SEND_INIT_SEQ (1U << 15) 97 #define AW_MMC_CMDR_PRG_CLK (1U << 21) 98 #define AW_MMC_CMDR_RD_CEDATA_DEV (1U << 22) 99 #define AW_MMC_CMDR_CCS_EXP (1U << 23) 100 #define AW_MMC_CMDR_BOOT_MOD_SHIFT 24 101 #define AW_MMC_CMDR_BOOT_MOD_NORMAL 0 102 #define AW_MMC_CMDR_BOOT_MOD_MANDATORY 1 103 #define AW_MMC_CMDR_BOOT_MOD_ALT 2 104 #define AW_MMC_CMDR_EXP_BOOT_ACK (1U << 26) 105 #define AW_MMC_CMDR_BOOT_ABT (1U << 27) 106 #define AW_MMC_CMDR_VOL_SW (1U << 28) 107 #define AW_MMC_CMDR_LOAD (1U << 31) 108 109 /* AW_MMC_IMKR and AW_MMC_RISR */ 110 #define AW_MMC_INT_RESP_ERR (1U << 1) 111 #define AW_MMC_INT_CMD_DONE (1U << 2) 112 #define AW_MMC_INT_DATA_OVER (1U << 3) 113 #define AW_MMC_INT_TX_DATA_REQ (1U << 4) 114 #define AW_MMC_INT_RX_DATA_REQ (1U << 5) 115 #define AW_MMC_INT_RESP_CRC_ERR (1U << 6) 116 #define AW_MMC_INT_DATA_CRC_ERR (1U << 7) 117 #define AW_MMC_INT_RESP_TIMEOUT (1U << 8) 118 #define AW_MMC_INT_BOOT_ACK_RECV (1U << 8) 119 #define AW_MMC_INT_DATA_TIMEOUT (1U << 9) 120 #define AW_MMC_INT_BOOT_START (1U << 9) 121 #define AW_MMC_INT_DATA_STARVE (1U << 10) 122 #define AW_MMC_INT_VOL_CHG_DONE (1U << 10) 123 #define AW_MMC_INT_FIFO_RUN_ERR (1U << 11) 124 #define AW_MMC_INT_CMD_BUSY (1U << 12) 125 #define AW_MMC_INT_DATA_START_ERR (1U << 13) 126 #define AW_MMC_INT_AUTO_STOP_DONE (1U << 14) 127 #define AW_MMC_INT_DATA_END_BIT_ERR (1U << 15) 128 #define AW_MMC_INT_SDIO (1U << 16) 129 #define AW_MMC_INT_CARD_INSERT (1U << 30) 130 #define AW_MMC_INT_CARD_REMOVE (1U << 31) 131 #define AW_MMC_INT_ERR_BIT \ 132 (AW_MMC_INT_RESP_ERR | AW_MMC_INT_RESP_CRC_ERR | \ 133 AW_MMC_INT_DATA_CRC_ERR | AW_MMC_INT_RESP_TIMEOUT | \ 134 AW_MMC_INT_FIFO_RUN_ERR | AW_MMC_INT_CMD_BUSY | \ 135 AW_MMC_INT_DATA_START_ERR | AW_MMC_INT_DATA_END_BIT_ERR) 136 137 /* AW_MMC_STAR */ 138 #define AW_MMC_STAR_FIFO_RX_LEVEL (1U << 0) 139 #define AW_MMC_STAR_FIFO_TX_LEVEL (1U << 1) 140 #define AW_MMC_STAR_FIFO_EMPTY (1U << 2) 141 #define AW_MMC_STAR_FIFO_FULL (1U << 3) 142 #define AW_MMC_STAR_CARD_PRESENT (1U << 8) 143 #define AW_MMC_STAR_CARD_BUSY (1U << 9) 144 #define AW_MMC_STAR_FSM_BUSY (1U << 10) 145 #define AW_MMC_STAR_DMA_REQ (1U << 31) 146 147 /* AW_MMC_FUNS */ 148 #define AW_MMC_CE_ATA_ON (0xceaaU << 16) 149 #define AW_MMC_SEND_IRQ_RESP (1U << 0) 150 #define AW_MMC_SDIO_RD_WAIT (1U << 1) 151 #define AW_MMC_ABT_RD_DATA (1U << 2) 152 #define AW_MMC_SEND_CC_SD (1U << 8) 153 #define AW_MMC_SEND_AUTOSTOP_CC_SD (1U << 9) 154 #define AW_MMC_CE_ATA_DEV_INT_ENB (1U << 10) 155 156 /* IDMA CONTROLLER BUS MOD BIT FIELD */ 157 #define AW_MMC_DMAC_IDMAC_SOFT_RST (1U << 0) 158 #define AW_MMC_DMAC_IDMAC_FIX_BURST (1U << 1) 159 #define AW_MMC_DMAC_IDMAC_IDMA_ON (1U << 7) 160 #define AW_MMC_DMAC_IDMAC_REFETCH_DES (1U << 31) 161 162 /* AW_MMC_IDST */ 163 #define AW_MMC_IDST_TX_INT (1U << 0) 164 #define AW_MMC_IDST_RX_INT (1U << 1) 165 #define AW_MMC_IDST_FATAL_BERR_INT (1U << 2) 166 #define AW_MMC_IDST_DES_UNAVL_INT (1U << 4) 167 #define AW_MMC_IDST_ERR_FLAG_SUM (1U << 5) 168 #define AW_MMC_IDST_NOR_INT_SUM (1U << 8) 169 #define AW_MMC_IDST_ABN_INT_SUM (1U << 9) 170 #define AW_MMC_IDST_HOST_ABT_INTX (1U << 10) 171 #define AW_MMC_IDST_HOST_ABT_INRX (1U << 10) 172 #define AW_MMC_IDST_IDLE (0U << 13) 173 #define AW_MMC_IDST_SUSPEND (1U << 13) 174 #define AW_MMC_IDST_DESC_RD (2U << 13) 175 #define AW_MMC_IDST_DESC_CHECK (3U << 13) 176 #define AW_MMC_IDST_RD_REQ_WAIT (4U << 13) 177 #define AW_MMC_IDST_WR_REQ_WAIT (5U << 13) 178 #define AW_MMC_IDST_RD (6U << 13) 179 #define AW_MMC_IDST_WR (7U << 13) 180 #define AW_MMC_IDST_DESC_CLOSE (8U << 13) 181 #define AW_MMC_IDST_ERROR \ 182 (AW_MMC_IDST_FATAL_BERR_INT | AW_MMC_IDST_ERR_FLAG_SUM | \ 183 AW_MMC_IDST_DES_UNAVL_INT | AW_MMC_IDST_ABN_INT_SUM) 184 #define AW_MMC_IDST_COMPLETE \ 185 (AW_MMC_IDST_TX_INT | AW_MMC_IDST_RX_INT) 186 187 /* The DMA descriptor table. */ 188 struct aw_mmc_dma_desc { 189 uint32_t config; 190 #define AW_MMC_DMA_CONFIG_DIC (1U << 1) /* Disable Interrupt Completion */ 191 #define AW_MMC_DMA_CONFIG_LD (1U << 2) /* Last DES */ 192 #define AW_MMC_DMA_CONFIG_FD (1U << 3) /* First DES */ 193 #define AW_MMC_DMA_CONFIG_CH (1U << 4) /* CHAIN MOD */ 194 #define AW_MMC_DMA_CONFIG_ER (1U << 5) /* End of Ring (undocumented register) */ 195 #define AW_MMC_DMA_CONFIG_CES (1U << 30) /* Card Error Summary */ 196 #define AW_MMC_DMA_CONFIG_OWN (1U << 31) /* DES Own Flag */ 197 uint32_t buf_size; 198 uint32_t buf_addr; 199 uint32_t next; 200 }; 201 202 #define AW_MMC_DMA_ALIGN 4 203 204 #endif /* _AW_MMC_H_ */ 205