1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org> 5 * Copyright (c) 2013 Alexander Fedorov 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/kernel.h> 37 #include <sys/lock.h> 38 #include <sys/malloc.h> 39 #include <sys/module.h> 40 #include <sys/mutex.h> 41 #include <sys/resource.h> 42 #include <sys/rman.h> 43 #include <sys/sysctl.h> 44 #include <sys/queue.h> 45 #include <sys/taskqueue.h> 46 47 #include <machine/bus.h> 48 49 #include <dev/ofw/ofw_bus.h> 50 #include <dev/ofw/ofw_bus_subr.h> 51 52 #include <dev/mmc/bridge.h> 53 #include <dev/mmc/mmcbrvar.h> 54 #include <dev/mmc/mmc_fdt_helpers.h> 55 56 #include <arm/allwinner/aw_mmc.h> 57 #include <dev/extres/clk/clk.h> 58 #include <dev/extres/hwreset/hwreset.h> 59 #include <dev/extres/regulator/regulator.h> 60 61 #include "opt_mmccam.h" 62 63 #ifdef MMCCAM 64 #include <cam/cam.h> 65 #include <cam/cam_ccb.h> 66 #include <cam/cam_debug.h> 67 #include <cam/cam_sim.h> 68 #include <cam/cam_xpt_sim.h> 69 #include <cam/mmc/mmc_sim.h> 70 71 #include "mmc_sim_if.h" 72 #endif 73 74 #define AW_MMC_MEMRES 0 75 #define AW_MMC_IRQRES 1 76 #define AW_MMC_RESSZ 2 77 #define AW_MMC_DMA_SEGS (PAGE_SIZE / sizeof(struct aw_mmc_dma_desc)) 78 #define AW_MMC_DMA_DESC_SIZE (sizeof(struct aw_mmc_dma_desc) * AW_MMC_DMA_SEGS) 79 #define AW_MMC_DMA_FTRGLEVEL 0x20070008 80 81 #define AW_MMC_RESET_RETRY 1000 82 83 #define CARD_ID_FREQUENCY 400000 84 85 struct aw_mmc_conf { 86 uint32_t dma_xferlen; 87 bool mask_data0; 88 bool can_calibrate; 89 bool new_timing; 90 }; 91 92 static const struct aw_mmc_conf a10_mmc_conf = { 93 .dma_xferlen = 0x2000, 94 }; 95 96 static const struct aw_mmc_conf a13_mmc_conf = { 97 .dma_xferlen = 0x10000, 98 }; 99 100 static const struct aw_mmc_conf a64_mmc_conf = { 101 .dma_xferlen = 0x10000, 102 .mask_data0 = true, 103 .can_calibrate = true, 104 .new_timing = true, 105 }; 106 107 static const struct aw_mmc_conf a64_emmc_conf = { 108 .dma_xferlen = 0x2000, 109 .can_calibrate = true, 110 }; 111 112 static struct ofw_compat_data compat_data[] = { 113 {"allwinner,sun4i-a10-mmc", (uintptr_t)&a10_mmc_conf}, 114 {"allwinner,sun5i-a13-mmc", (uintptr_t)&a13_mmc_conf}, 115 {"allwinner,sun7i-a20-mmc", (uintptr_t)&a13_mmc_conf}, 116 {"allwinner,sun50i-a64-mmc", (uintptr_t)&a64_mmc_conf}, 117 {"allwinner,sun50i-a64-emmc", (uintptr_t)&a64_emmc_conf}, 118 {NULL, 0} 119 }; 120 121 struct aw_mmc_softc { 122 device_t aw_dev; 123 clk_t aw_clk_ahb; 124 clk_t aw_clk_mmc; 125 hwreset_t aw_rst_ahb; 126 int aw_bus_busy; 127 int aw_resid; 128 int aw_timeout; 129 struct callout aw_timeoutc; 130 struct mmc_host aw_host; 131 struct mmc_fdt_helper mmc_helper; 132 #ifdef MMCCAM 133 union ccb * ccb; 134 struct mmc_sim mmc_sim; 135 #else 136 struct mmc_request * aw_req; 137 #endif 138 struct mtx aw_mtx; 139 struct resource * aw_res[AW_MMC_RESSZ]; 140 struct aw_mmc_conf * aw_mmc_conf; 141 uint32_t aw_intr; 142 uint32_t aw_intr_wait; 143 void * aw_intrhand; 144 unsigned int aw_clock; 145 device_t child; 146 147 /* Fields required for DMA access. */ 148 bus_addr_t aw_dma_desc_phys; 149 bus_dmamap_t aw_dma_map; 150 bus_dma_tag_t aw_dma_tag; 151 void * aw_dma_desc; 152 bus_dmamap_t aw_dma_buf_map; 153 bus_dma_tag_t aw_dma_buf_tag; 154 int aw_dma_map_err; 155 }; 156 157 static struct resource_spec aw_mmc_res_spec[] = { 158 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 159 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 160 { -1, 0, 0 } 161 }; 162 163 static int aw_mmc_probe(device_t); 164 static int aw_mmc_attach(device_t); 165 static int aw_mmc_detach(device_t); 166 static int aw_mmc_setup_dma(struct aw_mmc_softc *); 167 static void aw_mmc_teardown_dma(struct aw_mmc_softc *sc); 168 static int aw_mmc_reset(struct aw_mmc_softc *); 169 static int aw_mmc_init(struct aw_mmc_softc *); 170 static void aw_mmc_intr(void *); 171 static int aw_mmc_update_clock(struct aw_mmc_softc *, uint32_t); 172 static void aw_mmc_helper_cd_handler(device_t, bool); 173 174 static void aw_mmc_print_error(uint32_t); 175 static int aw_mmc_update_ios(device_t, device_t); 176 static int aw_mmc_request(device_t, device_t, struct mmc_request *); 177 178 #ifndef MMCCAM 179 static int aw_mmc_get_ro(device_t, device_t); 180 static int aw_mmc_acquire_host(device_t, device_t); 181 static int aw_mmc_release_host(device_t, device_t); 182 #endif 183 184 #define AW_MMC_LOCK(_sc) mtx_lock(&(_sc)->aw_mtx) 185 #define AW_MMC_UNLOCK(_sc) mtx_unlock(&(_sc)->aw_mtx) 186 #define AW_MMC_READ_4(_sc, _reg) \ 187 bus_read_4((_sc)->aw_res[AW_MMC_MEMRES], _reg) 188 #define AW_MMC_WRITE_4(_sc, _reg, _value) \ 189 bus_write_4((_sc)->aw_res[AW_MMC_MEMRES], _reg, _value) 190 191 SYSCTL_NODE(_hw, OID_AUTO, aw_mmc, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 192 "aw_mmc driver"); 193 194 static int aw_mmc_debug = 0; 195 SYSCTL_INT(_hw_aw_mmc, OID_AUTO, debug, CTLFLAG_RWTUN, &aw_mmc_debug, 0, 196 "Debug level bit0=card changes bit1=ios changes, bit2=interrupts, bit3=commands"); 197 #define AW_MMC_DEBUG_CARD 0x1 198 #define AW_MMC_DEBUG_IOS 0x2 199 #define AW_MMC_DEBUG_INT 0x4 200 #define AW_MMC_DEBUG_CMD 0x8 201 202 #ifdef MMCCAM 203 static int 204 aw_mmc_get_tran_settings(device_t dev, struct ccb_trans_settings_mmc *cts) 205 { 206 struct aw_mmc_softc *sc; 207 208 sc = device_get_softc(dev); 209 210 cts->host_ocr = sc->aw_host.host_ocr; 211 cts->host_f_min = sc->aw_host.f_min; 212 cts->host_f_max = sc->aw_host.f_max; 213 cts->host_caps = sc->aw_host.caps; 214 cts->host_max_data = (sc->aw_mmc_conf->dma_xferlen * 215 AW_MMC_DMA_SEGS) / MMC_SECTOR_SIZE; 216 memcpy(&cts->ios, &sc->aw_host.ios, sizeof(struct mmc_ios)); 217 218 return (0); 219 } 220 221 static int 222 aw_mmc_set_tran_settings(device_t dev, struct ccb_trans_settings_mmc *cts) 223 { 224 struct aw_mmc_softc *sc; 225 struct mmc_ios *ios; 226 struct mmc_ios *new_ios; 227 228 sc = device_get_softc(dev); 229 ios = &sc->aw_host.ios; 230 new_ios = &cts->ios; 231 232 /* Update only requested fields */ 233 if (cts->ios_valid & MMC_CLK) { 234 ios->clock = new_ios->clock; 235 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS)) 236 device_printf(sc->aw_dev, "Clock => %d\n", ios->clock); 237 } 238 if (cts->ios_valid & MMC_VDD) { 239 ios->vdd = new_ios->vdd; 240 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS)) 241 device_printf(sc->aw_dev, "VDD => %d\n", ios->vdd); 242 } 243 if (cts->ios_valid & MMC_CS) { 244 ios->chip_select = new_ios->chip_select; 245 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS)) 246 device_printf(sc->aw_dev, "CS => %d\n", ios->chip_select); 247 } 248 if (cts->ios_valid & MMC_BW) { 249 ios->bus_width = new_ios->bus_width; 250 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS)) 251 device_printf(sc->aw_dev, "Bus width => %d\n", ios->bus_width); 252 } 253 if (cts->ios_valid & MMC_PM) { 254 ios->power_mode = new_ios->power_mode; 255 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS)) 256 device_printf(sc->aw_dev, "Power mode => %d\n", ios->power_mode); 257 } 258 if (cts->ios_valid & MMC_BT) { 259 ios->timing = new_ios->timing; 260 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS)) 261 device_printf(sc->aw_dev, "Timing => %d\n", ios->timing); 262 } 263 if (cts->ios_valid & MMC_BM) { 264 ios->bus_mode = new_ios->bus_mode; 265 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS)) 266 device_printf(sc->aw_dev, "Bus mode => %d\n", ios->bus_mode); 267 } 268 269 return (aw_mmc_update_ios(sc->aw_dev, NULL)); 270 } 271 272 static int 273 aw_mmc_cam_request(device_t dev, union ccb *ccb) 274 { 275 struct aw_mmc_softc *sc; 276 struct ccb_mmcio *mmcio; 277 278 sc = device_get_softc(dev); 279 mmcio = &ccb->mmcio; 280 281 AW_MMC_LOCK(sc); 282 283 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CMD)) { 284 device_printf(sc->aw_dev, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 285 mmcio->cmd.opcode, mmcio->cmd.arg, mmcio->cmd.flags, 286 mmcio->cmd.data != NULL ? (unsigned int) mmcio->cmd.data->len : 0, 287 mmcio->cmd.data != NULL ? mmcio->cmd.data->flags: 0); 288 } 289 if (mmcio->cmd.data != NULL) { 290 if (mmcio->cmd.data->len == 0 || mmcio->cmd.data->flags == 0) 291 panic("data->len = %d, data->flags = %d -- something is b0rked", 292 (int)mmcio->cmd.data->len, mmcio->cmd.data->flags); 293 } 294 if (sc->ccb != NULL) { 295 device_printf(sc->aw_dev, "Controller still has an active command\n"); 296 return (EBUSY); 297 } 298 sc->ccb = ccb; 299 /* aw_mmc_request locks again */ 300 AW_MMC_UNLOCK(sc); 301 aw_mmc_request(sc->aw_dev, NULL, NULL); 302 303 return (0); 304 } 305 #endif /* MMCCAM */ 306 307 static void 308 aw_mmc_helper_cd_handler(device_t dev, bool present) 309 { 310 struct aw_mmc_softc *sc; 311 312 sc = device_get_softc(dev); 313 #ifdef MMCCAM 314 mmc_cam_sim_discover(&sc->mmc_sim); 315 #else 316 AW_MMC_LOCK(sc); 317 if (present) { 318 if (sc->child == NULL) { 319 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CARD)) 320 device_printf(sc->aw_dev, "Card inserted\n"); 321 322 sc->child = device_add_child(sc->aw_dev, "mmc", -1); 323 AW_MMC_UNLOCK(sc); 324 if (sc->child) { 325 device_set_ivars(sc->child, sc); 326 (void)device_probe_and_attach(sc->child); 327 } 328 } else 329 AW_MMC_UNLOCK(sc); 330 } else { 331 /* Card isn't present, detach if necessary */ 332 if (sc->child != NULL) { 333 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CARD)) 334 device_printf(sc->aw_dev, "Card removed\n"); 335 336 AW_MMC_UNLOCK(sc); 337 device_delete_child(sc->aw_dev, sc->child); 338 sc->child = NULL; 339 } else 340 AW_MMC_UNLOCK(sc); 341 } 342 #endif /* MMCCAM */ 343 } 344 345 static int 346 aw_mmc_probe(device_t dev) 347 { 348 349 if (!ofw_bus_status_okay(dev)) 350 return (ENXIO); 351 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 352 return (ENXIO); 353 354 device_set_desc(dev, "Allwinner Integrated MMC/SD controller"); 355 356 return (BUS_PROBE_DEFAULT); 357 } 358 359 static int 360 aw_mmc_attach(device_t dev) 361 { 362 struct aw_mmc_softc *sc; 363 struct sysctl_ctx_list *ctx; 364 struct sysctl_oid_list *tree; 365 int error; 366 367 sc = device_get_softc(dev); 368 sc->aw_dev = dev; 369 370 sc->aw_mmc_conf = (struct aw_mmc_conf *)ofw_bus_search_compatible(dev, compat_data)->ocd_data; 371 372 #ifndef MMCCAM 373 sc->aw_req = NULL; 374 #endif 375 if (bus_alloc_resources(dev, aw_mmc_res_spec, sc->aw_res) != 0) { 376 device_printf(dev, "cannot allocate device resources\n"); 377 return (ENXIO); 378 } 379 if (bus_setup_intr(dev, sc->aw_res[AW_MMC_IRQRES], 380 INTR_TYPE_NET | INTR_MPSAFE, NULL, aw_mmc_intr, sc, 381 &sc->aw_intrhand)) { 382 bus_release_resources(dev, aw_mmc_res_spec, sc->aw_res); 383 device_printf(dev, "cannot setup interrupt handler\n"); 384 return (ENXIO); 385 } 386 mtx_init(&sc->aw_mtx, device_get_nameunit(sc->aw_dev), "aw_mmc", 387 MTX_DEF); 388 callout_init_mtx(&sc->aw_timeoutc, &sc->aw_mtx, 0); 389 390 /* De-assert reset */ 391 if (hwreset_get_by_ofw_name(dev, 0, "ahb", &sc->aw_rst_ahb) == 0) { 392 error = hwreset_deassert(sc->aw_rst_ahb); 393 if (error != 0) { 394 device_printf(dev, "cannot de-assert reset\n"); 395 goto fail; 396 } 397 } 398 399 /* Activate the module clock. */ 400 error = clk_get_by_ofw_name(dev, 0, "ahb", &sc->aw_clk_ahb); 401 if (error != 0) { 402 device_printf(dev, "cannot get ahb clock\n"); 403 goto fail; 404 } 405 error = clk_enable(sc->aw_clk_ahb); 406 if (error != 0) { 407 device_printf(dev, "cannot enable ahb clock\n"); 408 goto fail; 409 } 410 error = clk_get_by_ofw_name(dev, 0, "mmc", &sc->aw_clk_mmc); 411 if (error != 0) { 412 device_printf(dev, "cannot get mmc clock\n"); 413 goto fail; 414 } 415 error = clk_set_freq(sc->aw_clk_mmc, CARD_ID_FREQUENCY, 416 CLK_SET_ROUND_DOWN); 417 if (error != 0) { 418 device_printf(dev, "cannot init mmc clock\n"); 419 goto fail; 420 } 421 error = clk_enable(sc->aw_clk_mmc); 422 if (error != 0) { 423 device_printf(dev, "cannot enable mmc clock\n"); 424 goto fail; 425 } 426 427 sc->aw_timeout = 10; 428 ctx = device_get_sysctl_ctx(dev); 429 tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 430 SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "req_timeout", CTLFLAG_RW, 431 &sc->aw_timeout, 0, "Request timeout in seconds"); 432 433 /* Soft Reset controller. */ 434 if (aw_mmc_reset(sc) != 0) { 435 device_printf(dev, "cannot reset the controller\n"); 436 goto fail; 437 } 438 439 if (aw_mmc_setup_dma(sc) != 0) { 440 device_printf(sc->aw_dev, "Couldn't setup DMA!\n"); 441 goto fail; 442 } 443 444 /* Set some defaults for freq and supported mode */ 445 sc->aw_host.f_min = 400000; 446 sc->aw_host.f_max = 52000000; 447 sc->aw_host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340; 448 sc->aw_host.caps |= MMC_CAP_HSPEED | MMC_CAP_SIGNALING_330; 449 mmc_fdt_parse(dev, 0, &sc->mmc_helper, &sc->aw_host); 450 mmc_fdt_gpio_setup(dev, 0, &sc->mmc_helper, aw_mmc_helper_cd_handler); 451 452 #ifdef MMCCAM 453 sc->ccb = NULL; 454 455 if (mmc_cam_sim_alloc(dev, "aw_mmc", &sc->mmc_sim) != 0) { 456 device_printf(dev, "cannot alloc cam sim\n"); 457 goto fail; 458 } 459 #endif /* MMCCAM */ 460 461 return (0); 462 463 fail: 464 callout_drain(&sc->aw_timeoutc); 465 mtx_destroy(&sc->aw_mtx); 466 bus_teardown_intr(dev, sc->aw_res[AW_MMC_IRQRES], sc->aw_intrhand); 467 bus_release_resources(dev, aw_mmc_res_spec, sc->aw_res); 468 469 return (ENXIO); 470 } 471 472 static int 473 aw_mmc_detach(device_t dev) 474 { 475 struct aw_mmc_softc *sc; 476 device_t d; 477 478 sc = device_get_softc(dev); 479 480 clk_disable(sc->aw_clk_mmc); 481 clk_disable(sc->aw_clk_ahb); 482 hwreset_assert(sc->aw_rst_ahb); 483 484 mmc_fdt_gpio_teardown(&sc->mmc_helper); 485 486 callout_drain(&sc->aw_timeoutc); 487 488 AW_MMC_LOCK(sc); 489 d = sc->child; 490 sc->child = NULL; 491 AW_MMC_UNLOCK(sc); 492 if (d != NULL) 493 device_delete_child(sc->aw_dev, d); 494 495 aw_mmc_teardown_dma(sc); 496 497 mtx_destroy(&sc->aw_mtx); 498 499 bus_teardown_intr(dev, sc->aw_res[AW_MMC_IRQRES], sc->aw_intrhand); 500 bus_release_resources(dev, aw_mmc_res_spec, sc->aw_res); 501 502 #ifdef MMCCAM 503 mmc_cam_sim_free(&sc->mmc_sim); 504 #endif 505 506 return (0); 507 } 508 509 static void 510 aw_dma_desc_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err) 511 { 512 struct aw_mmc_softc *sc; 513 514 sc = (struct aw_mmc_softc *)arg; 515 if (err) { 516 sc->aw_dma_map_err = err; 517 return; 518 } 519 sc->aw_dma_desc_phys = segs[0].ds_addr; 520 } 521 522 static int 523 aw_mmc_setup_dma(struct aw_mmc_softc *sc) 524 { 525 int error; 526 527 /* Allocate the DMA descriptor memory. */ 528 error = bus_dma_tag_create( 529 bus_get_dma_tag(sc->aw_dev), /* parent */ 530 AW_MMC_DMA_ALIGN, 0, /* align, boundary */ 531 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 532 BUS_SPACE_MAXADDR, /* highaddr */ 533 NULL, NULL, /* filter, filterarg*/ 534 AW_MMC_DMA_DESC_SIZE, 1, /* maxsize, nsegment */ 535 AW_MMC_DMA_DESC_SIZE, /* maxsegsize */ 536 0, /* flags */ 537 NULL, NULL, /* lock, lockarg*/ 538 &sc->aw_dma_tag); 539 if (error) 540 return (error); 541 542 error = bus_dmamem_alloc(sc->aw_dma_tag, &sc->aw_dma_desc, 543 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, 544 &sc->aw_dma_map); 545 if (error) 546 return (error); 547 548 error = bus_dmamap_load(sc->aw_dma_tag, 549 sc->aw_dma_map, 550 sc->aw_dma_desc, AW_MMC_DMA_DESC_SIZE, 551 aw_dma_desc_cb, sc, 0); 552 if (error) 553 return (error); 554 if (sc->aw_dma_map_err) 555 return (sc->aw_dma_map_err); 556 557 /* Create the DMA map for data transfers. */ 558 error = bus_dma_tag_create( 559 bus_get_dma_tag(sc->aw_dev), /* parent */ 560 AW_MMC_DMA_ALIGN, 0, /* align, boundary */ 561 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 562 BUS_SPACE_MAXADDR, /* highaddr */ 563 NULL, NULL, /* filter, filterarg*/ 564 sc->aw_mmc_conf->dma_xferlen * 565 AW_MMC_DMA_SEGS, AW_MMC_DMA_SEGS, /* maxsize, nsegments */ 566 sc->aw_mmc_conf->dma_xferlen, /* maxsegsize */ 567 BUS_DMA_ALLOCNOW, /* flags */ 568 NULL, NULL, /* lock, lockarg*/ 569 &sc->aw_dma_buf_tag); 570 if (error) 571 return (error); 572 error = bus_dmamap_create(sc->aw_dma_buf_tag, 0, 573 &sc->aw_dma_buf_map); 574 if (error) 575 return (error); 576 577 return (0); 578 } 579 580 static void 581 aw_mmc_teardown_dma(struct aw_mmc_softc *sc) 582 { 583 584 bus_dmamap_unload(sc->aw_dma_tag, sc->aw_dma_map); 585 bus_dmamem_free(sc->aw_dma_tag, sc->aw_dma_desc, sc->aw_dma_map); 586 if (bus_dma_tag_destroy(sc->aw_dma_tag) != 0) 587 device_printf(sc->aw_dev, "Cannot destroy the dma tag\n"); 588 589 bus_dmamap_unload(sc->aw_dma_buf_tag, sc->aw_dma_buf_map); 590 bus_dmamap_destroy(sc->aw_dma_buf_tag, sc->aw_dma_buf_map); 591 if (bus_dma_tag_destroy(sc->aw_dma_buf_tag) != 0) 592 device_printf(sc->aw_dev, "Cannot destroy the dma buf tag\n"); 593 } 594 595 static void 596 aw_dma_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err) 597 { 598 int i; 599 struct aw_mmc_dma_desc *dma_desc; 600 struct aw_mmc_softc *sc; 601 602 sc = (struct aw_mmc_softc *)arg; 603 sc->aw_dma_map_err = err; 604 605 if (err) 606 return; 607 608 dma_desc = sc->aw_dma_desc; 609 for (i = 0; i < nsegs; i++) { 610 if (segs[i].ds_len == sc->aw_mmc_conf->dma_xferlen) 611 dma_desc[i].buf_size = 0; /* Size of 0 indicate max len */ 612 else 613 dma_desc[i].buf_size = segs[i].ds_len; 614 dma_desc[i].buf_addr = segs[i].ds_addr; 615 dma_desc[i].config = AW_MMC_DMA_CONFIG_CH | 616 AW_MMC_DMA_CONFIG_OWN | AW_MMC_DMA_CONFIG_DIC; 617 618 dma_desc[i].next = sc->aw_dma_desc_phys + 619 ((i + 1) * sizeof(struct aw_mmc_dma_desc)); 620 } 621 622 dma_desc[0].config |= AW_MMC_DMA_CONFIG_FD; 623 dma_desc[nsegs - 1].config |= AW_MMC_DMA_CONFIG_LD | 624 AW_MMC_DMA_CONFIG_ER; 625 dma_desc[nsegs - 1].config &= ~AW_MMC_DMA_CONFIG_DIC; 626 dma_desc[nsegs - 1].next = 0; 627 } 628 629 static int 630 aw_mmc_prepare_dma(struct aw_mmc_softc *sc) 631 { 632 bus_dmasync_op_t sync_op; 633 int error; 634 struct mmc_command *cmd; 635 uint32_t val; 636 637 #ifdef MMCCAM 638 cmd = &sc->ccb->mmcio.cmd; 639 #else 640 cmd = sc->aw_req->cmd; 641 #endif 642 if (cmd->data->len > (sc->aw_mmc_conf->dma_xferlen * AW_MMC_DMA_SEGS)) 643 return (EFBIG); 644 error = bus_dmamap_load(sc->aw_dma_buf_tag, sc->aw_dma_buf_map, 645 cmd->data->data, cmd->data->len, aw_dma_cb, sc, 0); 646 if (error) 647 return (error); 648 if (sc->aw_dma_map_err) 649 return (sc->aw_dma_map_err); 650 651 if (cmd->data->flags & MMC_DATA_WRITE) 652 sync_op = BUS_DMASYNC_PREWRITE; 653 else 654 sync_op = BUS_DMASYNC_PREREAD; 655 bus_dmamap_sync(sc->aw_dma_buf_tag, sc->aw_dma_buf_map, sync_op); 656 bus_dmamap_sync(sc->aw_dma_tag, sc->aw_dma_map, BUS_DMASYNC_PREWRITE); 657 658 /* Enable DMA */ 659 val = AW_MMC_READ_4(sc, AW_MMC_GCTL); 660 val &= ~AW_MMC_GCTL_FIFO_AC_MOD; 661 val |= AW_MMC_GCTL_DMA_ENB; 662 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val); 663 664 /* Reset DMA */ 665 val |= AW_MMC_GCTL_DMA_RST; 666 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val); 667 668 AW_MMC_WRITE_4(sc, AW_MMC_DMAC, AW_MMC_DMAC_IDMAC_SOFT_RST); 669 AW_MMC_WRITE_4(sc, AW_MMC_DMAC, 670 AW_MMC_DMAC_IDMAC_IDMA_ON | AW_MMC_DMAC_IDMAC_FIX_BURST); 671 672 /* Enable RX or TX DMA interrupt */ 673 val = AW_MMC_READ_4(sc, AW_MMC_IDIE); 674 if (cmd->data->flags & MMC_DATA_WRITE) 675 val |= AW_MMC_IDST_TX_INT; 676 else 677 val |= AW_MMC_IDST_RX_INT; 678 AW_MMC_WRITE_4(sc, AW_MMC_IDIE, val); 679 680 /* Set DMA descritptor list address */ 681 AW_MMC_WRITE_4(sc, AW_MMC_DLBA, sc->aw_dma_desc_phys); 682 683 /* FIFO trigger level */ 684 AW_MMC_WRITE_4(sc, AW_MMC_FWLR, AW_MMC_DMA_FTRGLEVEL); 685 686 return (0); 687 } 688 689 static int 690 aw_mmc_reset(struct aw_mmc_softc *sc) 691 { 692 uint32_t reg; 693 int timeout; 694 695 reg = AW_MMC_READ_4(sc, AW_MMC_GCTL); 696 reg |= AW_MMC_GCTL_RESET; 697 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg); 698 timeout = AW_MMC_RESET_RETRY; 699 while (--timeout > 0) { 700 if ((AW_MMC_READ_4(sc, AW_MMC_GCTL) & AW_MMC_GCTL_RESET) == 0) 701 break; 702 DELAY(100); 703 } 704 if (timeout == 0) 705 return (ETIMEDOUT); 706 707 return (0); 708 } 709 710 static int 711 aw_mmc_init(struct aw_mmc_softc *sc) 712 { 713 uint32_t reg; 714 int ret; 715 716 ret = aw_mmc_reset(sc); 717 if (ret != 0) 718 return (ret); 719 720 /* Set the timeout. */ 721 AW_MMC_WRITE_4(sc, AW_MMC_TMOR, 722 AW_MMC_TMOR_DTO_LMT_SHIFT(AW_MMC_TMOR_DTO_LMT_MASK) | 723 AW_MMC_TMOR_RTO_LMT_SHIFT(AW_MMC_TMOR_RTO_LMT_MASK)); 724 725 /* Unmask interrupts. */ 726 AW_MMC_WRITE_4(sc, AW_MMC_IMKR, 0); 727 728 /* Clear pending interrupts. */ 729 AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff); 730 731 /* Debug register, undocumented */ 732 AW_MMC_WRITE_4(sc, AW_MMC_DBGC, 0xdeb); 733 734 /* Function select register */ 735 AW_MMC_WRITE_4(sc, AW_MMC_FUNS, 0xceaa0000); 736 737 AW_MMC_WRITE_4(sc, AW_MMC_IDST, 0xffffffff); 738 739 /* Enable interrupts and disable AHB access. */ 740 reg = AW_MMC_READ_4(sc, AW_MMC_GCTL); 741 reg |= AW_MMC_GCTL_INT_ENB; 742 reg &= ~AW_MMC_GCTL_FIFO_AC_MOD; 743 reg &= ~AW_MMC_GCTL_WAIT_MEM_ACCESS; 744 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg); 745 746 return (0); 747 } 748 749 static void 750 aw_mmc_req_done(struct aw_mmc_softc *sc) 751 { 752 struct mmc_command *cmd; 753 #ifdef MMCCAM 754 union ccb *ccb; 755 #else 756 struct mmc_request *req; 757 #endif 758 uint32_t val, mask; 759 int retry; 760 761 #ifdef MMCCAM 762 ccb = sc->ccb; 763 cmd = &ccb->mmcio.cmd; 764 #else 765 cmd = sc->aw_req->cmd; 766 #endif 767 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CMD)) { 768 device_printf(sc->aw_dev, "%s: cmd %d err %d\n", __func__, cmd->opcode, cmd->error); 769 } 770 if (cmd->error != MMC_ERR_NONE) { 771 /* Reset the FIFO and DMA engines. */ 772 mask = AW_MMC_GCTL_FIFO_RST | AW_MMC_GCTL_DMA_RST; 773 val = AW_MMC_READ_4(sc, AW_MMC_GCTL); 774 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val | mask); 775 776 retry = AW_MMC_RESET_RETRY; 777 while (--retry > 0) { 778 if ((AW_MMC_READ_4(sc, AW_MMC_GCTL) & 779 AW_MMC_GCTL_RESET) == 0) 780 break; 781 DELAY(100); 782 } 783 if (retry == 0) 784 device_printf(sc->aw_dev, 785 "timeout resetting DMA/FIFO\n"); 786 aw_mmc_update_clock(sc, 1); 787 } 788 789 callout_stop(&sc->aw_timeoutc); 790 sc->aw_intr = 0; 791 sc->aw_resid = 0; 792 sc->aw_dma_map_err = 0; 793 sc->aw_intr_wait = 0; 794 #ifdef MMCCAM 795 sc->ccb = NULL; 796 ccb->ccb_h.status = 797 (ccb->mmcio.cmd.error == 0 ? CAM_REQ_CMP : CAM_REQ_CMP_ERR); 798 xpt_done(ccb); 799 #else 800 req = sc->aw_req; 801 sc->aw_req = NULL; 802 req->done(req); 803 #endif 804 } 805 806 static void 807 aw_mmc_req_ok(struct aw_mmc_softc *sc) 808 { 809 int timeout; 810 struct mmc_command *cmd; 811 uint32_t status; 812 813 timeout = 1000; 814 while (--timeout > 0) { 815 status = AW_MMC_READ_4(sc, AW_MMC_STAR); 816 if ((status & AW_MMC_STAR_CARD_BUSY) == 0) 817 break; 818 DELAY(1000); 819 } 820 #ifdef MMCCAM 821 cmd = &sc->ccb->mmcio.cmd; 822 #else 823 cmd = sc->aw_req->cmd; 824 #endif 825 if (timeout == 0) { 826 cmd->error = MMC_ERR_FAILED; 827 aw_mmc_req_done(sc); 828 return; 829 } 830 if (cmd->flags & MMC_RSP_PRESENT) { 831 if (cmd->flags & MMC_RSP_136) { 832 cmd->resp[0] = AW_MMC_READ_4(sc, AW_MMC_RESP3); 833 cmd->resp[1] = AW_MMC_READ_4(sc, AW_MMC_RESP2); 834 cmd->resp[2] = AW_MMC_READ_4(sc, AW_MMC_RESP1); 835 cmd->resp[3] = AW_MMC_READ_4(sc, AW_MMC_RESP0); 836 } else 837 cmd->resp[0] = AW_MMC_READ_4(sc, AW_MMC_RESP0); 838 } 839 /* All data has been transferred ? */ 840 if (cmd->data != NULL && (sc->aw_resid << 2) < cmd->data->len) 841 cmd->error = MMC_ERR_FAILED; 842 aw_mmc_req_done(sc); 843 } 844 845 static inline void 846 set_mmc_error(struct aw_mmc_softc *sc, int error_code) 847 { 848 #ifdef MMCCAM 849 sc->ccb->mmcio.cmd.error = error_code; 850 #else 851 sc->aw_req->cmd->error = error_code; 852 #endif 853 } 854 855 static void 856 aw_mmc_timeout(void *arg) 857 { 858 struct aw_mmc_softc *sc; 859 860 sc = (struct aw_mmc_softc *)arg; 861 #ifdef MMCCAM 862 if (sc->ccb != NULL) { 863 #else 864 if (sc->aw_req != NULL) { 865 #endif 866 device_printf(sc->aw_dev, "controller timeout\n"); 867 set_mmc_error(sc, MMC_ERR_TIMEOUT); 868 aw_mmc_req_done(sc); 869 } else 870 device_printf(sc->aw_dev, 871 "Spurious timeout - no active request\n"); 872 } 873 874 static void 875 aw_mmc_print_error(uint32_t err) 876 { 877 if(err & AW_MMC_INT_RESP_ERR) 878 printf("AW_MMC_INT_RESP_ERR "); 879 if (err & AW_MMC_INT_RESP_CRC_ERR) 880 printf("AW_MMC_INT_RESP_CRC_ERR "); 881 if (err & AW_MMC_INT_DATA_CRC_ERR) 882 printf("AW_MMC_INT_DATA_CRC_ERR "); 883 if (err & AW_MMC_INT_RESP_TIMEOUT) 884 printf("AW_MMC_INT_RESP_TIMEOUT "); 885 if (err & AW_MMC_INT_FIFO_RUN_ERR) 886 printf("AW_MMC_INT_FIFO_RUN_ERR "); 887 if (err & AW_MMC_INT_CMD_BUSY) 888 printf("AW_MMC_INT_CMD_BUSY "); 889 if (err & AW_MMC_INT_DATA_START_ERR) 890 printf("AW_MMC_INT_DATA_START_ERR "); 891 if (err & AW_MMC_INT_DATA_END_BIT_ERR) 892 printf("AW_MMC_INT_DATA_END_BIT_ERR"); 893 printf("\n"); 894 } 895 896 static void 897 aw_mmc_intr(void *arg) 898 { 899 bus_dmasync_op_t sync_op; 900 struct aw_mmc_softc *sc; 901 struct mmc_data *data; 902 uint32_t idst, imask, rint; 903 904 sc = (struct aw_mmc_softc *)arg; 905 AW_MMC_LOCK(sc); 906 rint = AW_MMC_READ_4(sc, AW_MMC_RISR); 907 idst = AW_MMC_READ_4(sc, AW_MMC_IDST); 908 imask = AW_MMC_READ_4(sc, AW_MMC_IMKR); 909 if (idst == 0 && imask == 0 && rint == 0) { 910 AW_MMC_UNLOCK(sc); 911 return; 912 } 913 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_INT)) { 914 device_printf(sc->aw_dev, "idst: %#x, imask: %#x, rint: %#x\n", 915 idst, imask, rint); 916 } 917 #ifdef MMCCAM 918 if (sc->ccb == NULL) { 919 #else 920 if (sc->aw_req == NULL) { 921 #endif 922 device_printf(sc->aw_dev, 923 "Spurious interrupt - no active request, rint: 0x%08X\n", 924 rint); 925 aw_mmc_print_error(rint); 926 goto end; 927 } 928 if (rint & AW_MMC_INT_ERR_BIT) { 929 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_INT)) { 930 device_printf(sc->aw_dev, "error rint: 0x%08X\n", rint); 931 aw_mmc_print_error(rint); 932 } 933 if (rint & AW_MMC_INT_RESP_TIMEOUT) 934 set_mmc_error(sc, MMC_ERR_TIMEOUT); 935 else 936 set_mmc_error(sc, MMC_ERR_FAILED); 937 aw_mmc_req_done(sc); 938 goto end; 939 } 940 if (idst & AW_MMC_IDST_ERROR) { 941 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_INT)) 942 device_printf(sc->aw_dev, "error idst: 0x%08x\n", idst); 943 set_mmc_error(sc, MMC_ERR_FAILED); 944 aw_mmc_req_done(sc); 945 goto end; 946 } 947 948 sc->aw_intr |= rint; 949 #ifdef MMCCAM 950 data = sc->ccb->mmcio.cmd.data; 951 #else 952 data = sc->aw_req->cmd->data; 953 #endif 954 if (data != NULL && (idst & AW_MMC_IDST_COMPLETE) != 0) { 955 if (data->flags & MMC_DATA_WRITE) 956 sync_op = BUS_DMASYNC_POSTWRITE; 957 else 958 sync_op = BUS_DMASYNC_POSTREAD; 959 bus_dmamap_sync(sc->aw_dma_buf_tag, sc->aw_dma_buf_map, 960 sync_op); 961 bus_dmamap_sync(sc->aw_dma_tag, sc->aw_dma_map, 962 BUS_DMASYNC_POSTWRITE); 963 bus_dmamap_unload(sc->aw_dma_buf_tag, sc->aw_dma_buf_map); 964 sc->aw_resid = data->len >> 2; 965 } 966 if ((sc->aw_intr & sc->aw_intr_wait) == sc->aw_intr_wait) 967 aw_mmc_req_ok(sc); 968 969 end: 970 AW_MMC_WRITE_4(sc, AW_MMC_IDST, idst); 971 AW_MMC_WRITE_4(sc, AW_MMC_RISR, rint); 972 AW_MMC_UNLOCK(sc); 973 } 974 975 static int 976 aw_mmc_request(device_t bus, device_t child, struct mmc_request *req) 977 { 978 int blksz; 979 struct aw_mmc_softc *sc; 980 struct mmc_command *cmd; 981 uint32_t cmdreg, imask; 982 int err; 983 984 sc = device_get_softc(bus); 985 986 AW_MMC_LOCK(sc); 987 #ifdef MMCCAM 988 KASSERT(req == NULL, ("req should be NULL in MMCCAM case!")); 989 /* 990 * For MMCCAM, sc->ccb has been NULL-checked and populated 991 * by aw_mmc_cam_request() already. 992 */ 993 cmd = &sc->ccb->mmcio.cmd; 994 #else 995 if (sc->aw_req) { 996 AW_MMC_UNLOCK(sc); 997 return (EBUSY); 998 } 999 sc->aw_req = req; 1000 cmd = req->cmd; 1001 1002 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CMD)) { 1003 device_printf(sc->aw_dev, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 1004 cmd->opcode, cmd->arg, cmd->flags, 1005 cmd->data != NULL ? (unsigned int)cmd->data->len : 0, 1006 cmd->data != NULL ? cmd->data->flags: 0); 1007 } 1008 #endif 1009 cmdreg = AW_MMC_CMDR_LOAD; 1010 imask = AW_MMC_INT_ERR_BIT; 1011 sc->aw_intr_wait = 0; 1012 sc->aw_intr = 0; 1013 sc->aw_resid = 0; 1014 cmd->error = MMC_ERR_NONE; 1015 1016 if (cmd->opcode == MMC_GO_IDLE_STATE) 1017 cmdreg |= AW_MMC_CMDR_SEND_INIT_SEQ; 1018 1019 if (cmd->flags & MMC_RSP_PRESENT) 1020 cmdreg |= AW_MMC_CMDR_RESP_RCV; 1021 if (cmd->flags & MMC_RSP_136) 1022 cmdreg |= AW_MMC_CMDR_LONG_RESP; 1023 if (cmd->flags & MMC_RSP_CRC) 1024 cmdreg |= AW_MMC_CMDR_CHK_RESP_CRC; 1025 1026 if (cmd->data) { 1027 cmdreg |= AW_MMC_CMDR_DATA_TRANS | AW_MMC_CMDR_WAIT_PRE_OVER; 1028 1029 if (cmd->data->flags & MMC_DATA_MULTI) { 1030 cmdreg |= AW_MMC_CMDR_STOP_CMD_FLAG; 1031 imask |= AW_MMC_INT_AUTO_STOP_DONE; 1032 sc->aw_intr_wait |= AW_MMC_INT_AUTO_STOP_DONE; 1033 } else { 1034 sc->aw_intr_wait |= AW_MMC_INT_DATA_OVER; 1035 imask |= AW_MMC_INT_DATA_OVER; 1036 } 1037 if (cmd->data->flags & MMC_DATA_WRITE) 1038 cmdreg |= AW_MMC_CMDR_DIR_WRITE; 1039 #ifdef MMCCAM 1040 if (cmd->data->flags & MMC_DATA_BLOCK_SIZE) { 1041 AW_MMC_WRITE_4(sc, AW_MMC_BKSR, cmd->data->block_size); 1042 AW_MMC_WRITE_4(sc, AW_MMC_BYCR, cmd->data->len); 1043 } else 1044 #endif 1045 { 1046 blksz = min(cmd->data->len, MMC_SECTOR_SIZE); 1047 AW_MMC_WRITE_4(sc, AW_MMC_BKSR, blksz); 1048 AW_MMC_WRITE_4(sc, AW_MMC_BYCR, cmd->data->len); 1049 } 1050 } else { 1051 imask |= AW_MMC_INT_CMD_DONE; 1052 } 1053 1054 /* Enable the interrupts we are interested in */ 1055 AW_MMC_WRITE_4(sc, AW_MMC_IMKR, imask); 1056 AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff); 1057 1058 /* Enable auto stop if needed */ 1059 AW_MMC_WRITE_4(sc, AW_MMC_A12A, 1060 cmdreg & AW_MMC_CMDR_STOP_CMD_FLAG ? 0 : 0xffff); 1061 1062 /* Write the command argument */ 1063 AW_MMC_WRITE_4(sc, AW_MMC_CAGR, cmd->arg); 1064 1065 /* 1066 * If we don't have data start the request 1067 * if we do prepare the dma request and start the request 1068 */ 1069 if (cmd->data == NULL) { 1070 AW_MMC_WRITE_4(sc, AW_MMC_CMDR, cmdreg | cmd->opcode); 1071 } else { 1072 err = aw_mmc_prepare_dma(sc); 1073 if (err != 0) 1074 device_printf(sc->aw_dev, "prepare_dma failed: %d\n", err); 1075 1076 AW_MMC_WRITE_4(sc, AW_MMC_CMDR, cmdreg | cmd->opcode); 1077 } 1078 1079 callout_reset(&sc->aw_timeoutc, sc->aw_timeout * hz, 1080 aw_mmc_timeout, sc); 1081 AW_MMC_UNLOCK(sc); 1082 1083 return (0); 1084 } 1085 1086 static int 1087 aw_mmc_read_ivar(device_t bus, device_t child, int which, 1088 uintptr_t *result) 1089 { 1090 struct aw_mmc_softc *sc; 1091 1092 sc = device_get_softc(bus); 1093 switch (which) { 1094 default: 1095 return (EINVAL); 1096 case MMCBR_IVAR_BUS_MODE: 1097 *(int *)result = sc->aw_host.ios.bus_mode; 1098 break; 1099 case MMCBR_IVAR_BUS_WIDTH: 1100 *(int *)result = sc->aw_host.ios.bus_width; 1101 break; 1102 case MMCBR_IVAR_CHIP_SELECT: 1103 *(int *)result = sc->aw_host.ios.chip_select; 1104 break; 1105 case MMCBR_IVAR_CLOCK: 1106 *(int *)result = sc->aw_host.ios.clock; 1107 break; 1108 case MMCBR_IVAR_F_MIN: 1109 *(int *)result = sc->aw_host.f_min; 1110 break; 1111 case MMCBR_IVAR_F_MAX: 1112 *(int *)result = sc->aw_host.f_max; 1113 break; 1114 case MMCBR_IVAR_HOST_OCR: 1115 *(int *)result = sc->aw_host.host_ocr; 1116 break; 1117 case MMCBR_IVAR_MODE: 1118 *(int *)result = sc->aw_host.mode; 1119 break; 1120 case MMCBR_IVAR_OCR: 1121 *(int *)result = sc->aw_host.ocr; 1122 break; 1123 case MMCBR_IVAR_POWER_MODE: 1124 *(int *)result = sc->aw_host.ios.power_mode; 1125 break; 1126 case MMCBR_IVAR_VDD: 1127 *(int *)result = sc->aw_host.ios.vdd; 1128 break; 1129 case MMCBR_IVAR_VCCQ: 1130 *(int *)result = sc->aw_host.ios.vccq; 1131 break; 1132 case MMCBR_IVAR_CAPS: 1133 *(int *)result = sc->aw_host.caps; 1134 break; 1135 case MMCBR_IVAR_TIMING: 1136 *(int *)result = sc->aw_host.ios.timing; 1137 break; 1138 case MMCBR_IVAR_MAX_DATA: 1139 *(int *)result = (sc->aw_mmc_conf->dma_xferlen * 1140 AW_MMC_DMA_SEGS) / MMC_SECTOR_SIZE; 1141 break; 1142 case MMCBR_IVAR_RETUNE_REQ: 1143 *(int *)result = retune_req_none; 1144 break; 1145 } 1146 1147 return (0); 1148 } 1149 1150 static int 1151 aw_mmc_write_ivar(device_t bus, device_t child, int which, 1152 uintptr_t value) 1153 { 1154 struct aw_mmc_softc *sc; 1155 1156 sc = device_get_softc(bus); 1157 switch (which) { 1158 default: 1159 return (EINVAL); 1160 case MMCBR_IVAR_BUS_MODE: 1161 sc->aw_host.ios.bus_mode = value; 1162 break; 1163 case MMCBR_IVAR_BUS_WIDTH: 1164 sc->aw_host.ios.bus_width = value; 1165 break; 1166 case MMCBR_IVAR_CHIP_SELECT: 1167 sc->aw_host.ios.chip_select = value; 1168 break; 1169 case MMCBR_IVAR_CLOCK: 1170 sc->aw_host.ios.clock = value; 1171 break; 1172 case MMCBR_IVAR_MODE: 1173 sc->aw_host.mode = value; 1174 break; 1175 case MMCBR_IVAR_OCR: 1176 sc->aw_host.ocr = value; 1177 break; 1178 case MMCBR_IVAR_POWER_MODE: 1179 sc->aw_host.ios.power_mode = value; 1180 break; 1181 case MMCBR_IVAR_VDD: 1182 sc->aw_host.ios.vdd = value; 1183 break; 1184 case MMCBR_IVAR_VCCQ: 1185 sc->aw_host.ios.vccq = value; 1186 break; 1187 case MMCBR_IVAR_TIMING: 1188 sc->aw_host.ios.timing = value; 1189 break; 1190 /* These are read-only */ 1191 case MMCBR_IVAR_CAPS: 1192 case MMCBR_IVAR_HOST_OCR: 1193 case MMCBR_IVAR_F_MIN: 1194 case MMCBR_IVAR_F_MAX: 1195 case MMCBR_IVAR_MAX_DATA: 1196 return (EINVAL); 1197 } 1198 1199 return (0); 1200 } 1201 1202 static int 1203 aw_mmc_update_clock(struct aw_mmc_softc *sc, uint32_t clkon) 1204 { 1205 uint32_t reg; 1206 int retry; 1207 1208 reg = AW_MMC_READ_4(sc, AW_MMC_CKCR); 1209 reg &= ~(AW_MMC_CKCR_ENB | AW_MMC_CKCR_LOW_POWER | 1210 AW_MMC_CKCR_MASK_DATA0); 1211 1212 if (clkon) 1213 reg |= AW_MMC_CKCR_ENB; 1214 if (sc->aw_mmc_conf->mask_data0) 1215 reg |= AW_MMC_CKCR_MASK_DATA0; 1216 1217 AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg); 1218 1219 reg = AW_MMC_CMDR_LOAD | AW_MMC_CMDR_PRG_CLK | 1220 AW_MMC_CMDR_WAIT_PRE_OVER; 1221 AW_MMC_WRITE_4(sc, AW_MMC_CMDR, reg); 1222 retry = 0xfffff; 1223 1224 while (reg & AW_MMC_CMDR_LOAD && --retry > 0) { 1225 reg = AW_MMC_READ_4(sc, AW_MMC_CMDR); 1226 DELAY(10); 1227 } 1228 AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff); 1229 1230 if (reg & AW_MMC_CMDR_LOAD) { 1231 device_printf(sc->aw_dev, "timeout updating clock\n"); 1232 return (ETIMEDOUT); 1233 } 1234 1235 if (sc->aw_mmc_conf->mask_data0) { 1236 reg = AW_MMC_READ_4(sc, AW_MMC_CKCR); 1237 reg &= ~AW_MMC_CKCR_MASK_DATA0; 1238 AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg); 1239 } 1240 1241 return (0); 1242 } 1243 1244 #ifndef MMCCAM 1245 static int 1246 aw_mmc_switch_vccq(device_t bus, device_t child) 1247 { 1248 struct aw_mmc_softc *sc; 1249 int uvolt, err; 1250 1251 sc = device_get_softc(bus); 1252 1253 if (sc->mmc_helper.vqmmc_supply == NULL) 1254 return EOPNOTSUPP; 1255 1256 switch (sc->aw_host.ios.vccq) { 1257 case vccq_180: 1258 uvolt = 1800000; 1259 break; 1260 case vccq_330: 1261 uvolt = 3300000; 1262 break; 1263 default: 1264 return EINVAL; 1265 } 1266 1267 err = regulator_set_voltage(sc->mmc_helper.vqmmc_supply, uvolt, uvolt); 1268 if (err != 0) { 1269 device_printf(sc->aw_dev, 1270 "Cannot set vqmmc to %d<->%d\n", 1271 uvolt, 1272 uvolt); 1273 return (err); 1274 } 1275 1276 return (0); 1277 } 1278 #endif 1279 1280 static int 1281 aw_mmc_update_ios(device_t bus, device_t child) 1282 { 1283 int error; 1284 struct aw_mmc_softc *sc; 1285 struct mmc_ios *ios; 1286 unsigned int clock; 1287 uint32_t reg, div = 1; 1288 int reg_status; 1289 int rv; 1290 1291 sc = device_get_softc(bus); 1292 1293 ios = &sc->aw_host.ios; 1294 1295 /* Set the bus width. */ 1296 switch (ios->bus_width) { 1297 case bus_width_1: 1298 AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR1); 1299 break; 1300 case bus_width_4: 1301 AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR4); 1302 break; 1303 case bus_width_8: 1304 AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR8); 1305 break; 1306 } 1307 1308 switch (ios->power_mode) { 1309 case power_on: 1310 break; 1311 case power_off: 1312 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CARD)) 1313 device_printf(sc->aw_dev, "Powering down sd/mmc\n"); 1314 1315 if (sc->mmc_helper.vmmc_supply) { 1316 rv = regulator_status(sc->mmc_helper.vmmc_supply, ®_status); 1317 if (rv == 0 && reg_status == REGULATOR_STATUS_ENABLED) 1318 regulator_disable(sc->mmc_helper.vmmc_supply); 1319 } 1320 if (sc->mmc_helper.vqmmc_supply) { 1321 rv = regulator_status(sc->mmc_helper.vqmmc_supply, ®_status); 1322 if (rv == 0 && reg_status == REGULATOR_STATUS_ENABLED) 1323 regulator_disable(sc->mmc_helper.vqmmc_supply); 1324 } 1325 1326 aw_mmc_reset(sc); 1327 break; 1328 case power_up: 1329 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CARD)) 1330 device_printf(sc->aw_dev, "Powering up sd/mmc\n"); 1331 1332 if (sc->mmc_helper.vmmc_supply) { 1333 rv = regulator_status(sc->mmc_helper.vmmc_supply, ®_status); 1334 if (rv == 0 && reg_status != REGULATOR_STATUS_ENABLED) 1335 regulator_enable(sc->mmc_helper.vmmc_supply); 1336 } 1337 if (sc->mmc_helper.vqmmc_supply) { 1338 rv = regulator_status(sc->mmc_helper.vqmmc_supply, ®_status); 1339 if (rv == 0 && reg_status != REGULATOR_STATUS_ENABLED) 1340 regulator_enable(sc->mmc_helper.vqmmc_supply); 1341 } 1342 aw_mmc_init(sc); 1343 break; 1344 }; 1345 1346 /* Enable ddr mode if needed */ 1347 reg = AW_MMC_READ_4(sc, AW_MMC_GCTL); 1348 if (ios->timing == bus_timing_uhs_ddr50 || 1349 ios->timing == bus_timing_mmc_ddr52) 1350 reg |= AW_MMC_GCTL_DDR_MOD_SEL; 1351 else 1352 reg &= ~AW_MMC_GCTL_DDR_MOD_SEL; 1353 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg); 1354 1355 if (ios->clock && ios->clock != sc->aw_clock) { 1356 sc->aw_clock = clock = ios->clock; 1357 1358 /* Disable clock */ 1359 error = aw_mmc_update_clock(sc, 0); 1360 if (error != 0) 1361 return (error); 1362 1363 if (ios->timing == bus_timing_mmc_ddr52 && 1364 (sc->aw_mmc_conf->new_timing || 1365 ios->bus_width == bus_width_8)) { 1366 div = 2; 1367 clock <<= 1; 1368 } 1369 1370 /* Reset the divider. */ 1371 reg = AW_MMC_READ_4(sc, AW_MMC_CKCR); 1372 reg &= ~AW_MMC_CKCR_DIV; 1373 reg |= div - 1; 1374 AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg); 1375 1376 /* New timing mode if needed */ 1377 if (sc->aw_mmc_conf->new_timing) { 1378 reg = AW_MMC_READ_4(sc, AW_MMC_NTSR); 1379 reg |= AW_MMC_NTSR_MODE_SELECT; 1380 AW_MMC_WRITE_4(sc, AW_MMC_NTSR, reg); 1381 } 1382 1383 /* Set the MMC clock. */ 1384 error = clk_disable(sc->aw_clk_mmc); 1385 if (error != 0 && bootverbose) 1386 device_printf(sc->aw_dev, 1387 "failed to disable mmc clock: %d\n", error); 1388 error = clk_set_freq(sc->aw_clk_mmc, clock, 1389 CLK_SET_ROUND_DOWN); 1390 if (error != 0) { 1391 device_printf(sc->aw_dev, 1392 "failed to set frequency to %u Hz: %d\n", 1393 clock, error); 1394 return (error); 1395 } 1396 error = clk_enable(sc->aw_clk_mmc); 1397 if (error != 0 && bootverbose) 1398 device_printf(sc->aw_dev, 1399 "failed to re-enable mmc clock: %d\n", error); 1400 1401 if (sc->aw_mmc_conf->can_calibrate) 1402 AW_MMC_WRITE_4(sc, AW_MMC_SAMP_DL, AW_MMC_SAMP_DL_SW_EN); 1403 1404 /* Enable clock. */ 1405 error = aw_mmc_update_clock(sc, 1); 1406 if (error != 0) 1407 return (error); 1408 } 1409 1410 return (0); 1411 } 1412 1413 #ifndef MMCCAM 1414 static int 1415 aw_mmc_get_ro(device_t bus, device_t child) 1416 { 1417 struct aw_mmc_softc *sc; 1418 1419 sc = device_get_softc(bus); 1420 1421 return (mmc_fdt_gpio_get_readonly(&sc->mmc_helper)); 1422 } 1423 1424 static int 1425 aw_mmc_acquire_host(device_t bus, device_t child) 1426 { 1427 struct aw_mmc_softc *sc; 1428 int error; 1429 1430 sc = device_get_softc(bus); 1431 AW_MMC_LOCK(sc); 1432 while (sc->aw_bus_busy) { 1433 error = msleep(sc, &sc->aw_mtx, PCATCH, "mmchw", 0); 1434 if (error != 0) { 1435 AW_MMC_UNLOCK(sc); 1436 return (error); 1437 } 1438 } 1439 sc->aw_bus_busy++; 1440 AW_MMC_UNLOCK(sc); 1441 1442 return (0); 1443 } 1444 1445 static int 1446 aw_mmc_release_host(device_t bus, device_t child) 1447 { 1448 struct aw_mmc_softc *sc; 1449 1450 sc = device_get_softc(bus); 1451 AW_MMC_LOCK(sc); 1452 sc->aw_bus_busy--; 1453 wakeup(sc); 1454 AW_MMC_UNLOCK(sc); 1455 1456 return (0); 1457 } 1458 #endif 1459 1460 static device_method_t aw_mmc_methods[] = { 1461 /* Device interface */ 1462 DEVMETHOD(device_probe, aw_mmc_probe), 1463 DEVMETHOD(device_attach, aw_mmc_attach), 1464 DEVMETHOD(device_detach, aw_mmc_detach), 1465 1466 /* Bus interface */ 1467 DEVMETHOD(bus_read_ivar, aw_mmc_read_ivar), 1468 DEVMETHOD(bus_write_ivar, aw_mmc_write_ivar), 1469 DEVMETHOD(bus_add_child, bus_generic_add_child), 1470 1471 #ifndef MMCCAM 1472 /* MMC bridge interface */ 1473 DEVMETHOD(mmcbr_update_ios, aw_mmc_update_ios), 1474 DEVMETHOD(mmcbr_request, aw_mmc_request), 1475 DEVMETHOD(mmcbr_get_ro, aw_mmc_get_ro), 1476 DEVMETHOD(mmcbr_switch_vccq, aw_mmc_switch_vccq), 1477 DEVMETHOD(mmcbr_acquire_host, aw_mmc_acquire_host), 1478 DEVMETHOD(mmcbr_release_host, aw_mmc_release_host), 1479 #endif 1480 1481 #ifdef MMCCAM 1482 /* MMCCAM interface */ 1483 DEVMETHOD(mmc_sim_get_tran_settings, aw_mmc_get_tran_settings), 1484 DEVMETHOD(mmc_sim_set_tran_settings, aw_mmc_set_tran_settings), 1485 DEVMETHOD(mmc_sim_cam_request, aw_mmc_cam_request), 1486 #endif 1487 1488 DEVMETHOD_END 1489 }; 1490 1491 static devclass_t aw_mmc_devclass; 1492 1493 static driver_t aw_mmc_driver = { 1494 "aw_mmc", 1495 aw_mmc_methods, 1496 sizeof(struct aw_mmc_softc), 1497 }; 1498 1499 DRIVER_MODULE(aw_mmc, simplebus, aw_mmc_driver, aw_mmc_devclass, NULL, 1500 NULL); 1501 #ifndef MMCCAM 1502 MMC_DECLARE_BRIDGE(aw_mmc); 1503 #endif 1504 SIMPLEBUS_PNP_INFO(compat_data); 1505