1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org> 5 * Copyright (c) 2013 Alexander Fedorov 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/kernel.h> 37 #include <sys/lock.h> 38 #include <sys/malloc.h> 39 #include <sys/module.h> 40 #include <sys/mutex.h> 41 #include <sys/resource.h> 42 #include <sys/rman.h> 43 #include <sys/sysctl.h> 44 45 #include <machine/bus.h> 46 47 #include <dev/ofw/ofw_bus.h> 48 #include <dev/ofw/ofw_bus_subr.h> 49 50 #include <dev/mmc/bridge.h> 51 #include <dev/mmc/mmcbrvar.h> 52 53 #include <arm/allwinner/aw_mmc.h> 54 #include <dev/extres/clk/clk.h> 55 #include <dev/extres/hwreset/hwreset.h> 56 #include <dev/extres/regulator/regulator.h> 57 58 #include "opt_mmccam.h" 59 60 #ifdef MMCCAM 61 #include <cam/cam.h> 62 #include <cam/cam_ccb.h> 63 #include <cam/cam_debug.h> 64 #include <cam/cam_sim.h> 65 #include <cam/cam_xpt_sim.h> 66 #endif 67 68 #define AW_MMC_MEMRES 0 69 #define AW_MMC_IRQRES 1 70 #define AW_MMC_RESSZ 2 71 #define AW_MMC_DMA_SEGS (PAGE_SIZE / sizeof(struct aw_mmc_dma_desc)) 72 #define AW_MMC_DMA_DESC_SIZE (sizeof(struct aw_mmc_dma_desc) * AW_MMC_DMA_SEGS) 73 #define AW_MMC_DMA_FTRGLEVEL 0x20070008 74 75 #define AW_MMC_RESET_RETRY 1000 76 77 #define CARD_ID_FREQUENCY 400000 78 79 struct aw_mmc_conf { 80 uint32_t dma_xferlen; 81 bool mask_data0; 82 bool can_calibrate; 83 bool new_timing; 84 }; 85 86 static const struct aw_mmc_conf a10_mmc_conf = { 87 .dma_xferlen = 0x2000, 88 }; 89 90 static const struct aw_mmc_conf a13_mmc_conf = { 91 .dma_xferlen = 0x10000, 92 }; 93 94 static const struct aw_mmc_conf a64_mmc_conf = { 95 .dma_xferlen = 0x10000, 96 .mask_data0 = true, 97 .can_calibrate = true, 98 .new_timing = true, 99 }; 100 101 static const struct aw_mmc_conf a64_emmc_conf = { 102 .dma_xferlen = 0x2000, 103 .can_calibrate = true, 104 }; 105 106 static struct ofw_compat_data compat_data[] = { 107 {"allwinner,sun4i-a10-mmc", (uintptr_t)&a10_mmc_conf}, 108 {"allwinner,sun5i-a13-mmc", (uintptr_t)&a13_mmc_conf}, 109 {"allwinner,sun7i-a20-mmc", (uintptr_t)&a13_mmc_conf}, 110 {"allwinner,sun50i-a64-mmc", (uintptr_t)&a64_mmc_conf}, 111 {"allwinner,sun50i-a64-emmc", (uintptr_t)&a64_emmc_conf}, 112 {NULL, 0} 113 }; 114 115 struct aw_mmc_softc { 116 device_t aw_dev; 117 clk_t aw_clk_ahb; 118 clk_t aw_clk_mmc; 119 hwreset_t aw_rst_ahb; 120 int aw_bus_busy; 121 int aw_resid; 122 int aw_timeout; 123 struct callout aw_timeoutc; 124 struct mmc_host aw_host; 125 #ifdef MMCCAM 126 union ccb * ccb; 127 struct cam_devq * devq; 128 struct cam_sim * sim; 129 struct mtx sim_mtx; 130 #else 131 struct mmc_request * aw_req; 132 #endif 133 struct mtx aw_mtx; 134 struct resource * aw_res[AW_MMC_RESSZ]; 135 struct aw_mmc_conf * aw_mmc_conf; 136 uint32_t aw_intr; 137 uint32_t aw_intr_wait; 138 void * aw_intrhand; 139 regulator_t aw_reg_vmmc; 140 regulator_t aw_reg_vqmmc; 141 unsigned int aw_clock; 142 143 /* Fields required for DMA access. */ 144 bus_addr_t aw_dma_desc_phys; 145 bus_dmamap_t aw_dma_map; 146 bus_dma_tag_t aw_dma_tag; 147 void * aw_dma_desc; 148 bus_dmamap_t aw_dma_buf_map; 149 bus_dma_tag_t aw_dma_buf_tag; 150 int aw_dma_map_err; 151 }; 152 153 static struct resource_spec aw_mmc_res_spec[] = { 154 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 155 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 156 { -1, 0, 0 } 157 }; 158 159 static int aw_mmc_probe(device_t); 160 static int aw_mmc_attach(device_t); 161 static int aw_mmc_detach(device_t); 162 static int aw_mmc_setup_dma(struct aw_mmc_softc *); 163 static int aw_mmc_reset(struct aw_mmc_softc *); 164 static int aw_mmc_init(struct aw_mmc_softc *); 165 static void aw_mmc_intr(void *); 166 static int aw_mmc_update_clock(struct aw_mmc_softc *, uint32_t); 167 168 static void aw_mmc_print_error(uint32_t); 169 static int aw_mmc_update_ios(device_t, device_t); 170 static int aw_mmc_request(device_t, device_t, struct mmc_request *); 171 static int aw_mmc_get_ro(device_t, device_t); 172 static int aw_mmc_acquire_host(device_t, device_t); 173 static int aw_mmc_release_host(device_t, device_t); 174 #ifdef MMCCAM 175 static void aw_mmc_cam_action(struct cam_sim *, union ccb *); 176 static void aw_mmc_cam_poll(struct cam_sim *); 177 static int aw_mmc_cam_settran_settings(struct aw_mmc_softc *, union ccb *); 178 static int aw_mmc_cam_request(struct aw_mmc_softc *, union ccb *); 179 static void aw_mmc_cam_handle_mmcio(struct cam_sim *, union ccb *); 180 #endif 181 182 #define AW_MMC_LOCK(_sc) mtx_lock(&(_sc)->aw_mtx) 183 #define AW_MMC_UNLOCK(_sc) mtx_unlock(&(_sc)->aw_mtx) 184 #define AW_MMC_READ_4(_sc, _reg) \ 185 bus_read_4((_sc)->aw_res[AW_MMC_MEMRES], _reg) 186 #define AW_MMC_WRITE_4(_sc, _reg, _value) \ 187 bus_write_4((_sc)->aw_res[AW_MMC_MEMRES], _reg, _value) 188 189 #ifdef MMCCAM 190 static void 191 aw_mmc_cam_handle_mmcio(struct cam_sim *sim, union ccb *ccb) 192 { 193 struct aw_mmc_softc *sc; 194 195 sc = cam_sim_softc(sim); 196 197 aw_mmc_cam_request(sc, ccb); 198 } 199 200 static void 201 aw_mmc_cam_action(struct cam_sim *sim, union ccb *ccb) 202 { 203 struct aw_mmc_softc *sc; 204 205 sc = cam_sim_softc(sim); 206 if (sc == NULL) { 207 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 208 xpt_done(ccb); 209 return; 210 } 211 212 mtx_assert(&sc->sim_mtx, MA_OWNED); 213 214 switch (ccb->ccb_h.func_code) { 215 case XPT_PATH_INQ: 216 mmc_path_inq(&ccb->cpi, "Deglitch Networks", sim, 217 (sc->aw_mmc_conf->dma_xferlen * AW_MMC_DMA_SEGS) / 218 MMC_SECTOR_SIZE); 219 break; 220 221 case XPT_GET_TRAN_SETTINGS: 222 { 223 struct ccb_trans_settings *cts = &ccb->cts; 224 225 if (bootverbose) 226 device_printf(sc->aw_dev, "Got XPT_GET_TRAN_SETTINGS\n"); 227 228 cts->protocol = PROTO_MMCSD; 229 cts->protocol_version = 1; 230 cts->transport = XPORT_MMCSD; 231 cts->transport_version = 1; 232 cts->xport_specific.valid = 0; 233 cts->proto_specific.mmc.host_ocr = sc->aw_host.host_ocr; 234 cts->proto_specific.mmc.host_f_min = sc->aw_host.f_min; 235 cts->proto_specific.mmc.host_f_max = sc->aw_host.f_max; 236 cts->proto_specific.mmc.host_caps = sc->aw_host.caps; 237 cts->proto_specific.mmc.host_max_data = (sc->aw_mmc_conf->dma_xferlen * 238 AW_MMC_DMA_SEGS) / MMC_SECTOR_SIZE; 239 memcpy(&cts->proto_specific.mmc.ios, &sc->aw_host.ios, sizeof(struct mmc_ios)); 240 ccb->ccb_h.status = CAM_REQ_CMP; 241 break; 242 } 243 case XPT_SET_TRAN_SETTINGS: 244 { 245 if (bootverbose) 246 device_printf(sc->aw_dev, "Got XPT_SET_TRAN_SETTINGS\n"); 247 aw_mmc_cam_settran_settings(sc, ccb); 248 ccb->ccb_h.status = CAM_REQ_CMP; 249 break; 250 } 251 case XPT_RESET_BUS: 252 if (bootverbose) 253 device_printf(sc->aw_dev, "Got XPT_RESET_BUS, ACK it...\n"); 254 ccb->ccb_h.status = CAM_REQ_CMP; 255 break; 256 case XPT_MMC_IO: 257 /* 258 * Here is the HW-dependent part of 259 * sending the command to the underlying h/w 260 * At some point in the future an interrupt comes. 261 * Then the request will be marked as completed. 262 */ 263 ccb->ccb_h.status = CAM_REQ_INPROG; 264 265 aw_mmc_cam_handle_mmcio(sim, ccb); 266 return; 267 /* NOTREACHED */ 268 break; 269 default: 270 ccb->ccb_h.status = CAM_REQ_INVALID; 271 break; 272 } 273 xpt_done(ccb); 274 return; 275 } 276 277 static void 278 aw_mmc_cam_poll(struct cam_sim *sim) 279 { 280 return; 281 } 282 283 static int 284 aw_mmc_cam_settran_settings(struct aw_mmc_softc *sc, union ccb *ccb) 285 { 286 struct mmc_ios *ios; 287 struct mmc_ios *new_ios; 288 struct ccb_trans_settings_mmc *cts; 289 290 ios = &sc->aw_host.ios; 291 292 cts = &ccb->cts.proto_specific.mmc; 293 new_ios = &cts->ios; 294 295 /* Update only requested fields */ 296 if (cts->ios_valid & MMC_CLK) { 297 ios->clock = new_ios->clock; 298 device_printf(sc->aw_dev, "Clock => %d\n", ios->clock); 299 } 300 if (cts->ios_valid & MMC_VDD) { 301 ios->vdd = new_ios->vdd; 302 device_printf(sc->aw_dev, "VDD => %d\n", ios->vdd); 303 } 304 if (cts->ios_valid & MMC_CS) { 305 ios->chip_select = new_ios->chip_select; 306 device_printf(sc->aw_dev, "CS => %d\n", ios->chip_select); 307 } 308 if (cts->ios_valid & MMC_BW) { 309 ios->bus_width = new_ios->bus_width; 310 device_printf(sc->aw_dev, "Bus width => %d\n", ios->bus_width); 311 } 312 if (cts->ios_valid & MMC_PM) { 313 ios->power_mode = new_ios->power_mode; 314 device_printf(sc->aw_dev, "Power mode => %d\n", ios->power_mode); 315 } 316 if (cts->ios_valid & MMC_BT) { 317 ios->timing = new_ios->timing; 318 device_printf(sc->aw_dev, "Timing => %d\n", ios->timing); 319 } 320 if (cts->ios_valid & MMC_BM) { 321 ios->bus_mode = new_ios->bus_mode; 322 device_printf(sc->aw_dev, "Bus mode => %d\n", ios->bus_mode); 323 } 324 325 return (aw_mmc_update_ios(sc->aw_dev, NULL)); 326 } 327 328 static int 329 aw_mmc_cam_request(struct aw_mmc_softc *sc, union ccb *ccb) 330 { 331 struct ccb_mmcio *mmcio; 332 333 mmcio = &ccb->mmcio; 334 335 AW_MMC_LOCK(sc); 336 337 #ifdef DEBUG 338 if (__predict_false(bootverbose)) { 339 device_printf(sc->aw_dev, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 340 mmcio->cmd.opcode, mmcio->cmd.arg, mmcio->cmd.flags, 341 mmcio->cmd.data != NULL ? (unsigned int) mmcio->cmd.data->len : 0, 342 mmcio->cmd.data != NULL ? mmcio->cmd.data->flags: 0); 343 } 344 #endif 345 if (mmcio->cmd.data != NULL) { 346 if (mmcio->cmd.data->len == 0 || mmcio->cmd.data->flags == 0) 347 panic("data->len = %d, data->flags = %d -- something is b0rked", 348 (int)mmcio->cmd.data->len, mmcio->cmd.data->flags); 349 } 350 if (sc->ccb != NULL) { 351 device_printf(sc->aw_dev, "Controller still has an active command\n"); 352 return (EBUSY); 353 } 354 sc->ccb = ccb; 355 /* aw_mmc_request locks again */ 356 AW_MMC_UNLOCK(sc); 357 aw_mmc_request(sc->aw_dev, NULL, NULL); 358 359 return (0); 360 } 361 #endif /* MMCCAM */ 362 363 static int 364 aw_mmc_probe(device_t dev) 365 { 366 367 if (!ofw_bus_status_okay(dev)) 368 return (ENXIO); 369 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 370 return (ENXIO); 371 372 device_set_desc(dev, "Allwinner Integrated MMC/SD controller"); 373 374 return (BUS_PROBE_DEFAULT); 375 } 376 377 static int 378 aw_mmc_attach(device_t dev) 379 { 380 device_t child; 381 struct aw_mmc_softc *sc; 382 struct sysctl_ctx_list *ctx; 383 struct sysctl_oid_list *tree; 384 uint32_t bus_width, max_freq; 385 phandle_t node; 386 int error; 387 388 node = ofw_bus_get_node(dev); 389 sc = device_get_softc(dev); 390 sc->aw_dev = dev; 391 392 sc->aw_mmc_conf = (struct aw_mmc_conf *)ofw_bus_search_compatible(dev, compat_data)->ocd_data; 393 394 #ifndef MMCCAM 395 sc->aw_req = NULL; 396 #endif 397 if (bus_alloc_resources(dev, aw_mmc_res_spec, sc->aw_res) != 0) { 398 device_printf(dev, "cannot allocate device resources\n"); 399 return (ENXIO); 400 } 401 if (bus_setup_intr(dev, sc->aw_res[AW_MMC_IRQRES], 402 INTR_TYPE_MISC | INTR_MPSAFE, NULL, aw_mmc_intr, sc, 403 &sc->aw_intrhand)) { 404 bus_release_resources(dev, aw_mmc_res_spec, sc->aw_res); 405 device_printf(dev, "cannot setup interrupt handler\n"); 406 return (ENXIO); 407 } 408 mtx_init(&sc->aw_mtx, device_get_nameunit(sc->aw_dev), "aw_mmc", 409 MTX_DEF); 410 callout_init_mtx(&sc->aw_timeoutc, &sc->aw_mtx, 0); 411 412 /* De-assert reset */ 413 if (hwreset_get_by_ofw_name(dev, 0, "ahb", &sc->aw_rst_ahb) == 0) { 414 error = hwreset_deassert(sc->aw_rst_ahb); 415 if (error != 0) { 416 device_printf(dev, "cannot de-assert reset\n"); 417 goto fail; 418 } 419 } 420 421 /* Activate the module clock. */ 422 error = clk_get_by_ofw_name(dev, 0, "ahb", &sc->aw_clk_ahb); 423 if (error != 0) { 424 device_printf(dev, "cannot get ahb clock\n"); 425 goto fail; 426 } 427 error = clk_enable(sc->aw_clk_ahb); 428 if (error != 0) { 429 device_printf(dev, "cannot enable ahb clock\n"); 430 goto fail; 431 } 432 error = clk_get_by_ofw_name(dev, 0, "mmc", &sc->aw_clk_mmc); 433 if (error != 0) { 434 device_printf(dev, "cannot get mmc clock\n"); 435 goto fail; 436 } 437 error = clk_set_freq(sc->aw_clk_mmc, CARD_ID_FREQUENCY, 438 CLK_SET_ROUND_DOWN); 439 if (error != 0) { 440 device_printf(dev, "cannot init mmc clock\n"); 441 goto fail; 442 } 443 error = clk_enable(sc->aw_clk_mmc); 444 if (error != 0) { 445 device_printf(dev, "cannot enable mmc clock\n"); 446 goto fail; 447 } 448 449 sc->aw_timeout = 10; 450 ctx = device_get_sysctl_ctx(dev); 451 tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 452 SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "req_timeout", CTLFLAG_RW, 453 &sc->aw_timeout, 0, "Request timeout in seconds"); 454 455 /* Soft Reset controller. */ 456 if (aw_mmc_reset(sc) != 0) { 457 device_printf(dev, "cannot reset the controller\n"); 458 goto fail; 459 } 460 461 if (aw_mmc_setup_dma(sc) != 0) { 462 device_printf(sc->aw_dev, "Couldn't setup DMA!\n"); 463 goto fail; 464 } 465 466 if (OF_getencprop(node, "bus-width", &bus_width, sizeof(uint32_t)) <= 0) 467 bus_width = 4; 468 469 if (regulator_get_by_ofw_property(dev, 0, "vmmc-supply", 470 &sc->aw_reg_vmmc) == 0) { 471 if (bootverbose) 472 device_printf(dev, "vmmc-supply regulator found\n"); 473 } 474 if (regulator_get_by_ofw_property(dev, 0, "vqmmc-supply", 475 &sc->aw_reg_vqmmc) == 0 && bootverbose) { 476 if (bootverbose) 477 device_printf(dev, "vqmmc-supply regulator found\n"); 478 } 479 480 sc->aw_host.f_min = 400000; 481 482 if (OF_getencprop(node, "max-frequency", &max_freq, 483 sizeof(uint32_t)) <= 0) 484 max_freq = 52000000; 485 sc->aw_host.f_max = max_freq; 486 487 sc->aw_host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340; 488 sc->aw_host.caps = MMC_CAP_HSPEED | MMC_CAP_UHS_SDR12 | 489 MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR50 | 490 MMC_CAP_UHS_DDR50 | MMC_CAP_MMC_DDR52; 491 492 if (sc->aw_reg_vqmmc != NULL) { 493 if (regulator_check_voltage(sc->aw_reg_vqmmc, 1800000) == 0) 494 sc->aw_host.caps |= MMC_CAP_SIGNALING_180; 495 if (regulator_check_voltage(sc->aw_reg_vqmmc, 3300000) == 0) 496 sc->aw_host.caps |= MMC_CAP_SIGNALING_330; 497 } else 498 sc->aw_host.caps |= MMC_CAP_SIGNALING_330; 499 500 if (bus_width >= 4) 501 sc->aw_host.caps |= MMC_CAP_4_BIT_DATA; 502 if (bus_width >= 8) 503 sc->aw_host.caps |= MMC_CAP_8_BIT_DATA; 504 505 #ifdef MMCCAM 506 child = NULL; /* Not used by MMCCAM, need to silence compiler warnings */ 507 sc->ccb = NULL; 508 if ((sc->devq = cam_simq_alloc(1)) == NULL) { 509 goto fail; 510 } 511 512 mtx_init(&sc->sim_mtx, "awmmcsim", NULL, MTX_DEF); 513 sc->sim = cam_sim_alloc_dev(aw_mmc_cam_action, aw_mmc_cam_poll, 514 "aw_mmc_sim", sc, dev, 515 &sc->sim_mtx, 1, 1, sc->devq); 516 517 if (sc->sim == NULL) { 518 cam_simq_free(sc->devq); 519 device_printf(dev, "cannot allocate CAM SIM\n"); 520 goto fail; 521 } 522 523 mtx_lock(&sc->sim_mtx); 524 if (xpt_bus_register(sc->sim, sc->aw_dev, 0) != 0) { 525 device_printf(dev, "cannot register SCSI pass-through bus\n"); 526 cam_sim_free(sc->sim, FALSE); 527 cam_simq_free(sc->devq); 528 mtx_unlock(&sc->sim_mtx); 529 goto fail; 530 } 531 532 mtx_unlock(&sc->sim_mtx); 533 #else /* !MMCCAM */ 534 child = device_add_child(dev, "mmc", -1); 535 if (child == NULL) { 536 device_printf(dev, "attaching MMC bus failed!\n"); 537 goto fail; 538 } 539 if (device_probe_and_attach(child) != 0) { 540 device_printf(dev, "attaching MMC child failed!\n"); 541 device_delete_child(dev, child); 542 goto fail; 543 } 544 #endif /* MMCCAM */ 545 return (0); 546 547 fail: 548 callout_drain(&sc->aw_timeoutc); 549 mtx_destroy(&sc->aw_mtx); 550 bus_teardown_intr(dev, sc->aw_res[AW_MMC_IRQRES], sc->aw_intrhand); 551 bus_release_resources(dev, aw_mmc_res_spec, sc->aw_res); 552 553 #ifdef MMCCAM 554 if (sc->sim != NULL) { 555 mtx_lock(&sc->sim_mtx); 556 xpt_bus_deregister(cam_sim_path(sc->sim)); 557 cam_sim_free(sc->sim, FALSE); 558 mtx_unlock(&sc->sim_mtx); 559 } 560 561 if (sc->devq != NULL) 562 cam_simq_free(sc->devq); 563 #endif 564 return (ENXIO); 565 } 566 567 static int 568 aw_mmc_detach(device_t dev) 569 { 570 571 return (EBUSY); 572 } 573 574 static void 575 aw_dma_desc_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err) 576 { 577 struct aw_mmc_softc *sc; 578 579 sc = (struct aw_mmc_softc *)arg; 580 if (err) { 581 sc->aw_dma_map_err = err; 582 return; 583 } 584 sc->aw_dma_desc_phys = segs[0].ds_addr; 585 } 586 587 static int 588 aw_mmc_setup_dma(struct aw_mmc_softc *sc) 589 { 590 int error; 591 592 /* Allocate the DMA descriptor memory. */ 593 error = bus_dma_tag_create( 594 bus_get_dma_tag(sc->aw_dev), /* parent */ 595 AW_MMC_DMA_ALIGN, 0, /* align, boundary */ 596 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 597 BUS_SPACE_MAXADDR, /* highaddr */ 598 NULL, NULL, /* filter, filterarg*/ 599 AW_MMC_DMA_DESC_SIZE, 1, /* maxsize, nsegment */ 600 AW_MMC_DMA_DESC_SIZE, /* maxsegsize */ 601 0, /* flags */ 602 NULL, NULL, /* lock, lockarg*/ 603 &sc->aw_dma_tag); 604 if (error) 605 return (error); 606 607 error = bus_dmamem_alloc(sc->aw_dma_tag, &sc->aw_dma_desc, 608 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, 609 &sc->aw_dma_map); 610 if (error) 611 return (error); 612 613 error = bus_dmamap_load(sc->aw_dma_tag, 614 sc->aw_dma_map, 615 sc->aw_dma_desc, AW_MMC_DMA_DESC_SIZE, 616 aw_dma_desc_cb, sc, 0); 617 if (error) 618 return (error); 619 if (sc->aw_dma_map_err) 620 return (sc->aw_dma_map_err); 621 622 /* Create the DMA map for data transfers. */ 623 error = bus_dma_tag_create( 624 bus_get_dma_tag(sc->aw_dev), /* parent */ 625 AW_MMC_DMA_ALIGN, 0, /* align, boundary */ 626 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 627 BUS_SPACE_MAXADDR, /* highaddr */ 628 NULL, NULL, /* filter, filterarg*/ 629 sc->aw_mmc_conf->dma_xferlen * 630 AW_MMC_DMA_SEGS, AW_MMC_DMA_SEGS, /* maxsize, nsegments */ 631 sc->aw_mmc_conf->dma_xferlen, /* maxsegsize */ 632 BUS_DMA_ALLOCNOW, /* flags */ 633 NULL, NULL, /* lock, lockarg*/ 634 &sc->aw_dma_buf_tag); 635 if (error) 636 return (error); 637 error = bus_dmamap_create(sc->aw_dma_buf_tag, 0, 638 &sc->aw_dma_buf_map); 639 if (error) 640 return (error); 641 642 return (0); 643 } 644 645 static void 646 aw_dma_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err) 647 { 648 int i; 649 struct aw_mmc_dma_desc *dma_desc; 650 struct aw_mmc_softc *sc; 651 652 sc = (struct aw_mmc_softc *)arg; 653 sc->aw_dma_map_err = err; 654 655 if (err) 656 return; 657 658 dma_desc = sc->aw_dma_desc; 659 for (i = 0; i < nsegs; i++) { 660 if (segs[i].ds_len == sc->aw_mmc_conf->dma_xferlen) 661 dma_desc[i].buf_size = 0; /* Size of 0 indicate max len */ 662 else 663 dma_desc[i].buf_size = segs[i].ds_len; 664 dma_desc[i].buf_addr = segs[i].ds_addr; 665 dma_desc[i].config = AW_MMC_DMA_CONFIG_CH | 666 AW_MMC_DMA_CONFIG_OWN | AW_MMC_DMA_CONFIG_DIC; 667 668 dma_desc[i].next = sc->aw_dma_desc_phys + 669 ((i + 1) * sizeof(struct aw_mmc_dma_desc)); 670 } 671 672 dma_desc[0].config |= AW_MMC_DMA_CONFIG_FD; 673 dma_desc[nsegs - 1].config |= AW_MMC_DMA_CONFIG_LD | 674 AW_MMC_DMA_CONFIG_ER; 675 dma_desc[nsegs - 1].config &= ~AW_MMC_DMA_CONFIG_DIC; 676 dma_desc[nsegs - 1].next = 0; 677 } 678 679 static int 680 aw_mmc_prepare_dma(struct aw_mmc_softc *sc) 681 { 682 bus_dmasync_op_t sync_op; 683 int error; 684 struct mmc_command *cmd; 685 uint32_t val; 686 687 #ifdef MMCCAM 688 cmd = &sc->ccb->mmcio.cmd; 689 #else 690 cmd = sc->aw_req->cmd; 691 #endif 692 if (cmd->data->len > (sc->aw_mmc_conf->dma_xferlen * AW_MMC_DMA_SEGS)) 693 return (EFBIG); 694 error = bus_dmamap_load(sc->aw_dma_buf_tag, sc->aw_dma_buf_map, 695 cmd->data->data, cmd->data->len, aw_dma_cb, sc, 0); 696 if (error) 697 return (error); 698 if (sc->aw_dma_map_err) 699 return (sc->aw_dma_map_err); 700 701 if (cmd->data->flags & MMC_DATA_WRITE) 702 sync_op = BUS_DMASYNC_PREWRITE; 703 else 704 sync_op = BUS_DMASYNC_PREREAD; 705 bus_dmamap_sync(sc->aw_dma_buf_tag, sc->aw_dma_buf_map, sync_op); 706 bus_dmamap_sync(sc->aw_dma_tag, sc->aw_dma_map, BUS_DMASYNC_PREWRITE); 707 708 /* Enable DMA */ 709 val = AW_MMC_READ_4(sc, AW_MMC_GCTL); 710 val &= ~AW_MMC_GCTL_FIFO_AC_MOD; 711 val |= AW_MMC_GCTL_DMA_ENB; 712 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val); 713 714 /* Reset DMA */ 715 val |= AW_MMC_GCTL_DMA_RST; 716 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val); 717 718 AW_MMC_WRITE_4(sc, AW_MMC_DMAC, AW_MMC_DMAC_IDMAC_SOFT_RST); 719 AW_MMC_WRITE_4(sc, AW_MMC_DMAC, 720 AW_MMC_DMAC_IDMAC_IDMA_ON | AW_MMC_DMAC_IDMAC_FIX_BURST); 721 722 /* Enable RX or TX DMA interrupt */ 723 val = AW_MMC_READ_4(sc, AW_MMC_IDIE); 724 if (cmd->data->flags & MMC_DATA_WRITE) 725 val |= AW_MMC_IDST_TX_INT; 726 else 727 val |= AW_MMC_IDST_RX_INT; 728 AW_MMC_WRITE_4(sc, AW_MMC_IDIE, val); 729 730 /* Set DMA descritptor list address */ 731 AW_MMC_WRITE_4(sc, AW_MMC_DLBA, sc->aw_dma_desc_phys); 732 733 /* FIFO trigger level */ 734 AW_MMC_WRITE_4(sc, AW_MMC_FWLR, AW_MMC_DMA_FTRGLEVEL); 735 736 return (0); 737 } 738 739 static int 740 aw_mmc_reset(struct aw_mmc_softc *sc) 741 { 742 uint32_t reg; 743 int timeout; 744 745 reg = AW_MMC_READ_4(sc, AW_MMC_GCTL); 746 reg |= AW_MMC_GCTL_RESET; 747 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg); 748 timeout = AW_MMC_RESET_RETRY; 749 while (--timeout > 0) { 750 if ((AW_MMC_READ_4(sc, AW_MMC_GCTL) & AW_MMC_GCTL_RESET) == 0) 751 break; 752 DELAY(100); 753 } 754 if (timeout == 0) 755 return (ETIMEDOUT); 756 757 return (0); 758 } 759 760 static int 761 aw_mmc_init(struct aw_mmc_softc *sc) 762 { 763 uint32_t reg; 764 int ret; 765 766 ret = aw_mmc_reset(sc); 767 if (ret != 0) 768 return (ret); 769 770 /* Set the timeout. */ 771 AW_MMC_WRITE_4(sc, AW_MMC_TMOR, 772 AW_MMC_TMOR_DTO_LMT_SHIFT(AW_MMC_TMOR_DTO_LMT_MASK) | 773 AW_MMC_TMOR_RTO_LMT_SHIFT(AW_MMC_TMOR_RTO_LMT_MASK)); 774 775 /* Unmask interrupts. */ 776 AW_MMC_WRITE_4(sc, AW_MMC_IMKR, 0); 777 778 /* Clear pending interrupts. */ 779 AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff); 780 781 /* Debug register, undocumented */ 782 AW_MMC_WRITE_4(sc, AW_MMC_DBGC, 0xdeb); 783 784 /* Function select register */ 785 AW_MMC_WRITE_4(sc, AW_MMC_FUNS, 0xceaa0000); 786 787 AW_MMC_WRITE_4(sc, AW_MMC_IDST, 0xffffffff); 788 789 /* Enable interrupts and disable AHB access. */ 790 reg = AW_MMC_READ_4(sc, AW_MMC_GCTL); 791 reg |= AW_MMC_GCTL_INT_ENB; 792 reg &= ~AW_MMC_GCTL_FIFO_AC_MOD; 793 reg &= ~AW_MMC_GCTL_WAIT_MEM_ACCESS; 794 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg); 795 796 return (0); 797 } 798 799 static void 800 aw_mmc_req_done(struct aw_mmc_softc *sc) 801 { 802 struct mmc_command *cmd; 803 #ifdef MMCCAM 804 union ccb *ccb; 805 #else 806 struct mmc_request *req; 807 #endif 808 uint32_t val, mask; 809 int retry; 810 811 #ifdef MMCCAM 812 ccb = sc->ccb; 813 cmd = &ccb->mmcio.cmd; 814 #else 815 cmd = sc->aw_req->cmd; 816 #endif 817 #ifdef DEBUG 818 if (bootverbose) { 819 device_printf(sc->aw_dev, "%s: cmd %d err %d\n", __func__, cmd->opcode, cmd->error); 820 } 821 #endif 822 if (cmd->error != MMC_ERR_NONE) { 823 /* Reset the FIFO and DMA engines. */ 824 mask = AW_MMC_GCTL_FIFO_RST | AW_MMC_GCTL_DMA_RST; 825 val = AW_MMC_READ_4(sc, AW_MMC_GCTL); 826 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val | mask); 827 828 retry = AW_MMC_RESET_RETRY; 829 while (--retry > 0) { 830 if ((AW_MMC_READ_4(sc, AW_MMC_GCTL) & 831 AW_MMC_GCTL_RESET) == 0) 832 break; 833 DELAY(100); 834 } 835 if (retry == 0) 836 device_printf(sc->aw_dev, 837 "timeout resetting DMA/FIFO\n"); 838 aw_mmc_update_clock(sc, 1); 839 } 840 841 callout_stop(&sc->aw_timeoutc); 842 sc->aw_intr = 0; 843 sc->aw_resid = 0; 844 sc->aw_dma_map_err = 0; 845 sc->aw_intr_wait = 0; 846 #ifdef MMCCAM 847 sc->ccb = NULL; 848 ccb->ccb_h.status = 849 (ccb->mmcio.cmd.error == 0 ? CAM_REQ_CMP : CAM_REQ_CMP_ERR); 850 xpt_done(ccb); 851 #else 852 req = sc->aw_req; 853 sc->aw_req = NULL; 854 req->done(req); 855 #endif 856 } 857 858 static void 859 aw_mmc_req_ok(struct aw_mmc_softc *sc) 860 { 861 int timeout; 862 struct mmc_command *cmd; 863 uint32_t status; 864 865 timeout = 1000; 866 while (--timeout > 0) { 867 status = AW_MMC_READ_4(sc, AW_MMC_STAR); 868 if ((status & AW_MMC_STAR_CARD_BUSY) == 0) 869 break; 870 DELAY(1000); 871 } 872 #ifdef MMCCAM 873 cmd = &sc->ccb->mmcio.cmd; 874 #else 875 cmd = sc->aw_req->cmd; 876 #endif 877 if (timeout == 0) { 878 cmd->error = MMC_ERR_FAILED; 879 aw_mmc_req_done(sc); 880 return; 881 } 882 if (cmd->flags & MMC_RSP_PRESENT) { 883 if (cmd->flags & MMC_RSP_136) { 884 cmd->resp[0] = AW_MMC_READ_4(sc, AW_MMC_RESP3); 885 cmd->resp[1] = AW_MMC_READ_4(sc, AW_MMC_RESP2); 886 cmd->resp[2] = AW_MMC_READ_4(sc, AW_MMC_RESP1); 887 cmd->resp[3] = AW_MMC_READ_4(sc, AW_MMC_RESP0); 888 } else 889 cmd->resp[0] = AW_MMC_READ_4(sc, AW_MMC_RESP0); 890 } 891 /* All data has been transferred ? */ 892 if (cmd->data != NULL && (sc->aw_resid << 2) < cmd->data->len) 893 cmd->error = MMC_ERR_FAILED; 894 aw_mmc_req_done(sc); 895 } 896 897 898 static inline void 899 set_mmc_error(struct aw_mmc_softc *sc, int error_code) 900 { 901 #ifdef MMCCAM 902 sc->ccb->mmcio.cmd.error = error_code; 903 #else 904 sc->aw_req->cmd->error = error_code; 905 #endif 906 } 907 908 static void 909 aw_mmc_timeout(void *arg) 910 { 911 struct aw_mmc_softc *sc; 912 913 sc = (struct aw_mmc_softc *)arg; 914 #ifdef MMCCAM 915 if (sc->ccb != NULL) { 916 #else 917 if (sc->aw_req != NULL) { 918 #endif 919 device_printf(sc->aw_dev, "controller timeout\n"); 920 set_mmc_error(sc, MMC_ERR_TIMEOUT); 921 aw_mmc_req_done(sc); 922 } else 923 device_printf(sc->aw_dev, 924 "Spurious timeout - no active request\n"); 925 } 926 927 static void 928 aw_mmc_print_error(uint32_t err) 929 { 930 if(err & AW_MMC_INT_RESP_ERR) 931 printf("AW_MMC_INT_RESP_ERR "); 932 if (err & AW_MMC_INT_RESP_CRC_ERR) 933 printf("AW_MMC_INT_RESP_CRC_ERR "); 934 if (err & AW_MMC_INT_DATA_CRC_ERR) 935 printf("AW_MMC_INT_DATA_CRC_ERR "); 936 if (err & AW_MMC_INT_RESP_TIMEOUT) 937 printf("AW_MMC_INT_RESP_TIMEOUT "); 938 if (err & AW_MMC_INT_FIFO_RUN_ERR) 939 printf("AW_MMC_INT_FIFO_RUN_ERR "); 940 if (err & AW_MMC_INT_CMD_BUSY) 941 printf("AW_MMC_INT_CMD_BUSY "); 942 if (err & AW_MMC_INT_DATA_START_ERR) 943 printf("AW_MMC_INT_DATA_START_ERR "); 944 if (err & AW_MMC_INT_DATA_END_BIT_ERR) 945 printf("AW_MMC_INT_DATA_END_BIT_ERR"); 946 printf("\n"); 947 } 948 949 static void 950 aw_mmc_intr(void *arg) 951 { 952 bus_dmasync_op_t sync_op; 953 struct aw_mmc_softc *sc; 954 struct mmc_data *data; 955 uint32_t idst, imask, rint; 956 957 sc = (struct aw_mmc_softc *)arg; 958 AW_MMC_LOCK(sc); 959 rint = AW_MMC_READ_4(sc, AW_MMC_RISR); 960 idst = AW_MMC_READ_4(sc, AW_MMC_IDST); 961 imask = AW_MMC_READ_4(sc, AW_MMC_IMKR); 962 if (idst == 0 && imask == 0 && rint == 0) { 963 AW_MMC_UNLOCK(sc); 964 return; 965 } 966 #ifdef DEBUG 967 device_printf(sc->aw_dev, "idst: %#x, imask: %#x, rint: %#x\n", 968 idst, imask, rint); 969 #endif 970 #ifdef MMCCAM 971 if (sc->ccb == NULL) { 972 #else 973 if (sc->aw_req == NULL) { 974 #endif 975 device_printf(sc->aw_dev, 976 "Spurious interrupt - no active request, rint: 0x%08X\n", 977 rint); 978 aw_mmc_print_error(rint); 979 goto end; 980 } 981 if (rint & AW_MMC_INT_ERR_BIT) { 982 if (bootverbose) 983 device_printf(sc->aw_dev, "error rint: 0x%08X\n", rint); 984 aw_mmc_print_error(rint); 985 if (rint & AW_MMC_INT_RESP_TIMEOUT) 986 set_mmc_error(sc, MMC_ERR_TIMEOUT); 987 else 988 set_mmc_error(sc, MMC_ERR_FAILED); 989 aw_mmc_req_done(sc); 990 goto end; 991 } 992 if (idst & AW_MMC_IDST_ERROR) { 993 device_printf(sc->aw_dev, "error idst: 0x%08x\n", idst); 994 set_mmc_error(sc, MMC_ERR_FAILED); 995 aw_mmc_req_done(sc); 996 goto end; 997 } 998 999 sc->aw_intr |= rint; 1000 #ifdef MMCCAM 1001 data = sc->ccb->mmcio.cmd.data; 1002 #else 1003 data = sc->aw_req->cmd->data; 1004 #endif 1005 if (data != NULL && (idst & AW_MMC_IDST_COMPLETE) != 0) { 1006 if (data->flags & MMC_DATA_WRITE) 1007 sync_op = BUS_DMASYNC_POSTWRITE; 1008 else 1009 sync_op = BUS_DMASYNC_POSTREAD; 1010 bus_dmamap_sync(sc->aw_dma_buf_tag, sc->aw_dma_buf_map, 1011 sync_op); 1012 bus_dmamap_sync(sc->aw_dma_tag, sc->aw_dma_map, 1013 BUS_DMASYNC_POSTWRITE); 1014 bus_dmamap_unload(sc->aw_dma_buf_tag, sc->aw_dma_buf_map); 1015 sc->aw_resid = data->len >> 2; 1016 } 1017 if ((sc->aw_intr & sc->aw_intr_wait) == sc->aw_intr_wait) 1018 aw_mmc_req_ok(sc); 1019 1020 end: 1021 AW_MMC_WRITE_4(sc, AW_MMC_IDST, idst); 1022 AW_MMC_WRITE_4(sc, AW_MMC_RISR, rint); 1023 AW_MMC_UNLOCK(sc); 1024 } 1025 1026 static int 1027 aw_mmc_request(device_t bus, device_t child, struct mmc_request *req) 1028 { 1029 int blksz; 1030 struct aw_mmc_softc *sc; 1031 struct mmc_command *cmd; 1032 uint32_t cmdreg, imask; 1033 int err; 1034 1035 sc = device_get_softc(bus); 1036 1037 AW_MMC_LOCK(sc); 1038 #ifdef MMCCAM 1039 KASSERT(req == NULL, ("req should be NULL in MMCCAM case!")); 1040 /* 1041 * For MMCCAM, sc->ccb has been NULL-checked and populated 1042 * by aw_mmc_cam_request() already. 1043 */ 1044 cmd = &sc->ccb->mmcio.cmd; 1045 #else 1046 if (sc->aw_req) { 1047 AW_MMC_UNLOCK(sc); 1048 return (EBUSY); 1049 } 1050 sc->aw_req = req; 1051 cmd = req->cmd; 1052 1053 #ifdef DEBUG 1054 if (bootverbose) 1055 device_printf(sc->aw_dev, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 1056 cmd->opcode, cmd->arg, cmd->flags, 1057 cmd->data != NULL ? (unsigned int)cmd->data->len : 0, 1058 cmd->data != NULL ? cmd->data->flags: 0); 1059 #endif 1060 #endif 1061 cmdreg = AW_MMC_CMDR_LOAD; 1062 imask = AW_MMC_INT_ERR_BIT; 1063 sc->aw_intr_wait = 0; 1064 sc->aw_intr = 0; 1065 sc->aw_resid = 0; 1066 cmd->error = MMC_ERR_NONE; 1067 1068 if (cmd->opcode == MMC_GO_IDLE_STATE) 1069 cmdreg |= AW_MMC_CMDR_SEND_INIT_SEQ; 1070 1071 if (cmd->flags & MMC_RSP_PRESENT) 1072 cmdreg |= AW_MMC_CMDR_RESP_RCV; 1073 if (cmd->flags & MMC_RSP_136) 1074 cmdreg |= AW_MMC_CMDR_LONG_RESP; 1075 if (cmd->flags & MMC_RSP_CRC) 1076 cmdreg |= AW_MMC_CMDR_CHK_RESP_CRC; 1077 1078 if (cmd->data) { 1079 cmdreg |= AW_MMC_CMDR_DATA_TRANS | AW_MMC_CMDR_WAIT_PRE_OVER; 1080 1081 if (cmd->data->flags & MMC_DATA_MULTI) { 1082 cmdreg |= AW_MMC_CMDR_STOP_CMD_FLAG; 1083 imask |= AW_MMC_INT_AUTO_STOP_DONE; 1084 sc->aw_intr_wait |= AW_MMC_INT_AUTO_STOP_DONE; 1085 } else { 1086 sc->aw_intr_wait |= AW_MMC_INT_DATA_OVER; 1087 imask |= AW_MMC_INT_DATA_OVER; 1088 } 1089 if (cmd->data->flags & MMC_DATA_WRITE) 1090 cmdreg |= AW_MMC_CMDR_DIR_WRITE; 1091 #ifdef MMCCAM 1092 if (cmd->data->flags & MMC_DATA_BLOCK_SIZE) { 1093 AW_MMC_WRITE_4(sc, AW_MMC_BKSR, cmd->data->block_size); 1094 AW_MMC_WRITE_4(sc, AW_MMC_BYCR, cmd->data->len); 1095 } else 1096 #endif 1097 { 1098 blksz = min(cmd->data->len, MMC_SECTOR_SIZE); 1099 AW_MMC_WRITE_4(sc, AW_MMC_BKSR, blksz); 1100 AW_MMC_WRITE_4(sc, AW_MMC_BYCR, cmd->data->len); 1101 } 1102 } else { 1103 imask |= AW_MMC_INT_CMD_DONE; 1104 } 1105 1106 /* Enable the interrupts we are interested in */ 1107 AW_MMC_WRITE_4(sc, AW_MMC_IMKR, imask); 1108 AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff); 1109 1110 /* Enable auto stop if needed */ 1111 AW_MMC_WRITE_4(sc, AW_MMC_A12A, 1112 cmdreg & AW_MMC_CMDR_STOP_CMD_FLAG ? 0 : 0xffff); 1113 1114 /* Write the command argument */ 1115 AW_MMC_WRITE_4(sc, AW_MMC_CAGR, cmd->arg); 1116 1117 /* 1118 * If we don't have data start the request 1119 * if we do prepare the dma request and start the request 1120 */ 1121 if (cmd->data == NULL) { 1122 AW_MMC_WRITE_4(sc, AW_MMC_CMDR, cmdreg | cmd->opcode); 1123 } else { 1124 err = aw_mmc_prepare_dma(sc); 1125 if (err != 0) 1126 device_printf(sc->aw_dev, "prepare_dma failed: %d\n", err); 1127 1128 AW_MMC_WRITE_4(sc, AW_MMC_CMDR, cmdreg | cmd->opcode); 1129 } 1130 1131 callout_reset(&sc->aw_timeoutc, sc->aw_timeout * hz, 1132 aw_mmc_timeout, sc); 1133 AW_MMC_UNLOCK(sc); 1134 1135 return (0); 1136 } 1137 1138 static int 1139 aw_mmc_read_ivar(device_t bus, device_t child, int which, 1140 uintptr_t *result) 1141 { 1142 struct aw_mmc_softc *sc; 1143 1144 sc = device_get_softc(bus); 1145 switch (which) { 1146 default: 1147 return (EINVAL); 1148 case MMCBR_IVAR_BUS_MODE: 1149 *(int *)result = sc->aw_host.ios.bus_mode; 1150 break; 1151 case MMCBR_IVAR_BUS_WIDTH: 1152 *(int *)result = sc->aw_host.ios.bus_width; 1153 break; 1154 case MMCBR_IVAR_CHIP_SELECT: 1155 *(int *)result = sc->aw_host.ios.chip_select; 1156 break; 1157 case MMCBR_IVAR_CLOCK: 1158 *(int *)result = sc->aw_host.ios.clock; 1159 break; 1160 case MMCBR_IVAR_F_MIN: 1161 *(int *)result = sc->aw_host.f_min; 1162 break; 1163 case MMCBR_IVAR_F_MAX: 1164 *(int *)result = sc->aw_host.f_max; 1165 break; 1166 case MMCBR_IVAR_HOST_OCR: 1167 *(int *)result = sc->aw_host.host_ocr; 1168 break; 1169 case MMCBR_IVAR_MODE: 1170 *(int *)result = sc->aw_host.mode; 1171 break; 1172 case MMCBR_IVAR_OCR: 1173 *(int *)result = sc->aw_host.ocr; 1174 break; 1175 case MMCBR_IVAR_POWER_MODE: 1176 *(int *)result = sc->aw_host.ios.power_mode; 1177 break; 1178 case MMCBR_IVAR_VDD: 1179 *(int *)result = sc->aw_host.ios.vdd; 1180 break; 1181 case MMCBR_IVAR_VCCQ: 1182 *(int *)result = sc->aw_host.ios.vccq; 1183 break; 1184 case MMCBR_IVAR_CAPS: 1185 *(int *)result = sc->aw_host.caps; 1186 break; 1187 case MMCBR_IVAR_TIMING: 1188 *(int *)result = sc->aw_host.ios.timing; 1189 break; 1190 case MMCBR_IVAR_MAX_DATA: 1191 *(int *)result = (sc->aw_mmc_conf->dma_xferlen * 1192 AW_MMC_DMA_SEGS) / MMC_SECTOR_SIZE; 1193 break; 1194 case MMCBR_IVAR_RETUNE_REQ: 1195 *(int *)result = retune_req_none; 1196 break; 1197 } 1198 1199 return (0); 1200 } 1201 1202 static int 1203 aw_mmc_write_ivar(device_t bus, device_t child, int which, 1204 uintptr_t value) 1205 { 1206 struct aw_mmc_softc *sc; 1207 1208 sc = device_get_softc(bus); 1209 switch (which) { 1210 default: 1211 return (EINVAL); 1212 case MMCBR_IVAR_BUS_MODE: 1213 sc->aw_host.ios.bus_mode = value; 1214 break; 1215 case MMCBR_IVAR_BUS_WIDTH: 1216 sc->aw_host.ios.bus_width = value; 1217 break; 1218 case MMCBR_IVAR_CHIP_SELECT: 1219 sc->aw_host.ios.chip_select = value; 1220 break; 1221 case MMCBR_IVAR_CLOCK: 1222 sc->aw_host.ios.clock = value; 1223 break; 1224 case MMCBR_IVAR_MODE: 1225 sc->aw_host.mode = value; 1226 break; 1227 case MMCBR_IVAR_OCR: 1228 sc->aw_host.ocr = value; 1229 break; 1230 case MMCBR_IVAR_POWER_MODE: 1231 sc->aw_host.ios.power_mode = value; 1232 break; 1233 case MMCBR_IVAR_VDD: 1234 sc->aw_host.ios.vdd = value; 1235 break; 1236 case MMCBR_IVAR_VCCQ: 1237 sc->aw_host.ios.vccq = value; 1238 break; 1239 case MMCBR_IVAR_TIMING: 1240 sc->aw_host.ios.timing = value; 1241 break; 1242 /* These are read-only */ 1243 case MMCBR_IVAR_CAPS: 1244 case MMCBR_IVAR_HOST_OCR: 1245 case MMCBR_IVAR_F_MIN: 1246 case MMCBR_IVAR_F_MAX: 1247 case MMCBR_IVAR_MAX_DATA: 1248 return (EINVAL); 1249 } 1250 1251 return (0); 1252 } 1253 1254 static int 1255 aw_mmc_update_clock(struct aw_mmc_softc *sc, uint32_t clkon) 1256 { 1257 uint32_t reg; 1258 int retry; 1259 1260 reg = AW_MMC_READ_4(sc, AW_MMC_CKCR); 1261 reg &= ~(AW_MMC_CKCR_ENB | AW_MMC_CKCR_LOW_POWER | 1262 AW_MMC_CKCR_MASK_DATA0); 1263 1264 if (clkon) 1265 reg |= AW_MMC_CKCR_ENB; 1266 if (sc->aw_mmc_conf->mask_data0) 1267 reg |= AW_MMC_CKCR_MASK_DATA0; 1268 1269 AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg); 1270 1271 reg = AW_MMC_CMDR_LOAD | AW_MMC_CMDR_PRG_CLK | 1272 AW_MMC_CMDR_WAIT_PRE_OVER; 1273 AW_MMC_WRITE_4(sc, AW_MMC_CMDR, reg); 1274 retry = 0xfffff; 1275 1276 while (reg & AW_MMC_CMDR_LOAD && --retry > 0) { 1277 reg = AW_MMC_READ_4(sc, AW_MMC_CMDR); 1278 DELAY(10); 1279 } 1280 AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff); 1281 1282 if (reg & AW_MMC_CMDR_LOAD) { 1283 device_printf(sc->aw_dev, "timeout updating clock\n"); 1284 return (ETIMEDOUT); 1285 } 1286 1287 if (sc->aw_mmc_conf->mask_data0) { 1288 reg = AW_MMC_READ_4(sc, AW_MMC_CKCR); 1289 reg &= ~AW_MMC_CKCR_MASK_DATA0; 1290 AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg); 1291 } 1292 1293 return (0); 1294 } 1295 1296 static int 1297 aw_mmc_switch_vccq(device_t bus, device_t child) 1298 { 1299 struct aw_mmc_softc *sc; 1300 int uvolt, err; 1301 1302 sc = device_get_softc(bus); 1303 1304 if (sc->aw_reg_vqmmc == NULL) 1305 return EOPNOTSUPP; 1306 1307 switch (sc->aw_host.ios.vccq) { 1308 case vccq_180: 1309 uvolt = 1800000; 1310 break; 1311 case vccq_330: 1312 uvolt = 3300000; 1313 break; 1314 default: 1315 return EINVAL; 1316 } 1317 1318 err = regulator_set_voltage(sc->aw_reg_vqmmc, uvolt, uvolt); 1319 if (err != 0) { 1320 device_printf(sc->aw_dev, 1321 "Cannot set vqmmc to %d<->%d\n", 1322 uvolt, 1323 uvolt); 1324 return (err); 1325 } 1326 1327 return (0); 1328 } 1329 1330 static int 1331 aw_mmc_update_ios(device_t bus, device_t child) 1332 { 1333 int error; 1334 struct aw_mmc_softc *sc; 1335 struct mmc_ios *ios; 1336 unsigned int clock; 1337 uint32_t reg, div = 1; 1338 1339 sc = device_get_softc(bus); 1340 1341 ios = &sc->aw_host.ios; 1342 1343 /* Set the bus width. */ 1344 switch (ios->bus_width) { 1345 case bus_width_1: 1346 AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR1); 1347 break; 1348 case bus_width_4: 1349 AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR4); 1350 break; 1351 case bus_width_8: 1352 AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR8); 1353 break; 1354 } 1355 1356 switch (ios->power_mode) { 1357 case power_on: 1358 break; 1359 case power_off: 1360 if (bootverbose) 1361 device_printf(sc->aw_dev, "Powering down sd/mmc\n"); 1362 1363 if (sc->aw_reg_vmmc) 1364 regulator_disable(sc->aw_reg_vmmc); 1365 if (sc->aw_reg_vqmmc) 1366 regulator_disable(sc->aw_reg_vqmmc); 1367 1368 aw_mmc_reset(sc); 1369 break; 1370 case power_up: 1371 if (bootverbose) 1372 device_printf(sc->aw_dev, "Powering up sd/mmc\n"); 1373 1374 if (sc->aw_reg_vmmc) 1375 regulator_enable(sc->aw_reg_vmmc); 1376 if (sc->aw_reg_vqmmc) 1377 regulator_enable(sc->aw_reg_vqmmc); 1378 aw_mmc_init(sc); 1379 break; 1380 }; 1381 1382 /* Enable ddr mode if needed */ 1383 reg = AW_MMC_READ_4(sc, AW_MMC_GCTL); 1384 if (ios->timing == bus_timing_uhs_ddr50 || 1385 ios->timing == bus_timing_mmc_ddr52) 1386 reg |= AW_MMC_GCTL_DDR_MOD_SEL; 1387 else 1388 reg &= ~AW_MMC_GCTL_DDR_MOD_SEL; 1389 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg); 1390 1391 if (ios->clock && ios->clock != sc->aw_clock) { 1392 sc->aw_clock = clock = ios->clock; 1393 1394 /* Disable clock */ 1395 error = aw_mmc_update_clock(sc, 0); 1396 if (error != 0) 1397 return (error); 1398 1399 if (ios->timing == bus_timing_mmc_ddr52 && 1400 (sc->aw_mmc_conf->new_timing || 1401 ios->bus_width == bus_width_8)) { 1402 div = 2; 1403 clock <<= 1; 1404 } 1405 1406 /* Reset the divider. */ 1407 reg = AW_MMC_READ_4(sc, AW_MMC_CKCR); 1408 reg &= ~AW_MMC_CKCR_DIV; 1409 reg |= div - 1; 1410 AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg); 1411 1412 /* New timing mode if needed */ 1413 if (sc->aw_mmc_conf->new_timing) { 1414 reg = AW_MMC_READ_4(sc, AW_MMC_NTSR); 1415 reg |= AW_MMC_NTSR_MODE_SELECT; 1416 AW_MMC_WRITE_4(sc, AW_MMC_NTSR, reg); 1417 } 1418 1419 /* Set the MMC clock. */ 1420 error = clk_disable(sc->aw_clk_mmc); 1421 if (error != 0 && bootverbose) 1422 device_printf(sc->aw_dev, 1423 "failed to disable mmc clock: %d\n", error); 1424 error = clk_set_freq(sc->aw_clk_mmc, clock, 1425 CLK_SET_ROUND_DOWN); 1426 if (error != 0) { 1427 device_printf(sc->aw_dev, 1428 "failed to set frequency to %u Hz: %d\n", 1429 clock, error); 1430 return (error); 1431 } 1432 error = clk_enable(sc->aw_clk_mmc); 1433 if (error != 0 && bootverbose) 1434 device_printf(sc->aw_dev, 1435 "failed to re-enable mmc clock: %d\n", error); 1436 1437 if (sc->aw_mmc_conf->can_calibrate) 1438 AW_MMC_WRITE_4(sc, AW_MMC_SAMP_DL, AW_MMC_SAMP_DL_SW_EN); 1439 1440 /* Enable clock. */ 1441 error = aw_mmc_update_clock(sc, 1); 1442 if (error != 0) 1443 return (error); 1444 } 1445 1446 1447 return (0); 1448 } 1449 1450 static int 1451 aw_mmc_get_ro(device_t bus, device_t child) 1452 { 1453 1454 return (0); 1455 } 1456 1457 static int 1458 aw_mmc_acquire_host(device_t bus, device_t child) 1459 { 1460 struct aw_mmc_softc *sc; 1461 int error; 1462 1463 sc = device_get_softc(bus); 1464 AW_MMC_LOCK(sc); 1465 while (sc->aw_bus_busy) { 1466 error = msleep(sc, &sc->aw_mtx, PCATCH, "mmchw", 0); 1467 if (error != 0) { 1468 AW_MMC_UNLOCK(sc); 1469 return (error); 1470 } 1471 } 1472 sc->aw_bus_busy++; 1473 AW_MMC_UNLOCK(sc); 1474 1475 return (0); 1476 } 1477 1478 static int 1479 aw_mmc_release_host(device_t bus, device_t child) 1480 { 1481 struct aw_mmc_softc *sc; 1482 1483 sc = device_get_softc(bus); 1484 AW_MMC_LOCK(sc); 1485 sc->aw_bus_busy--; 1486 wakeup(sc); 1487 AW_MMC_UNLOCK(sc); 1488 1489 return (0); 1490 } 1491 1492 static device_method_t aw_mmc_methods[] = { 1493 /* Device interface */ 1494 DEVMETHOD(device_probe, aw_mmc_probe), 1495 DEVMETHOD(device_attach, aw_mmc_attach), 1496 DEVMETHOD(device_detach, aw_mmc_detach), 1497 1498 /* Bus interface */ 1499 DEVMETHOD(bus_read_ivar, aw_mmc_read_ivar), 1500 DEVMETHOD(bus_write_ivar, aw_mmc_write_ivar), 1501 DEVMETHOD(bus_add_child, bus_generic_add_child), 1502 1503 /* MMC bridge interface */ 1504 DEVMETHOD(mmcbr_update_ios, aw_mmc_update_ios), 1505 DEVMETHOD(mmcbr_request, aw_mmc_request), 1506 DEVMETHOD(mmcbr_get_ro, aw_mmc_get_ro), 1507 DEVMETHOD(mmcbr_switch_vccq, aw_mmc_switch_vccq), 1508 DEVMETHOD(mmcbr_acquire_host, aw_mmc_acquire_host), 1509 DEVMETHOD(mmcbr_release_host, aw_mmc_release_host), 1510 1511 DEVMETHOD_END 1512 }; 1513 1514 static devclass_t aw_mmc_devclass; 1515 1516 static driver_t aw_mmc_driver = { 1517 "aw_mmc", 1518 aw_mmc_methods, 1519 sizeof(struct aw_mmc_softc), 1520 }; 1521 1522 DRIVER_MODULE(aw_mmc, simplebus, aw_mmc_driver, aw_mmc_devclass, NULL, 1523 NULL); 1524 #ifndef MMCCAM 1525 MMC_DECLARE_BRIDGE(aw_mmc); 1526 #endif 1527