1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org> 5 * Copyright (c) 2013 Alexander Fedorov 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/kernel.h> 37 #include <sys/lock.h> 38 #include <sys/malloc.h> 39 #include <sys/module.h> 40 #include <sys/mutex.h> 41 #include <sys/resource.h> 42 #include <sys/rman.h> 43 #include <sys/sysctl.h> 44 45 #include <machine/bus.h> 46 47 #include <dev/ofw/ofw_bus.h> 48 #include <dev/ofw/ofw_bus_subr.h> 49 50 #include <dev/mmc/bridge.h> 51 #include <dev/mmc/mmcbrvar.h> 52 53 #include <arm/allwinner/aw_mmc.h> 54 #include <dev/extres/clk/clk.h> 55 #include <dev/extres/hwreset/hwreset.h> 56 #include <dev/extres/regulator/regulator.h> 57 58 #include "opt_mmccam.h" 59 60 #ifdef MMCCAM 61 #include <cam/cam.h> 62 #include <cam/cam_ccb.h> 63 #include <cam/cam_debug.h> 64 #include <cam/cam_sim.h> 65 #include <cam/cam_xpt_sim.h> 66 #endif 67 68 #define AW_MMC_MEMRES 0 69 #define AW_MMC_IRQRES 1 70 #define AW_MMC_RESSZ 2 71 #define AW_MMC_DMA_SEGS (PAGE_SIZE / sizeof(struct aw_mmc_dma_desc)) 72 #define AW_MMC_DMA_DESC_SIZE (sizeof(struct aw_mmc_dma_desc) * AW_MMC_DMA_SEGS) 73 #define AW_MMC_DMA_FTRGLEVEL 0x20070008 74 75 #define AW_MMC_RESET_RETRY 1000 76 77 #define CARD_ID_FREQUENCY 400000 78 79 struct aw_mmc_conf { 80 uint32_t dma_xferlen; 81 bool mask_data0; 82 bool can_calibrate; 83 bool new_timing; 84 }; 85 86 static const struct aw_mmc_conf a10_mmc_conf = { 87 .dma_xferlen = 0x2000, 88 }; 89 90 static const struct aw_mmc_conf a13_mmc_conf = { 91 .dma_xferlen = 0x10000, 92 }; 93 94 static const struct aw_mmc_conf a64_mmc_conf = { 95 .dma_xferlen = 0x10000, 96 .mask_data0 = true, 97 .can_calibrate = true, 98 .new_timing = true, 99 }; 100 101 static const struct aw_mmc_conf a64_emmc_conf = { 102 .dma_xferlen = 0x2000, 103 .can_calibrate = true, 104 }; 105 106 static struct ofw_compat_data compat_data[] = { 107 {"allwinner,sun4i-a10-mmc", (uintptr_t)&a10_mmc_conf}, 108 {"allwinner,sun5i-a13-mmc", (uintptr_t)&a13_mmc_conf}, 109 {"allwinner,sun7i-a20-mmc", (uintptr_t)&a13_mmc_conf}, 110 {"allwinner,sun50i-a64-mmc", (uintptr_t)&a64_mmc_conf}, 111 {"allwinner,sun50i-a64-emmc", (uintptr_t)&a64_emmc_conf}, 112 {NULL, 0} 113 }; 114 115 struct aw_mmc_softc { 116 device_t aw_dev; 117 clk_t aw_clk_ahb; 118 clk_t aw_clk_mmc; 119 hwreset_t aw_rst_ahb; 120 int aw_bus_busy; 121 int aw_resid; 122 int aw_timeout; 123 struct callout aw_timeoutc; 124 struct mmc_host aw_host; 125 #ifdef MMCCAM 126 union ccb * ccb; 127 struct cam_devq * devq; 128 struct cam_sim * sim; 129 struct mtx sim_mtx; 130 #else 131 struct mmc_request * aw_req; 132 #endif 133 struct mtx aw_mtx; 134 struct resource * aw_res[AW_MMC_RESSZ]; 135 struct aw_mmc_conf * aw_mmc_conf; 136 uint32_t aw_intr; 137 uint32_t aw_intr_wait; 138 void * aw_intrhand; 139 regulator_t aw_reg_vmmc; 140 regulator_t aw_reg_vqmmc; 141 unsigned int aw_clock; 142 143 /* Fields required for DMA access. */ 144 bus_addr_t aw_dma_desc_phys; 145 bus_dmamap_t aw_dma_map; 146 bus_dma_tag_t aw_dma_tag; 147 void * aw_dma_desc; 148 bus_dmamap_t aw_dma_buf_map; 149 bus_dma_tag_t aw_dma_buf_tag; 150 int aw_dma_map_err; 151 }; 152 153 static struct resource_spec aw_mmc_res_spec[] = { 154 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 155 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 156 { -1, 0, 0 } 157 }; 158 159 static int aw_mmc_probe(device_t); 160 static int aw_mmc_attach(device_t); 161 static int aw_mmc_detach(device_t); 162 static int aw_mmc_setup_dma(struct aw_mmc_softc *); 163 static int aw_mmc_reset(struct aw_mmc_softc *); 164 static int aw_mmc_init(struct aw_mmc_softc *); 165 static void aw_mmc_intr(void *); 166 static int aw_mmc_update_clock(struct aw_mmc_softc *, uint32_t); 167 168 static void aw_mmc_print_error(uint32_t); 169 static int aw_mmc_update_ios(device_t, device_t); 170 static int aw_mmc_request(device_t, device_t, struct mmc_request *); 171 static int aw_mmc_get_ro(device_t, device_t); 172 static int aw_mmc_acquire_host(device_t, device_t); 173 static int aw_mmc_release_host(device_t, device_t); 174 #ifdef MMCCAM 175 static void aw_mmc_cam_action(struct cam_sim *, union ccb *); 176 static void aw_mmc_cam_poll(struct cam_sim *); 177 static int aw_mmc_cam_settran_settings(struct aw_mmc_softc *, union ccb *); 178 static int aw_mmc_cam_request(struct aw_mmc_softc *, union ccb *); 179 static void aw_mmc_cam_handle_mmcio(struct cam_sim *, union ccb *); 180 #endif 181 182 #define AW_MMC_LOCK(_sc) mtx_lock(&(_sc)->aw_mtx) 183 #define AW_MMC_UNLOCK(_sc) mtx_unlock(&(_sc)->aw_mtx) 184 #define AW_MMC_READ_4(_sc, _reg) \ 185 bus_read_4((_sc)->aw_res[AW_MMC_MEMRES], _reg) 186 #define AW_MMC_WRITE_4(_sc, _reg, _value) \ 187 bus_write_4((_sc)->aw_res[AW_MMC_MEMRES], _reg, _value) 188 189 #ifdef MMCCAM 190 static void 191 aw_mmc_cam_handle_mmcio(struct cam_sim *sim, union ccb *ccb) 192 { 193 struct aw_mmc_softc *sc; 194 195 sc = cam_sim_softc(sim); 196 197 aw_mmc_cam_request(sc, ccb); 198 } 199 200 static void 201 aw_mmc_cam_action(struct cam_sim *sim, union ccb *ccb) 202 { 203 struct aw_mmc_softc *sc; 204 205 sc = cam_sim_softc(sim); 206 if (sc == NULL) { 207 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 208 xpt_done(ccb); 209 return; 210 } 211 212 mtx_assert(&sc->sim_mtx, MA_OWNED); 213 214 switch (ccb->ccb_h.func_code) { 215 case XPT_PATH_INQ: 216 { 217 struct ccb_pathinq *cpi; 218 219 cpi = &ccb->cpi; 220 cpi->version_num = 1; 221 cpi->hba_inquiry = 0; 222 cpi->target_sprt = 0; 223 cpi->hba_misc = PIM_NOBUSRESET | PIM_SEQSCAN; 224 cpi->hba_eng_cnt = 0; 225 cpi->max_target = 0; 226 cpi->max_lun = 0; 227 cpi->initiator_id = 1; 228 cpi->maxio = (sc->aw_mmc_conf->dma_xferlen * 229 AW_MMC_DMA_SEGS) / MMC_SECTOR_SIZE; 230 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 231 strncpy(cpi->hba_vid, "Deglitch Networks", HBA_IDLEN); 232 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 233 cpi->unit_number = cam_sim_unit(sim); 234 cpi->bus_id = cam_sim_bus(sim); 235 cpi->protocol = PROTO_MMCSD; 236 cpi->protocol_version = SCSI_REV_0; 237 cpi->transport = XPORT_MMCSD; 238 cpi->transport_version = 1; 239 240 cpi->ccb_h.status = CAM_REQ_CMP; 241 break; 242 } 243 case XPT_GET_TRAN_SETTINGS: 244 { 245 struct ccb_trans_settings *cts = &ccb->cts; 246 247 if (bootverbose) 248 device_printf(sc->aw_dev, "Got XPT_GET_TRAN_SETTINGS\n"); 249 250 cts->protocol = PROTO_MMCSD; 251 cts->protocol_version = 1; 252 cts->transport = XPORT_MMCSD; 253 cts->transport_version = 1; 254 cts->xport_specific.valid = 0; 255 cts->proto_specific.mmc.host_ocr = sc->aw_host.host_ocr; 256 cts->proto_specific.mmc.host_f_min = sc->aw_host.f_min; 257 cts->proto_specific.mmc.host_f_max = sc->aw_host.f_max; 258 cts->proto_specific.mmc.host_caps = sc->aw_host.caps; 259 cts->proto_specific.mmc.host_max_data = (sc->aw_mmc_conf->dma_xferlen * 260 AW_MMC_DMA_SEGS) / MMC_SECTOR_SIZE; 261 memcpy(&cts->proto_specific.mmc.ios, &sc->aw_host.ios, sizeof(struct mmc_ios)); 262 ccb->ccb_h.status = CAM_REQ_CMP; 263 break; 264 } 265 case XPT_SET_TRAN_SETTINGS: 266 { 267 if (bootverbose) 268 device_printf(sc->aw_dev, "Got XPT_SET_TRAN_SETTINGS\n"); 269 aw_mmc_cam_settran_settings(sc, ccb); 270 ccb->ccb_h.status = CAM_REQ_CMP; 271 break; 272 } 273 case XPT_RESET_BUS: 274 if (bootverbose) 275 device_printf(sc->aw_dev, "Got XPT_RESET_BUS, ACK it...\n"); 276 ccb->ccb_h.status = CAM_REQ_CMP; 277 break; 278 case XPT_MMC_IO: 279 /* 280 * Here is the HW-dependent part of 281 * sending the command to the underlying h/w 282 * At some point in the future an interrupt comes. 283 * Then the request will be marked as completed. 284 */ 285 ccb->ccb_h.status = CAM_REQ_INPROG; 286 287 aw_mmc_cam_handle_mmcio(sim, ccb); 288 return; 289 /* NOTREACHED */ 290 break; 291 default: 292 ccb->ccb_h.status = CAM_REQ_INVALID; 293 break; 294 } 295 xpt_done(ccb); 296 return; 297 } 298 299 static void 300 aw_mmc_cam_poll(struct cam_sim *sim) 301 { 302 return; 303 } 304 305 static int 306 aw_mmc_cam_settran_settings(struct aw_mmc_softc *sc, union ccb *ccb) 307 { 308 struct mmc_ios *ios; 309 struct mmc_ios *new_ios; 310 struct ccb_trans_settings_mmc *cts; 311 312 ios = &sc->aw_host.ios; 313 314 cts = &ccb->cts.proto_specific.mmc; 315 new_ios = &cts->ios; 316 317 /* Update only requested fields */ 318 if (cts->ios_valid & MMC_CLK) { 319 ios->clock = new_ios->clock; 320 device_printf(sc->aw_dev, "Clock => %d\n", ios->clock); 321 } 322 if (cts->ios_valid & MMC_VDD) { 323 ios->vdd = new_ios->vdd; 324 device_printf(sc->aw_dev, "VDD => %d\n", ios->vdd); 325 } 326 if (cts->ios_valid & MMC_CS) { 327 ios->chip_select = new_ios->chip_select; 328 device_printf(sc->aw_dev, "CS => %d\n", ios->chip_select); 329 } 330 if (cts->ios_valid & MMC_BW) { 331 ios->bus_width = new_ios->bus_width; 332 device_printf(sc->aw_dev, "Bus width => %d\n", ios->bus_width); 333 } 334 if (cts->ios_valid & MMC_PM) { 335 ios->power_mode = new_ios->power_mode; 336 device_printf(sc->aw_dev, "Power mode => %d\n", ios->power_mode); 337 } 338 if (cts->ios_valid & MMC_BT) { 339 ios->timing = new_ios->timing; 340 device_printf(sc->aw_dev, "Timing => %d\n", ios->timing); 341 } 342 if (cts->ios_valid & MMC_BM) { 343 ios->bus_mode = new_ios->bus_mode; 344 device_printf(sc->aw_dev, "Bus mode => %d\n", ios->bus_mode); 345 } 346 347 return (aw_mmc_update_ios(sc->aw_dev, NULL)); 348 } 349 350 static int 351 aw_mmc_cam_request(struct aw_mmc_softc *sc, union ccb *ccb) 352 { 353 struct ccb_mmcio *mmcio; 354 355 mmcio = &ccb->mmcio; 356 357 AW_MMC_LOCK(sc); 358 359 #ifdef DEBUG 360 if (__predict_false(bootverbose)) { 361 device_printf(sc->aw_dev, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 362 mmcio->cmd.opcode, mmcio->cmd.arg, mmcio->cmd.flags, 363 mmcio->cmd.data != NULL ? (unsigned int) mmcio->cmd.data->len : 0, 364 mmcio->cmd.data != NULL ? mmcio->cmd.data->flags: 0); 365 } 366 #endif 367 if (mmcio->cmd.data != NULL) { 368 if (mmcio->cmd.data->len == 0 || mmcio->cmd.data->flags == 0) 369 panic("data->len = %d, data->flags = %d -- something is b0rked", 370 (int)mmcio->cmd.data->len, mmcio->cmd.data->flags); 371 } 372 if (sc->ccb != NULL) { 373 device_printf(sc->aw_dev, "Controller still has an active command\n"); 374 return (EBUSY); 375 } 376 sc->ccb = ccb; 377 /* aw_mmc_request locks again */ 378 AW_MMC_UNLOCK(sc); 379 aw_mmc_request(sc->aw_dev, NULL, NULL); 380 381 return (0); 382 } 383 #endif /* MMCCAM */ 384 385 static int 386 aw_mmc_probe(device_t dev) 387 { 388 389 if (!ofw_bus_status_okay(dev)) 390 return (ENXIO); 391 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 392 return (ENXIO); 393 394 device_set_desc(dev, "Allwinner Integrated MMC/SD controller"); 395 396 return (BUS_PROBE_DEFAULT); 397 } 398 399 static int 400 aw_mmc_attach(device_t dev) 401 { 402 device_t child; 403 struct aw_mmc_softc *sc; 404 struct sysctl_ctx_list *ctx; 405 struct sysctl_oid_list *tree; 406 uint32_t bus_width, max_freq; 407 phandle_t node; 408 int error; 409 410 node = ofw_bus_get_node(dev); 411 sc = device_get_softc(dev); 412 sc->aw_dev = dev; 413 414 sc->aw_mmc_conf = (struct aw_mmc_conf *)ofw_bus_search_compatible(dev, compat_data)->ocd_data; 415 416 #ifndef MMCCAM 417 sc->aw_req = NULL; 418 #endif 419 if (bus_alloc_resources(dev, aw_mmc_res_spec, sc->aw_res) != 0) { 420 device_printf(dev, "cannot allocate device resources\n"); 421 return (ENXIO); 422 } 423 if (bus_setup_intr(dev, sc->aw_res[AW_MMC_IRQRES], 424 INTR_TYPE_MISC | INTR_MPSAFE, NULL, aw_mmc_intr, sc, 425 &sc->aw_intrhand)) { 426 bus_release_resources(dev, aw_mmc_res_spec, sc->aw_res); 427 device_printf(dev, "cannot setup interrupt handler\n"); 428 return (ENXIO); 429 } 430 mtx_init(&sc->aw_mtx, device_get_nameunit(sc->aw_dev), "aw_mmc", 431 MTX_DEF); 432 callout_init_mtx(&sc->aw_timeoutc, &sc->aw_mtx, 0); 433 434 /* De-assert reset */ 435 if (hwreset_get_by_ofw_name(dev, 0, "ahb", &sc->aw_rst_ahb) == 0) { 436 error = hwreset_deassert(sc->aw_rst_ahb); 437 if (error != 0) { 438 device_printf(dev, "cannot de-assert reset\n"); 439 goto fail; 440 } 441 } 442 443 /* Activate the module clock. */ 444 error = clk_get_by_ofw_name(dev, 0, "ahb", &sc->aw_clk_ahb); 445 if (error != 0) { 446 device_printf(dev, "cannot get ahb clock\n"); 447 goto fail; 448 } 449 error = clk_enable(sc->aw_clk_ahb); 450 if (error != 0) { 451 device_printf(dev, "cannot enable ahb clock\n"); 452 goto fail; 453 } 454 error = clk_get_by_ofw_name(dev, 0, "mmc", &sc->aw_clk_mmc); 455 if (error != 0) { 456 device_printf(dev, "cannot get mmc clock\n"); 457 goto fail; 458 } 459 error = clk_set_freq(sc->aw_clk_mmc, CARD_ID_FREQUENCY, 460 CLK_SET_ROUND_DOWN); 461 if (error != 0) { 462 device_printf(dev, "cannot init mmc clock\n"); 463 goto fail; 464 } 465 error = clk_enable(sc->aw_clk_mmc); 466 if (error != 0) { 467 device_printf(dev, "cannot enable mmc clock\n"); 468 goto fail; 469 } 470 471 sc->aw_timeout = 10; 472 ctx = device_get_sysctl_ctx(dev); 473 tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 474 SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "req_timeout", CTLFLAG_RW, 475 &sc->aw_timeout, 0, "Request timeout in seconds"); 476 477 /* Soft Reset controller. */ 478 if (aw_mmc_reset(sc) != 0) { 479 device_printf(dev, "cannot reset the controller\n"); 480 goto fail; 481 } 482 483 if (aw_mmc_setup_dma(sc) != 0) { 484 device_printf(sc->aw_dev, "Couldn't setup DMA!\n"); 485 goto fail; 486 } 487 488 if (OF_getencprop(node, "bus-width", &bus_width, sizeof(uint32_t)) <= 0) 489 bus_width = 4; 490 491 if (regulator_get_by_ofw_property(dev, 0, "vmmc-supply", 492 &sc->aw_reg_vmmc) == 0) { 493 if (bootverbose) 494 device_printf(dev, "vmmc-supply regulator found\n"); 495 } 496 if (regulator_get_by_ofw_property(dev, 0, "vqmmc-supply", 497 &sc->aw_reg_vqmmc) == 0 && bootverbose) { 498 if (bootverbose) 499 device_printf(dev, "vqmmc-supply regulator found\n"); 500 } 501 502 sc->aw_host.f_min = 400000; 503 504 if (OF_getencprop(node, "max-frequency", &max_freq, 505 sizeof(uint32_t)) <= 0) 506 max_freq = 52000000; 507 sc->aw_host.f_max = max_freq; 508 509 sc->aw_host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340; 510 sc->aw_host.caps = MMC_CAP_HSPEED | MMC_CAP_UHS_SDR12 | 511 MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR50 | 512 MMC_CAP_UHS_DDR50 | MMC_CAP_MMC_DDR52; 513 514 sc->aw_host.caps |= MMC_CAP_SIGNALING_330 | MMC_CAP_SIGNALING_180; 515 516 if (bus_width >= 4) 517 sc->aw_host.caps |= MMC_CAP_4_BIT_DATA; 518 if (bus_width >= 8) 519 sc->aw_host.caps |= MMC_CAP_8_BIT_DATA; 520 521 #ifdef MMCCAM 522 child = NULL; /* Not used by MMCCAM, need to silence compiler warnings */ 523 sc->ccb = NULL; 524 if ((sc->devq = cam_simq_alloc(1)) == NULL) { 525 goto fail; 526 } 527 528 mtx_init(&sc->sim_mtx, "awmmcsim", NULL, MTX_DEF); 529 sc->sim = cam_sim_alloc(aw_mmc_cam_action, aw_mmc_cam_poll, 530 "aw_mmc_sim", sc, device_get_unit(dev), 531 &sc->sim_mtx, 1, 1, sc->devq); 532 533 if (sc->sim == NULL) { 534 cam_simq_free(sc->devq); 535 device_printf(dev, "cannot allocate CAM SIM\n"); 536 goto fail; 537 } 538 539 mtx_lock(&sc->sim_mtx); 540 if (xpt_bus_register(sc->sim, sc->aw_dev, 0) != 0) { 541 device_printf(dev, "cannot register SCSI pass-through bus\n"); 542 cam_sim_free(sc->sim, FALSE); 543 cam_simq_free(sc->devq); 544 mtx_unlock(&sc->sim_mtx); 545 goto fail; 546 } 547 548 mtx_unlock(&sc->sim_mtx); 549 #else /* !MMCCAM */ 550 child = device_add_child(dev, "mmc", -1); 551 if (child == NULL) { 552 device_printf(dev, "attaching MMC bus failed!\n"); 553 goto fail; 554 } 555 if (device_probe_and_attach(child) != 0) { 556 device_printf(dev, "attaching MMC child failed!\n"); 557 device_delete_child(dev, child); 558 goto fail; 559 } 560 #endif /* MMCCAM */ 561 return (0); 562 563 fail: 564 callout_drain(&sc->aw_timeoutc); 565 mtx_destroy(&sc->aw_mtx); 566 bus_teardown_intr(dev, sc->aw_res[AW_MMC_IRQRES], sc->aw_intrhand); 567 bus_release_resources(dev, aw_mmc_res_spec, sc->aw_res); 568 569 #ifdef MMCCAM 570 if (sc->sim != NULL) { 571 mtx_lock(&sc->sim_mtx); 572 xpt_bus_deregister(cam_sim_path(sc->sim)); 573 cam_sim_free(sc->sim, FALSE); 574 mtx_unlock(&sc->sim_mtx); 575 } 576 577 if (sc->devq != NULL) 578 cam_simq_free(sc->devq); 579 #endif 580 return (ENXIO); 581 } 582 583 static int 584 aw_mmc_detach(device_t dev) 585 { 586 587 return (EBUSY); 588 } 589 590 static void 591 aw_dma_desc_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err) 592 { 593 struct aw_mmc_softc *sc; 594 595 sc = (struct aw_mmc_softc *)arg; 596 if (err) { 597 sc->aw_dma_map_err = err; 598 return; 599 } 600 sc->aw_dma_desc_phys = segs[0].ds_addr; 601 } 602 603 static int 604 aw_mmc_setup_dma(struct aw_mmc_softc *sc) 605 { 606 int error; 607 608 /* Allocate the DMA descriptor memory. */ 609 error = bus_dma_tag_create( 610 bus_get_dma_tag(sc->aw_dev), /* parent */ 611 AW_MMC_DMA_ALIGN, 0, /* align, boundary */ 612 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 613 BUS_SPACE_MAXADDR, /* highaddr */ 614 NULL, NULL, /* filter, filterarg*/ 615 AW_MMC_DMA_DESC_SIZE, 1, /* maxsize, nsegment */ 616 AW_MMC_DMA_DESC_SIZE, /* maxsegsize */ 617 0, /* flags */ 618 NULL, NULL, /* lock, lockarg*/ 619 &sc->aw_dma_tag); 620 if (error) 621 return (error); 622 623 error = bus_dmamem_alloc(sc->aw_dma_tag, &sc->aw_dma_desc, 624 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, 625 &sc->aw_dma_map); 626 if (error) 627 return (error); 628 629 error = bus_dmamap_load(sc->aw_dma_tag, 630 sc->aw_dma_map, 631 sc->aw_dma_desc, AW_MMC_DMA_DESC_SIZE, 632 aw_dma_desc_cb, sc, 0); 633 if (error) 634 return (error); 635 if (sc->aw_dma_map_err) 636 return (sc->aw_dma_map_err); 637 638 /* Create the DMA map for data transfers. */ 639 error = bus_dma_tag_create( 640 bus_get_dma_tag(sc->aw_dev), /* parent */ 641 AW_MMC_DMA_ALIGN, 0, /* align, boundary */ 642 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 643 BUS_SPACE_MAXADDR, /* highaddr */ 644 NULL, NULL, /* filter, filterarg*/ 645 sc->aw_mmc_conf->dma_xferlen * 646 AW_MMC_DMA_SEGS, AW_MMC_DMA_SEGS, /* maxsize, nsegments */ 647 sc->aw_mmc_conf->dma_xferlen, /* maxsegsize */ 648 BUS_DMA_ALLOCNOW, /* flags */ 649 NULL, NULL, /* lock, lockarg*/ 650 &sc->aw_dma_buf_tag); 651 if (error) 652 return (error); 653 error = bus_dmamap_create(sc->aw_dma_buf_tag, 0, 654 &sc->aw_dma_buf_map); 655 if (error) 656 return (error); 657 658 return (0); 659 } 660 661 static void 662 aw_dma_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err) 663 { 664 int i; 665 struct aw_mmc_dma_desc *dma_desc; 666 struct aw_mmc_softc *sc; 667 668 sc = (struct aw_mmc_softc *)arg; 669 sc->aw_dma_map_err = err; 670 671 if (err) 672 return; 673 674 dma_desc = sc->aw_dma_desc; 675 for (i = 0; i < nsegs; i++) { 676 if (segs[i].ds_len == sc->aw_mmc_conf->dma_xferlen) 677 dma_desc[i].buf_size = 0; /* Size of 0 indicate max len */ 678 else 679 dma_desc[i].buf_size = segs[i].ds_len; 680 dma_desc[i].buf_addr = segs[i].ds_addr; 681 dma_desc[i].config = AW_MMC_DMA_CONFIG_CH | 682 AW_MMC_DMA_CONFIG_OWN | AW_MMC_DMA_CONFIG_DIC; 683 684 dma_desc[i].next = sc->aw_dma_desc_phys + 685 ((i + 1) * sizeof(struct aw_mmc_dma_desc)); 686 } 687 688 dma_desc[0].config |= AW_MMC_DMA_CONFIG_FD; 689 dma_desc[nsegs - 1].config |= AW_MMC_DMA_CONFIG_LD | 690 AW_MMC_DMA_CONFIG_ER; 691 dma_desc[nsegs - 1].config &= ~AW_MMC_DMA_CONFIG_DIC; 692 dma_desc[nsegs - 1].next = 0; 693 } 694 695 static int 696 aw_mmc_prepare_dma(struct aw_mmc_softc *sc) 697 { 698 bus_dmasync_op_t sync_op; 699 int error; 700 struct mmc_command *cmd; 701 uint32_t val; 702 703 #ifdef MMCCAM 704 cmd = &sc->ccb->mmcio.cmd; 705 #else 706 cmd = sc->aw_req->cmd; 707 #endif 708 if (cmd->data->len > (sc->aw_mmc_conf->dma_xferlen * AW_MMC_DMA_SEGS)) 709 return (EFBIG); 710 error = bus_dmamap_load(sc->aw_dma_buf_tag, sc->aw_dma_buf_map, 711 cmd->data->data, cmd->data->len, aw_dma_cb, sc, 0); 712 if (error) 713 return (error); 714 if (sc->aw_dma_map_err) 715 return (sc->aw_dma_map_err); 716 717 if (cmd->data->flags & MMC_DATA_WRITE) 718 sync_op = BUS_DMASYNC_PREWRITE; 719 else 720 sync_op = BUS_DMASYNC_PREREAD; 721 bus_dmamap_sync(sc->aw_dma_buf_tag, sc->aw_dma_buf_map, sync_op); 722 bus_dmamap_sync(sc->aw_dma_tag, sc->aw_dma_map, BUS_DMASYNC_PREWRITE); 723 724 /* Enable DMA */ 725 val = AW_MMC_READ_4(sc, AW_MMC_GCTL); 726 val &= ~AW_MMC_GCTL_FIFO_AC_MOD; 727 val |= AW_MMC_GCTL_DMA_ENB; 728 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val); 729 730 /* Reset DMA */ 731 val |= AW_MMC_GCTL_DMA_RST; 732 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val); 733 734 AW_MMC_WRITE_4(sc, AW_MMC_DMAC, AW_MMC_DMAC_IDMAC_SOFT_RST); 735 AW_MMC_WRITE_4(sc, AW_MMC_DMAC, 736 AW_MMC_DMAC_IDMAC_IDMA_ON | AW_MMC_DMAC_IDMAC_FIX_BURST); 737 738 /* Enable RX or TX DMA interrupt */ 739 val = AW_MMC_READ_4(sc, AW_MMC_IDIE); 740 if (cmd->data->flags & MMC_DATA_WRITE) 741 val |= AW_MMC_IDST_TX_INT; 742 else 743 val |= AW_MMC_IDST_RX_INT; 744 AW_MMC_WRITE_4(sc, AW_MMC_IDIE, val); 745 746 /* Set DMA descritptor list address */ 747 AW_MMC_WRITE_4(sc, AW_MMC_DLBA, sc->aw_dma_desc_phys); 748 749 /* FIFO trigger level */ 750 AW_MMC_WRITE_4(sc, AW_MMC_FWLR, AW_MMC_DMA_FTRGLEVEL); 751 752 return (0); 753 } 754 755 static int 756 aw_mmc_reset(struct aw_mmc_softc *sc) 757 { 758 uint32_t reg; 759 int timeout; 760 761 reg = AW_MMC_READ_4(sc, AW_MMC_GCTL); 762 reg |= AW_MMC_GCTL_RESET; 763 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg); 764 timeout = AW_MMC_RESET_RETRY; 765 while (--timeout > 0) { 766 if ((AW_MMC_READ_4(sc, AW_MMC_GCTL) & AW_MMC_GCTL_RESET) == 0) 767 break; 768 DELAY(100); 769 } 770 if (timeout == 0) 771 return (ETIMEDOUT); 772 773 return (0); 774 } 775 776 static int 777 aw_mmc_init(struct aw_mmc_softc *sc) 778 { 779 uint32_t reg; 780 int ret; 781 782 ret = aw_mmc_reset(sc); 783 if (ret != 0) 784 return (ret); 785 786 /* Set the timeout. */ 787 AW_MMC_WRITE_4(sc, AW_MMC_TMOR, 788 AW_MMC_TMOR_DTO_LMT_SHIFT(AW_MMC_TMOR_DTO_LMT_MASK) | 789 AW_MMC_TMOR_RTO_LMT_SHIFT(AW_MMC_TMOR_RTO_LMT_MASK)); 790 791 /* Unmask interrupts. */ 792 AW_MMC_WRITE_4(sc, AW_MMC_IMKR, 0); 793 794 /* Clear pending interrupts. */ 795 AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff); 796 797 /* Debug register, undocumented */ 798 AW_MMC_WRITE_4(sc, AW_MMC_DBGC, 0xdeb); 799 800 /* Function select register */ 801 AW_MMC_WRITE_4(sc, AW_MMC_FUNS, 0xceaa0000); 802 803 AW_MMC_WRITE_4(sc, AW_MMC_IDST, 0xffffffff); 804 805 /* Enable interrupts and disable AHB access. */ 806 reg = AW_MMC_READ_4(sc, AW_MMC_GCTL); 807 reg |= AW_MMC_GCTL_INT_ENB; 808 reg &= ~AW_MMC_GCTL_FIFO_AC_MOD; 809 reg &= ~AW_MMC_GCTL_WAIT_MEM_ACCESS; 810 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg); 811 812 return (0); 813 } 814 815 static void 816 aw_mmc_req_done(struct aw_mmc_softc *sc) 817 { 818 struct mmc_command *cmd; 819 #ifdef MMCCAM 820 union ccb *ccb; 821 #else 822 struct mmc_request *req; 823 #endif 824 uint32_t val, mask; 825 int retry; 826 827 #ifdef MMCCAM 828 ccb = sc->ccb; 829 cmd = &ccb->mmcio.cmd; 830 #else 831 cmd = sc->aw_req->cmd; 832 #endif 833 #ifdef DEBUG 834 if (bootverbose) { 835 device_printf(sc->aw_dev, "%s: cmd %d err %d\n", __func__, cmd->opcode, cmd->error); 836 } 837 #endif 838 if (cmd->error != MMC_ERR_NONE) { 839 /* Reset the FIFO and DMA engines. */ 840 mask = AW_MMC_GCTL_FIFO_RST | AW_MMC_GCTL_DMA_RST; 841 val = AW_MMC_READ_4(sc, AW_MMC_GCTL); 842 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val | mask); 843 844 retry = AW_MMC_RESET_RETRY; 845 while (--retry > 0) { 846 if ((AW_MMC_READ_4(sc, AW_MMC_GCTL) & 847 AW_MMC_GCTL_RESET) == 0) 848 break; 849 DELAY(100); 850 } 851 if (retry == 0) 852 device_printf(sc->aw_dev, 853 "timeout resetting DMA/FIFO\n"); 854 aw_mmc_update_clock(sc, 1); 855 } 856 857 callout_stop(&sc->aw_timeoutc); 858 sc->aw_intr = 0; 859 sc->aw_resid = 0; 860 sc->aw_dma_map_err = 0; 861 sc->aw_intr_wait = 0; 862 #ifdef MMCCAM 863 sc->ccb = NULL; 864 ccb->ccb_h.status = 865 (ccb->mmcio.cmd.error == 0 ? CAM_REQ_CMP : CAM_REQ_CMP_ERR); 866 xpt_done(ccb); 867 #else 868 req = sc->aw_req; 869 sc->aw_req = NULL; 870 req->done(req); 871 #endif 872 } 873 874 static void 875 aw_mmc_req_ok(struct aw_mmc_softc *sc) 876 { 877 int timeout; 878 struct mmc_command *cmd; 879 uint32_t status; 880 881 timeout = 1000; 882 while (--timeout > 0) { 883 status = AW_MMC_READ_4(sc, AW_MMC_STAR); 884 if ((status & AW_MMC_STAR_CARD_BUSY) == 0) 885 break; 886 DELAY(1000); 887 } 888 #ifdef MMCCAM 889 cmd = &sc->ccb->mmcio.cmd; 890 #else 891 cmd = sc->aw_req->cmd; 892 #endif 893 if (timeout == 0) { 894 cmd->error = MMC_ERR_FAILED; 895 aw_mmc_req_done(sc); 896 return; 897 } 898 if (cmd->flags & MMC_RSP_PRESENT) { 899 if (cmd->flags & MMC_RSP_136) { 900 cmd->resp[0] = AW_MMC_READ_4(sc, AW_MMC_RESP3); 901 cmd->resp[1] = AW_MMC_READ_4(sc, AW_MMC_RESP2); 902 cmd->resp[2] = AW_MMC_READ_4(sc, AW_MMC_RESP1); 903 cmd->resp[3] = AW_MMC_READ_4(sc, AW_MMC_RESP0); 904 } else 905 cmd->resp[0] = AW_MMC_READ_4(sc, AW_MMC_RESP0); 906 } 907 /* All data has been transferred ? */ 908 if (cmd->data != NULL && (sc->aw_resid << 2) < cmd->data->len) 909 cmd->error = MMC_ERR_FAILED; 910 aw_mmc_req_done(sc); 911 } 912 913 914 static inline void 915 set_mmc_error(struct aw_mmc_softc *sc, int error_code) 916 { 917 #ifdef MMCCAM 918 sc->ccb->mmcio.cmd.error = error_code; 919 #else 920 sc->aw_req->cmd->error = error_code; 921 #endif 922 } 923 924 static void 925 aw_mmc_timeout(void *arg) 926 { 927 struct aw_mmc_softc *sc; 928 929 sc = (struct aw_mmc_softc *)arg; 930 #ifdef MMCCAM 931 if (sc->ccb != NULL) { 932 #else 933 if (sc->aw_req != NULL) { 934 #endif 935 device_printf(sc->aw_dev, "controller timeout\n"); 936 set_mmc_error(sc, MMC_ERR_TIMEOUT); 937 aw_mmc_req_done(sc); 938 } else 939 device_printf(sc->aw_dev, 940 "Spurious timeout - no active request\n"); 941 } 942 943 static void 944 aw_mmc_print_error(uint32_t err) 945 { 946 if(err & AW_MMC_INT_RESP_ERR) 947 printf("AW_MMC_INT_RESP_ERR "); 948 if (err & AW_MMC_INT_RESP_CRC_ERR) 949 printf("AW_MMC_INT_RESP_CRC_ERR "); 950 if (err & AW_MMC_INT_DATA_CRC_ERR) 951 printf("AW_MMC_INT_DATA_CRC_ERR "); 952 if (err & AW_MMC_INT_RESP_TIMEOUT) 953 printf("AW_MMC_INT_RESP_TIMEOUT "); 954 if (err & AW_MMC_INT_FIFO_RUN_ERR) 955 printf("AW_MMC_INT_FIFO_RUN_ERR "); 956 if (err & AW_MMC_INT_CMD_BUSY) 957 printf("AW_MMC_INT_CMD_BUSY "); 958 if (err & AW_MMC_INT_DATA_START_ERR) 959 printf("AW_MMC_INT_DATA_START_ERR "); 960 if (err & AW_MMC_INT_DATA_END_BIT_ERR) 961 printf("AW_MMC_INT_DATA_END_BIT_ERR"); 962 printf("\n"); 963 } 964 965 static void 966 aw_mmc_intr(void *arg) 967 { 968 bus_dmasync_op_t sync_op; 969 struct aw_mmc_softc *sc; 970 struct mmc_data *data; 971 uint32_t idst, imask, rint; 972 973 sc = (struct aw_mmc_softc *)arg; 974 AW_MMC_LOCK(sc); 975 rint = AW_MMC_READ_4(sc, AW_MMC_RISR); 976 idst = AW_MMC_READ_4(sc, AW_MMC_IDST); 977 imask = AW_MMC_READ_4(sc, AW_MMC_IMKR); 978 if (idst == 0 && imask == 0 && rint == 0) { 979 AW_MMC_UNLOCK(sc); 980 return; 981 } 982 #ifdef DEBUG 983 device_printf(sc->aw_dev, "idst: %#x, imask: %#x, rint: %#x\n", 984 idst, imask, rint); 985 #endif 986 #ifdef MMCCAM 987 if (sc->ccb == NULL) { 988 #else 989 if (sc->aw_req == NULL) { 990 #endif 991 device_printf(sc->aw_dev, 992 "Spurious interrupt - no active request, rint: 0x%08X\n", 993 rint); 994 aw_mmc_print_error(rint); 995 goto end; 996 } 997 if (rint & AW_MMC_INT_ERR_BIT) { 998 if (bootverbose) 999 device_printf(sc->aw_dev, "error rint: 0x%08X\n", rint); 1000 aw_mmc_print_error(rint); 1001 if (rint & AW_MMC_INT_RESP_TIMEOUT) 1002 set_mmc_error(sc, MMC_ERR_TIMEOUT); 1003 else 1004 set_mmc_error(sc, MMC_ERR_FAILED); 1005 aw_mmc_req_done(sc); 1006 goto end; 1007 } 1008 if (idst & AW_MMC_IDST_ERROR) { 1009 device_printf(sc->aw_dev, "error idst: 0x%08x\n", idst); 1010 set_mmc_error(sc, MMC_ERR_FAILED); 1011 aw_mmc_req_done(sc); 1012 goto end; 1013 } 1014 1015 sc->aw_intr |= rint; 1016 #ifdef MMCCAM 1017 data = sc->ccb->mmcio.cmd.data; 1018 #else 1019 data = sc->aw_req->cmd->data; 1020 #endif 1021 if (data != NULL && (idst & AW_MMC_IDST_COMPLETE) != 0) { 1022 if (data->flags & MMC_DATA_WRITE) 1023 sync_op = BUS_DMASYNC_POSTWRITE; 1024 else 1025 sync_op = BUS_DMASYNC_POSTREAD; 1026 bus_dmamap_sync(sc->aw_dma_buf_tag, sc->aw_dma_buf_map, 1027 sync_op); 1028 bus_dmamap_sync(sc->aw_dma_tag, sc->aw_dma_map, 1029 BUS_DMASYNC_POSTWRITE); 1030 bus_dmamap_unload(sc->aw_dma_buf_tag, sc->aw_dma_buf_map); 1031 sc->aw_resid = data->len >> 2; 1032 } 1033 if ((sc->aw_intr & sc->aw_intr_wait) == sc->aw_intr_wait) 1034 aw_mmc_req_ok(sc); 1035 1036 end: 1037 AW_MMC_WRITE_4(sc, AW_MMC_IDST, idst); 1038 AW_MMC_WRITE_4(sc, AW_MMC_RISR, rint); 1039 AW_MMC_UNLOCK(sc); 1040 } 1041 1042 static int 1043 aw_mmc_request(device_t bus, device_t child, struct mmc_request *req) 1044 { 1045 int blksz; 1046 struct aw_mmc_softc *sc; 1047 struct mmc_command *cmd; 1048 uint32_t cmdreg, imask; 1049 int err; 1050 1051 sc = device_get_softc(bus); 1052 1053 AW_MMC_LOCK(sc); 1054 #ifdef MMCCAM 1055 KASSERT(req == NULL, ("req should be NULL in MMCCAM case!")); 1056 /* 1057 * For MMCCAM, sc->ccb has been NULL-checked and populated 1058 * by aw_mmc_cam_request() already. 1059 */ 1060 cmd = &sc->ccb->mmcio.cmd; 1061 #else 1062 if (sc->aw_req) { 1063 AW_MMC_UNLOCK(sc); 1064 return (EBUSY); 1065 } 1066 sc->aw_req = req; 1067 cmd = req->cmd; 1068 1069 #ifdef DEBUG 1070 if (bootverbose) 1071 device_printf(sc->aw_dev, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 1072 cmd->opcode, cmd->arg, cmd->flags, 1073 cmd->data != NULL ? (unsigned int)cmd->data->len : 0, 1074 cmd->data != NULL ? cmd->data->flags: 0); 1075 #endif 1076 #endif 1077 cmdreg = AW_MMC_CMDR_LOAD; 1078 imask = AW_MMC_INT_ERR_BIT; 1079 sc->aw_intr_wait = 0; 1080 sc->aw_intr = 0; 1081 sc->aw_resid = 0; 1082 cmd->error = MMC_ERR_NONE; 1083 1084 if (cmd->opcode == MMC_GO_IDLE_STATE) 1085 cmdreg |= AW_MMC_CMDR_SEND_INIT_SEQ; 1086 1087 if (cmd->flags & MMC_RSP_PRESENT) 1088 cmdreg |= AW_MMC_CMDR_RESP_RCV; 1089 if (cmd->flags & MMC_RSP_136) 1090 cmdreg |= AW_MMC_CMDR_LONG_RESP; 1091 if (cmd->flags & MMC_RSP_CRC) 1092 cmdreg |= AW_MMC_CMDR_CHK_RESP_CRC; 1093 1094 if (cmd->data) { 1095 cmdreg |= AW_MMC_CMDR_DATA_TRANS | AW_MMC_CMDR_WAIT_PRE_OVER; 1096 1097 if (cmd->data->flags & MMC_DATA_MULTI) { 1098 cmdreg |= AW_MMC_CMDR_STOP_CMD_FLAG; 1099 imask |= AW_MMC_INT_AUTO_STOP_DONE; 1100 sc->aw_intr_wait |= AW_MMC_INT_AUTO_STOP_DONE; 1101 } else { 1102 sc->aw_intr_wait |= AW_MMC_INT_DATA_OVER; 1103 imask |= AW_MMC_INT_DATA_OVER; 1104 } 1105 if (cmd->data->flags & MMC_DATA_WRITE) 1106 cmdreg |= AW_MMC_CMDR_DIR_WRITE; 1107 #ifdef MMCCAM 1108 if (cmd->data->flags & MMC_DATA_BLOCK_SIZE) { 1109 AW_MMC_WRITE_4(sc, AW_MMC_BKSR, cmd->data->block_size); 1110 AW_MMC_WRITE_4(sc, AW_MMC_BYCR, cmd->data->len); 1111 } else 1112 #endif 1113 { 1114 blksz = min(cmd->data->len, MMC_SECTOR_SIZE); 1115 AW_MMC_WRITE_4(sc, AW_MMC_BKSR, blksz); 1116 AW_MMC_WRITE_4(sc, AW_MMC_BYCR, cmd->data->len); 1117 } 1118 } else { 1119 imask |= AW_MMC_INT_CMD_DONE; 1120 } 1121 1122 /* Enable the interrupts we are interested in */ 1123 AW_MMC_WRITE_4(sc, AW_MMC_IMKR, imask); 1124 AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff); 1125 1126 /* Enable auto stop if needed */ 1127 AW_MMC_WRITE_4(sc, AW_MMC_A12A, 1128 cmdreg & AW_MMC_CMDR_STOP_CMD_FLAG ? 0 : 0xffff); 1129 1130 /* Write the command argument */ 1131 AW_MMC_WRITE_4(sc, AW_MMC_CAGR, cmd->arg); 1132 1133 /* 1134 * If we don't have data start the request 1135 * if we do prepare the dma request and start the request 1136 */ 1137 if (cmd->data == NULL) { 1138 AW_MMC_WRITE_4(sc, AW_MMC_CMDR, cmdreg | cmd->opcode); 1139 } else { 1140 err = aw_mmc_prepare_dma(sc); 1141 if (err != 0) 1142 device_printf(sc->aw_dev, "prepare_dma failed: %d\n", err); 1143 1144 AW_MMC_WRITE_4(sc, AW_MMC_CMDR, cmdreg | cmd->opcode); 1145 } 1146 1147 callout_reset(&sc->aw_timeoutc, sc->aw_timeout * hz, 1148 aw_mmc_timeout, sc); 1149 AW_MMC_UNLOCK(sc); 1150 1151 return (0); 1152 } 1153 1154 static int 1155 aw_mmc_read_ivar(device_t bus, device_t child, int which, 1156 uintptr_t *result) 1157 { 1158 struct aw_mmc_softc *sc; 1159 1160 sc = device_get_softc(bus); 1161 switch (which) { 1162 default: 1163 return (EINVAL); 1164 case MMCBR_IVAR_BUS_MODE: 1165 *(int *)result = sc->aw_host.ios.bus_mode; 1166 break; 1167 case MMCBR_IVAR_BUS_WIDTH: 1168 *(int *)result = sc->aw_host.ios.bus_width; 1169 break; 1170 case MMCBR_IVAR_CHIP_SELECT: 1171 *(int *)result = sc->aw_host.ios.chip_select; 1172 break; 1173 case MMCBR_IVAR_CLOCK: 1174 *(int *)result = sc->aw_host.ios.clock; 1175 break; 1176 case MMCBR_IVAR_F_MIN: 1177 *(int *)result = sc->aw_host.f_min; 1178 break; 1179 case MMCBR_IVAR_F_MAX: 1180 *(int *)result = sc->aw_host.f_max; 1181 break; 1182 case MMCBR_IVAR_HOST_OCR: 1183 *(int *)result = sc->aw_host.host_ocr; 1184 break; 1185 case MMCBR_IVAR_MODE: 1186 *(int *)result = sc->aw_host.mode; 1187 break; 1188 case MMCBR_IVAR_OCR: 1189 *(int *)result = sc->aw_host.ocr; 1190 break; 1191 case MMCBR_IVAR_POWER_MODE: 1192 *(int *)result = sc->aw_host.ios.power_mode; 1193 break; 1194 case MMCBR_IVAR_VDD: 1195 *(int *)result = sc->aw_host.ios.vdd; 1196 break; 1197 case MMCBR_IVAR_VCCQ: 1198 *(int *)result = sc->aw_host.ios.vccq; 1199 break; 1200 case MMCBR_IVAR_CAPS: 1201 *(int *)result = sc->aw_host.caps; 1202 break; 1203 case MMCBR_IVAR_TIMING: 1204 *(int *)result = sc->aw_host.ios.timing; 1205 break; 1206 case MMCBR_IVAR_MAX_DATA: 1207 *(int *)result = (sc->aw_mmc_conf->dma_xferlen * 1208 AW_MMC_DMA_SEGS) / MMC_SECTOR_SIZE; 1209 break; 1210 case MMCBR_IVAR_RETUNE_REQ: 1211 *(int *)result = retune_req_none; 1212 break; 1213 } 1214 1215 return (0); 1216 } 1217 1218 static int 1219 aw_mmc_write_ivar(device_t bus, device_t child, int which, 1220 uintptr_t value) 1221 { 1222 struct aw_mmc_softc *sc; 1223 1224 sc = device_get_softc(bus); 1225 switch (which) { 1226 default: 1227 return (EINVAL); 1228 case MMCBR_IVAR_BUS_MODE: 1229 sc->aw_host.ios.bus_mode = value; 1230 break; 1231 case MMCBR_IVAR_BUS_WIDTH: 1232 sc->aw_host.ios.bus_width = value; 1233 break; 1234 case MMCBR_IVAR_CHIP_SELECT: 1235 sc->aw_host.ios.chip_select = value; 1236 break; 1237 case MMCBR_IVAR_CLOCK: 1238 sc->aw_host.ios.clock = value; 1239 break; 1240 case MMCBR_IVAR_MODE: 1241 sc->aw_host.mode = value; 1242 break; 1243 case MMCBR_IVAR_OCR: 1244 sc->aw_host.ocr = value; 1245 break; 1246 case MMCBR_IVAR_POWER_MODE: 1247 sc->aw_host.ios.power_mode = value; 1248 break; 1249 case MMCBR_IVAR_VDD: 1250 sc->aw_host.ios.vdd = value; 1251 break; 1252 case MMCBR_IVAR_VCCQ: 1253 sc->aw_host.ios.vccq = value; 1254 break; 1255 case MMCBR_IVAR_TIMING: 1256 sc->aw_host.ios.timing = value; 1257 break; 1258 /* These are read-only */ 1259 case MMCBR_IVAR_CAPS: 1260 case MMCBR_IVAR_HOST_OCR: 1261 case MMCBR_IVAR_F_MIN: 1262 case MMCBR_IVAR_F_MAX: 1263 case MMCBR_IVAR_MAX_DATA: 1264 return (EINVAL); 1265 } 1266 1267 return (0); 1268 } 1269 1270 static int 1271 aw_mmc_update_clock(struct aw_mmc_softc *sc, uint32_t clkon) 1272 { 1273 uint32_t reg; 1274 int retry; 1275 1276 reg = AW_MMC_READ_4(sc, AW_MMC_CKCR); 1277 reg &= ~(AW_MMC_CKCR_ENB | AW_MMC_CKCR_LOW_POWER | 1278 AW_MMC_CKCR_MASK_DATA0); 1279 1280 if (clkon) 1281 reg |= AW_MMC_CKCR_ENB; 1282 if (sc->aw_mmc_conf->mask_data0) 1283 reg |= AW_MMC_CKCR_MASK_DATA0; 1284 1285 AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg); 1286 1287 reg = AW_MMC_CMDR_LOAD | AW_MMC_CMDR_PRG_CLK | 1288 AW_MMC_CMDR_WAIT_PRE_OVER; 1289 AW_MMC_WRITE_4(sc, AW_MMC_CMDR, reg); 1290 retry = 0xfffff; 1291 1292 while (reg & AW_MMC_CMDR_LOAD && --retry > 0) { 1293 reg = AW_MMC_READ_4(sc, AW_MMC_CMDR); 1294 DELAY(10); 1295 } 1296 AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff); 1297 1298 if (reg & AW_MMC_CMDR_LOAD) { 1299 device_printf(sc->aw_dev, "timeout updating clock\n"); 1300 return (ETIMEDOUT); 1301 } 1302 1303 if (sc->aw_mmc_conf->mask_data0) { 1304 reg = AW_MMC_READ_4(sc, AW_MMC_CKCR); 1305 reg &= ~AW_MMC_CKCR_MASK_DATA0; 1306 AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg); 1307 } 1308 1309 return (0); 1310 } 1311 1312 static int 1313 aw_mmc_switch_vccq(device_t bus, device_t child) 1314 { 1315 struct aw_mmc_softc *sc; 1316 int uvolt, err; 1317 1318 sc = device_get_softc(bus); 1319 1320 if (sc->aw_reg_vqmmc == NULL) 1321 return EOPNOTSUPP; 1322 1323 switch (sc->aw_host.ios.vccq) { 1324 case vccq_180: 1325 uvolt = 1800000; 1326 break; 1327 case vccq_330: 1328 uvolt = 3300000; 1329 break; 1330 default: 1331 return EINVAL; 1332 } 1333 1334 err = regulator_set_voltage(sc->aw_reg_vqmmc, uvolt, uvolt); 1335 if (err != 0) { 1336 device_printf(sc->aw_dev, 1337 "Cannot set vqmmc to %d<->%d\n", 1338 uvolt, 1339 uvolt); 1340 return (err); 1341 } 1342 1343 return (0); 1344 } 1345 1346 static int 1347 aw_mmc_update_ios(device_t bus, device_t child) 1348 { 1349 int error; 1350 struct aw_mmc_softc *sc; 1351 struct mmc_ios *ios; 1352 unsigned int clock; 1353 uint32_t reg, div = 1; 1354 1355 sc = device_get_softc(bus); 1356 1357 ios = &sc->aw_host.ios; 1358 1359 /* Set the bus width. */ 1360 switch (ios->bus_width) { 1361 case bus_width_1: 1362 AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR1); 1363 break; 1364 case bus_width_4: 1365 AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR4); 1366 break; 1367 case bus_width_8: 1368 AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR8); 1369 break; 1370 } 1371 1372 switch (ios->power_mode) { 1373 case power_on: 1374 break; 1375 case power_off: 1376 if (bootverbose) 1377 device_printf(sc->aw_dev, "Powering down sd/mmc\n"); 1378 1379 if (sc->aw_reg_vmmc) 1380 regulator_disable(sc->aw_reg_vmmc); 1381 if (sc->aw_reg_vqmmc) 1382 regulator_disable(sc->aw_reg_vqmmc); 1383 1384 aw_mmc_reset(sc); 1385 break; 1386 case power_up: 1387 if (bootverbose) 1388 device_printf(sc->aw_dev, "Powering up sd/mmc\n"); 1389 1390 if (sc->aw_reg_vmmc) 1391 regulator_enable(sc->aw_reg_vmmc); 1392 if (sc->aw_reg_vqmmc) 1393 regulator_enable(sc->aw_reg_vqmmc); 1394 aw_mmc_init(sc); 1395 break; 1396 }; 1397 1398 /* Enable ddr mode if needed */ 1399 reg = AW_MMC_READ_4(sc, AW_MMC_GCTL); 1400 if (ios->timing == bus_timing_uhs_ddr50 || 1401 ios->timing == bus_timing_mmc_ddr52) 1402 reg |= AW_MMC_GCTL_DDR_MOD_SEL; 1403 else 1404 reg &= ~AW_MMC_GCTL_DDR_MOD_SEL; 1405 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg); 1406 1407 if (ios->clock && ios->clock != sc->aw_clock) { 1408 sc->aw_clock = clock = ios->clock; 1409 1410 /* Disable clock */ 1411 error = aw_mmc_update_clock(sc, 0); 1412 if (error != 0) 1413 return (error); 1414 1415 if (ios->timing == bus_timing_mmc_ddr52 && 1416 (sc->aw_mmc_conf->new_timing || 1417 ios->bus_width == bus_width_8)) { 1418 div = 2; 1419 clock <<= 1; 1420 } 1421 1422 /* Reset the divider. */ 1423 reg = AW_MMC_READ_4(sc, AW_MMC_CKCR); 1424 reg &= ~AW_MMC_CKCR_DIV; 1425 reg |= div - 1; 1426 AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg); 1427 1428 /* New timing mode if needed */ 1429 if (sc->aw_mmc_conf->new_timing) { 1430 reg = AW_MMC_READ_4(sc, AW_MMC_NTSR); 1431 reg |= AW_MMC_NTSR_MODE_SELECT; 1432 AW_MMC_WRITE_4(sc, AW_MMC_NTSR, reg); 1433 } 1434 1435 /* Set the MMC clock. */ 1436 error = clk_set_freq(sc->aw_clk_mmc, clock, 1437 CLK_SET_ROUND_DOWN); 1438 if (error != 0) { 1439 device_printf(sc->aw_dev, 1440 "failed to set frequency to %u Hz: %d\n", 1441 clock, error); 1442 return (error); 1443 } 1444 1445 if (sc->aw_mmc_conf->can_calibrate) 1446 AW_MMC_WRITE_4(sc, AW_MMC_SAMP_DL, AW_MMC_SAMP_DL_SW_EN); 1447 1448 /* Enable clock. */ 1449 error = aw_mmc_update_clock(sc, 1); 1450 if (error != 0) 1451 return (error); 1452 } 1453 1454 1455 return (0); 1456 } 1457 1458 static int 1459 aw_mmc_get_ro(device_t bus, device_t child) 1460 { 1461 1462 return (0); 1463 } 1464 1465 static int 1466 aw_mmc_acquire_host(device_t bus, device_t child) 1467 { 1468 struct aw_mmc_softc *sc; 1469 int error; 1470 1471 sc = device_get_softc(bus); 1472 AW_MMC_LOCK(sc); 1473 while (sc->aw_bus_busy) { 1474 error = msleep(sc, &sc->aw_mtx, PCATCH, "mmchw", 0); 1475 if (error != 0) { 1476 AW_MMC_UNLOCK(sc); 1477 return (error); 1478 } 1479 } 1480 sc->aw_bus_busy++; 1481 AW_MMC_UNLOCK(sc); 1482 1483 return (0); 1484 } 1485 1486 static int 1487 aw_mmc_release_host(device_t bus, device_t child) 1488 { 1489 struct aw_mmc_softc *sc; 1490 1491 sc = device_get_softc(bus); 1492 AW_MMC_LOCK(sc); 1493 sc->aw_bus_busy--; 1494 wakeup(sc); 1495 AW_MMC_UNLOCK(sc); 1496 1497 return (0); 1498 } 1499 1500 static device_method_t aw_mmc_methods[] = { 1501 /* Device interface */ 1502 DEVMETHOD(device_probe, aw_mmc_probe), 1503 DEVMETHOD(device_attach, aw_mmc_attach), 1504 DEVMETHOD(device_detach, aw_mmc_detach), 1505 1506 /* Bus interface */ 1507 DEVMETHOD(bus_read_ivar, aw_mmc_read_ivar), 1508 DEVMETHOD(bus_write_ivar, aw_mmc_write_ivar), 1509 1510 /* MMC bridge interface */ 1511 DEVMETHOD(mmcbr_update_ios, aw_mmc_update_ios), 1512 DEVMETHOD(mmcbr_request, aw_mmc_request), 1513 DEVMETHOD(mmcbr_get_ro, aw_mmc_get_ro), 1514 DEVMETHOD(mmcbr_switch_vccq, aw_mmc_switch_vccq), 1515 DEVMETHOD(mmcbr_acquire_host, aw_mmc_acquire_host), 1516 DEVMETHOD(mmcbr_release_host, aw_mmc_release_host), 1517 1518 DEVMETHOD_END 1519 }; 1520 1521 static devclass_t aw_mmc_devclass; 1522 1523 static driver_t aw_mmc_driver = { 1524 "aw_mmc", 1525 aw_mmc_methods, 1526 sizeof(struct aw_mmc_softc), 1527 }; 1528 1529 DRIVER_MODULE(aw_mmc, simplebus, aw_mmc_driver, aw_mmc_devclass, NULL, 1530 NULL); 1531 #ifndef MMCCAM 1532 MMC_DECLARE_BRIDGE(aw_mmc); 1533 #endif 1534