1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org> 5 * Copyright (c) 2013 Alexander Fedorov 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 #include <sys/conf.h> 35 #include <sys/kernel.h> 36 #include <sys/lock.h> 37 #include <sys/malloc.h> 38 #include <sys/module.h> 39 #include <sys/mutex.h> 40 #include <sys/resource.h> 41 #include <sys/rman.h> 42 #include <sys/sysctl.h> 43 #include <sys/queue.h> 44 #include <sys/taskqueue.h> 45 46 #include <machine/bus.h> 47 48 #include <dev/ofw/ofw_bus.h> 49 #include <dev/ofw/ofw_bus_subr.h> 50 51 #include <dev/mmc/bridge.h> 52 #include <dev/mmc/mmcbrvar.h> 53 #include <dev/mmc/mmc_fdt_helpers.h> 54 55 #include <arm/allwinner/aw_mmc.h> 56 #include <dev/extres/clk/clk.h> 57 #include <dev/extres/hwreset/hwreset.h> 58 #include <dev/extres/regulator/regulator.h> 59 60 #include "opt_mmccam.h" 61 62 #ifdef MMCCAM 63 #include <cam/cam.h> 64 #include <cam/cam_ccb.h> 65 #include <cam/cam_debug.h> 66 #include <cam/cam_sim.h> 67 #include <cam/cam_xpt_sim.h> 68 #include <cam/mmc/mmc_sim.h> 69 70 #include "mmc_sim_if.h" 71 #endif 72 73 #include "mmc_pwrseq_if.h" 74 75 #define AW_MMC_MEMRES 0 76 #define AW_MMC_IRQRES 1 77 #define AW_MMC_RESSZ 2 78 #define AW_MMC_DMA_SEGS (PAGE_SIZE / sizeof(struct aw_mmc_dma_desc)) 79 #define AW_MMC_DMA_DESC_SIZE (sizeof(struct aw_mmc_dma_desc) * AW_MMC_DMA_SEGS) 80 #define AW_MMC_DMA_FTRGLEVEL 0x20070008 81 82 #define AW_MMC_RESET_RETRY 1000 83 84 #define CARD_ID_FREQUENCY 400000 85 86 struct aw_mmc_conf { 87 uint32_t dma_xferlen; 88 bool mask_data0; 89 bool can_calibrate; 90 bool new_timing; 91 }; 92 93 static const struct aw_mmc_conf a10_mmc_conf = { 94 .dma_xferlen = 0x2000, 95 }; 96 97 static const struct aw_mmc_conf a13_mmc_conf = { 98 .dma_xferlen = 0x10000, 99 }; 100 101 static const struct aw_mmc_conf a64_mmc_conf = { 102 .dma_xferlen = 0x10000, 103 .mask_data0 = true, 104 .can_calibrate = true, 105 .new_timing = true, 106 }; 107 108 static const struct aw_mmc_conf a64_emmc_conf = { 109 .dma_xferlen = 0x2000, 110 .can_calibrate = true, 111 }; 112 113 static struct ofw_compat_data compat_data[] = { 114 {"allwinner,sun4i-a10-mmc", (uintptr_t)&a10_mmc_conf}, 115 {"allwinner,sun5i-a13-mmc", (uintptr_t)&a13_mmc_conf}, 116 {"allwinner,sun7i-a20-mmc", (uintptr_t)&a13_mmc_conf}, 117 {"allwinner,sun50i-a64-mmc", (uintptr_t)&a64_mmc_conf}, 118 {"allwinner,sun50i-a64-emmc", (uintptr_t)&a64_emmc_conf}, 119 {NULL, 0} 120 }; 121 122 struct aw_mmc_softc { 123 device_t aw_dev; 124 clk_t aw_clk_ahb; 125 clk_t aw_clk_mmc; 126 hwreset_t aw_rst_ahb; 127 int aw_bus_busy; 128 int aw_resid; 129 int aw_timeout; 130 struct callout aw_timeoutc; 131 struct mmc_host aw_host; 132 struct mmc_helper mmc_helper; 133 #ifdef MMCCAM 134 union ccb * ccb; 135 struct mmc_sim mmc_sim; 136 #else 137 struct mmc_request * aw_req; 138 #endif 139 struct mtx aw_mtx; 140 struct resource * aw_res[AW_MMC_RESSZ]; 141 struct aw_mmc_conf * aw_mmc_conf; 142 uint32_t aw_intr; 143 uint32_t aw_intr_wait; 144 void * aw_intrhand; 145 unsigned int aw_clock; 146 device_t child; 147 148 /* Fields required for DMA access. */ 149 bus_addr_t aw_dma_desc_phys; 150 bus_dmamap_t aw_dma_map; 151 bus_dma_tag_t aw_dma_tag; 152 void * aw_dma_desc; 153 bus_dmamap_t aw_dma_buf_map; 154 bus_dma_tag_t aw_dma_buf_tag; 155 int aw_dma_map_err; 156 }; 157 158 static struct resource_spec aw_mmc_res_spec[] = { 159 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 160 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 161 { -1, 0, 0 } 162 }; 163 164 static int aw_mmc_probe(device_t); 165 static int aw_mmc_attach(device_t); 166 static int aw_mmc_detach(device_t); 167 static int aw_mmc_setup_dma(struct aw_mmc_softc *); 168 static void aw_mmc_teardown_dma(struct aw_mmc_softc *sc); 169 static int aw_mmc_reset(struct aw_mmc_softc *); 170 static int aw_mmc_init(struct aw_mmc_softc *); 171 static void aw_mmc_intr(void *); 172 static int aw_mmc_update_clock(struct aw_mmc_softc *, uint32_t); 173 static void aw_mmc_helper_cd_handler(device_t, bool); 174 175 static void aw_mmc_print_error(uint32_t); 176 static int aw_mmc_update_ios(device_t, device_t); 177 static int aw_mmc_request(device_t, device_t, struct mmc_request *); 178 179 #ifndef MMCCAM 180 static int aw_mmc_get_ro(device_t, device_t); 181 static int aw_mmc_acquire_host(device_t, device_t); 182 static int aw_mmc_release_host(device_t, device_t); 183 #endif 184 185 #define AW_MMC_LOCK(_sc) mtx_lock(&(_sc)->aw_mtx) 186 #define AW_MMC_UNLOCK(_sc) mtx_unlock(&(_sc)->aw_mtx) 187 #define AW_MMC_READ_4(_sc, _reg) \ 188 bus_read_4((_sc)->aw_res[AW_MMC_MEMRES], _reg) 189 #define AW_MMC_WRITE_4(_sc, _reg, _value) \ 190 bus_write_4((_sc)->aw_res[AW_MMC_MEMRES], _reg, _value) 191 192 SYSCTL_NODE(_hw, OID_AUTO, aw_mmc, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 193 "aw_mmc driver"); 194 195 static int aw_mmc_debug = 0; 196 SYSCTL_INT(_hw_aw_mmc, OID_AUTO, debug, CTLFLAG_RWTUN, &aw_mmc_debug, 0, 197 "Debug level bit0=card changes bit1=ios changes, bit2=interrupts, bit3=commands"); 198 #define AW_MMC_DEBUG_CARD 0x1 199 #define AW_MMC_DEBUG_IOS 0x2 200 #define AW_MMC_DEBUG_INT 0x4 201 #define AW_MMC_DEBUG_CMD 0x8 202 203 #ifdef MMCCAM 204 static int 205 aw_mmc_get_tran_settings(device_t dev, struct ccb_trans_settings_mmc *cts) 206 { 207 struct aw_mmc_softc *sc; 208 209 sc = device_get_softc(dev); 210 211 cts->host_ocr = sc->aw_host.host_ocr; 212 cts->host_f_min = sc->aw_host.f_min; 213 cts->host_f_max = sc->aw_host.f_max; 214 cts->host_caps = sc->aw_host.caps; 215 cts->host_max_data = (sc->aw_mmc_conf->dma_xferlen * 216 AW_MMC_DMA_SEGS) / MMC_SECTOR_SIZE; 217 memcpy(&cts->ios, &sc->aw_host.ios, sizeof(struct mmc_ios)); 218 219 return (0); 220 } 221 222 static int 223 aw_mmc_set_tran_settings(device_t dev, struct ccb_trans_settings_mmc *cts) 224 { 225 struct aw_mmc_softc *sc; 226 struct mmc_ios *ios; 227 struct mmc_ios *new_ios; 228 229 sc = device_get_softc(dev); 230 ios = &sc->aw_host.ios; 231 new_ios = &cts->ios; 232 233 /* Update only requested fields */ 234 if (cts->ios_valid & MMC_CLK) { 235 ios->clock = new_ios->clock; 236 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS)) 237 device_printf(sc->aw_dev, "Clock => %d\n", ios->clock); 238 } 239 if (cts->ios_valid & MMC_VDD) { 240 ios->vdd = new_ios->vdd; 241 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS)) 242 device_printf(sc->aw_dev, "VDD => %d\n", ios->vdd); 243 } 244 if (cts->ios_valid & MMC_CS) { 245 ios->chip_select = new_ios->chip_select; 246 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS)) 247 device_printf(sc->aw_dev, "CS => %d\n", ios->chip_select); 248 } 249 if (cts->ios_valid & MMC_BW) { 250 ios->bus_width = new_ios->bus_width; 251 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS)) 252 device_printf(sc->aw_dev, "Bus width => %d\n", ios->bus_width); 253 } 254 if (cts->ios_valid & MMC_PM) { 255 ios->power_mode = new_ios->power_mode; 256 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS)) 257 device_printf(sc->aw_dev, "Power mode => %d\n", ios->power_mode); 258 } 259 if (cts->ios_valid & MMC_BT) { 260 ios->timing = new_ios->timing; 261 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS)) 262 device_printf(sc->aw_dev, "Timing => %d\n", ios->timing); 263 } 264 if (cts->ios_valid & MMC_BM) { 265 ios->bus_mode = new_ios->bus_mode; 266 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS)) 267 device_printf(sc->aw_dev, "Bus mode => %d\n", ios->bus_mode); 268 } 269 270 return (aw_mmc_update_ios(sc->aw_dev, NULL)); 271 } 272 273 static int 274 aw_mmc_cam_request(device_t dev, union ccb *ccb) 275 { 276 struct aw_mmc_softc *sc; 277 struct ccb_mmcio *mmcio; 278 279 sc = device_get_softc(dev); 280 mmcio = &ccb->mmcio; 281 282 AW_MMC_LOCK(sc); 283 284 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CMD)) { 285 device_printf(sc->aw_dev, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 286 mmcio->cmd.opcode, mmcio->cmd.arg, mmcio->cmd.flags, 287 mmcio->cmd.data != NULL ? (unsigned int) mmcio->cmd.data->len : 0, 288 mmcio->cmd.data != NULL ? mmcio->cmd.data->flags: 0); 289 } 290 if (mmcio->cmd.data != NULL) { 291 if (mmcio->cmd.data->len == 0 || mmcio->cmd.data->flags == 0) 292 panic("data->len = %d, data->flags = %d -- something is b0rked", 293 (int)mmcio->cmd.data->len, mmcio->cmd.data->flags); 294 } 295 if (sc->ccb != NULL) { 296 device_printf(sc->aw_dev, "Controller still has an active command\n"); 297 return (EBUSY); 298 } 299 sc->ccb = ccb; 300 /* aw_mmc_request locks again */ 301 AW_MMC_UNLOCK(sc); 302 aw_mmc_request(sc->aw_dev, NULL, NULL); 303 304 return (0); 305 } 306 307 static void 308 aw_mmc_cam_poll(device_t dev) 309 { 310 struct aw_mmc_softc *sc; 311 312 sc = device_get_softc(dev); 313 aw_mmc_intr(sc); 314 } 315 #endif /* MMCCAM */ 316 317 static void 318 aw_mmc_helper_cd_handler(device_t dev, bool present) 319 { 320 struct aw_mmc_softc *sc; 321 322 sc = device_get_softc(dev); 323 #ifdef MMCCAM 324 mmc_cam_sim_discover(&sc->mmc_sim); 325 #else 326 AW_MMC_LOCK(sc); 327 if (present) { 328 if (sc->child == NULL) { 329 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CARD)) 330 device_printf(sc->aw_dev, "Card inserted\n"); 331 332 sc->child = device_add_child(sc->aw_dev, "mmc", -1); 333 AW_MMC_UNLOCK(sc); 334 if (sc->child) { 335 device_set_ivars(sc->child, sc); 336 (void)device_probe_and_attach(sc->child); 337 } 338 } else 339 AW_MMC_UNLOCK(sc); 340 } else { 341 /* Card isn't present, detach if necessary */ 342 if (sc->child != NULL) { 343 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CARD)) 344 device_printf(sc->aw_dev, "Card removed\n"); 345 346 AW_MMC_UNLOCK(sc); 347 device_delete_child(sc->aw_dev, sc->child); 348 sc->child = NULL; 349 } else 350 AW_MMC_UNLOCK(sc); 351 } 352 #endif /* MMCCAM */ 353 } 354 355 static int 356 aw_mmc_probe(device_t dev) 357 { 358 359 if (!ofw_bus_status_okay(dev)) 360 return (ENXIO); 361 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 362 return (ENXIO); 363 364 device_set_desc(dev, "Allwinner Integrated MMC/SD controller"); 365 366 return (BUS_PROBE_DEFAULT); 367 } 368 369 static int 370 aw_mmc_attach(device_t dev) 371 { 372 struct aw_mmc_softc *sc; 373 struct sysctl_ctx_list *ctx; 374 struct sysctl_oid_list *tree; 375 int error; 376 377 sc = device_get_softc(dev); 378 sc->aw_dev = dev; 379 380 sc->aw_mmc_conf = (struct aw_mmc_conf *)ofw_bus_search_compatible(dev, compat_data)->ocd_data; 381 382 #ifndef MMCCAM 383 sc->aw_req = NULL; 384 #endif 385 if (bus_alloc_resources(dev, aw_mmc_res_spec, sc->aw_res) != 0) { 386 device_printf(dev, "cannot allocate device resources\n"); 387 return (ENXIO); 388 } 389 if (bus_setup_intr(dev, sc->aw_res[AW_MMC_IRQRES], 390 INTR_TYPE_NET | INTR_MPSAFE, NULL, aw_mmc_intr, sc, 391 &sc->aw_intrhand)) { 392 bus_release_resources(dev, aw_mmc_res_spec, sc->aw_res); 393 device_printf(dev, "cannot setup interrupt handler\n"); 394 return (ENXIO); 395 } 396 mtx_init(&sc->aw_mtx, device_get_nameunit(sc->aw_dev), "aw_mmc", 397 MTX_DEF); 398 callout_init_mtx(&sc->aw_timeoutc, &sc->aw_mtx, 0); 399 400 /* De-assert reset */ 401 if (hwreset_get_by_ofw_name(dev, 0, "ahb", &sc->aw_rst_ahb) == 0) { 402 error = hwreset_deassert(sc->aw_rst_ahb); 403 if (error != 0) { 404 device_printf(dev, "cannot de-assert reset\n"); 405 goto fail; 406 } 407 } 408 409 /* Activate the module clock. */ 410 error = clk_get_by_ofw_name(dev, 0, "ahb", &sc->aw_clk_ahb); 411 if (error != 0) { 412 device_printf(dev, "cannot get ahb clock\n"); 413 goto fail; 414 } 415 error = clk_enable(sc->aw_clk_ahb); 416 if (error != 0) { 417 device_printf(dev, "cannot enable ahb clock\n"); 418 goto fail; 419 } 420 error = clk_get_by_ofw_name(dev, 0, "mmc", &sc->aw_clk_mmc); 421 if (error != 0) { 422 device_printf(dev, "cannot get mmc clock\n"); 423 goto fail; 424 } 425 error = clk_set_freq(sc->aw_clk_mmc, CARD_ID_FREQUENCY, 426 CLK_SET_ROUND_DOWN); 427 if (error != 0) { 428 device_printf(dev, "cannot init mmc clock\n"); 429 goto fail; 430 } 431 error = clk_enable(sc->aw_clk_mmc); 432 if (error != 0) { 433 device_printf(dev, "cannot enable mmc clock\n"); 434 goto fail; 435 } 436 437 sc->aw_timeout = 10; 438 ctx = device_get_sysctl_ctx(dev); 439 tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 440 SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "req_timeout", CTLFLAG_RW, 441 &sc->aw_timeout, 0, "Request timeout in seconds"); 442 443 /* Soft Reset controller. */ 444 if (aw_mmc_reset(sc) != 0) { 445 device_printf(dev, "cannot reset the controller\n"); 446 goto fail; 447 } 448 449 if (aw_mmc_setup_dma(sc) != 0) { 450 device_printf(sc->aw_dev, "Couldn't setup DMA!\n"); 451 goto fail; 452 } 453 454 /* Set some defaults for freq and supported mode */ 455 sc->aw_host.f_min = 400000; 456 sc->aw_host.f_max = 52000000; 457 sc->aw_host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340; 458 sc->aw_host.caps |= MMC_CAP_HSPEED | MMC_CAP_SIGNALING_330; 459 mmc_fdt_parse(dev, 0, &sc->mmc_helper, &sc->aw_host); 460 mmc_fdt_gpio_setup(dev, 0, &sc->mmc_helper, aw_mmc_helper_cd_handler); 461 462 #ifdef MMCCAM 463 sc->ccb = NULL; 464 465 if (mmc_cam_sim_alloc(dev, "aw_mmc", &sc->mmc_sim) != 0) { 466 device_printf(dev, "cannot alloc cam sim\n"); 467 goto fail; 468 } 469 #endif /* MMCCAM */ 470 471 return (0); 472 473 fail: 474 callout_drain(&sc->aw_timeoutc); 475 mtx_destroy(&sc->aw_mtx); 476 bus_teardown_intr(dev, sc->aw_res[AW_MMC_IRQRES], sc->aw_intrhand); 477 bus_release_resources(dev, aw_mmc_res_spec, sc->aw_res); 478 479 return (ENXIO); 480 } 481 482 static int 483 aw_mmc_detach(device_t dev) 484 { 485 struct aw_mmc_softc *sc; 486 device_t d; 487 488 sc = device_get_softc(dev); 489 490 clk_disable(sc->aw_clk_mmc); 491 clk_disable(sc->aw_clk_ahb); 492 hwreset_assert(sc->aw_rst_ahb); 493 494 mmc_fdt_gpio_teardown(&sc->mmc_helper); 495 496 callout_drain(&sc->aw_timeoutc); 497 498 AW_MMC_LOCK(sc); 499 d = sc->child; 500 sc->child = NULL; 501 AW_MMC_UNLOCK(sc); 502 if (d != NULL) 503 device_delete_child(sc->aw_dev, d); 504 505 aw_mmc_teardown_dma(sc); 506 507 mtx_destroy(&sc->aw_mtx); 508 509 bus_teardown_intr(dev, sc->aw_res[AW_MMC_IRQRES], sc->aw_intrhand); 510 bus_release_resources(dev, aw_mmc_res_spec, sc->aw_res); 511 512 #ifdef MMCCAM 513 mmc_cam_sim_free(&sc->mmc_sim); 514 #endif 515 516 return (0); 517 } 518 519 static void 520 aw_dma_desc_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err) 521 { 522 struct aw_mmc_softc *sc; 523 524 sc = (struct aw_mmc_softc *)arg; 525 if (err) { 526 sc->aw_dma_map_err = err; 527 return; 528 } 529 sc->aw_dma_desc_phys = segs[0].ds_addr; 530 } 531 532 static int 533 aw_mmc_setup_dma(struct aw_mmc_softc *sc) 534 { 535 int error; 536 537 /* Allocate the DMA descriptor memory. */ 538 error = bus_dma_tag_create( 539 bus_get_dma_tag(sc->aw_dev), /* parent */ 540 AW_MMC_DMA_ALIGN, 0, /* align, boundary */ 541 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 542 BUS_SPACE_MAXADDR, /* highaddr */ 543 NULL, NULL, /* filter, filterarg*/ 544 AW_MMC_DMA_DESC_SIZE, 1, /* maxsize, nsegment */ 545 AW_MMC_DMA_DESC_SIZE, /* maxsegsize */ 546 0, /* flags */ 547 NULL, NULL, /* lock, lockarg*/ 548 &sc->aw_dma_tag); 549 if (error) 550 return (error); 551 552 error = bus_dmamem_alloc(sc->aw_dma_tag, &sc->aw_dma_desc, 553 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, 554 &sc->aw_dma_map); 555 if (error) 556 return (error); 557 558 error = bus_dmamap_load(sc->aw_dma_tag, 559 sc->aw_dma_map, 560 sc->aw_dma_desc, AW_MMC_DMA_DESC_SIZE, 561 aw_dma_desc_cb, sc, 0); 562 if (error) 563 return (error); 564 if (sc->aw_dma_map_err) 565 return (sc->aw_dma_map_err); 566 567 /* Create the DMA map for data transfers. */ 568 error = bus_dma_tag_create( 569 bus_get_dma_tag(sc->aw_dev), /* parent */ 570 AW_MMC_DMA_ALIGN, 0, /* align, boundary */ 571 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 572 BUS_SPACE_MAXADDR, /* highaddr */ 573 NULL, NULL, /* filter, filterarg*/ 574 sc->aw_mmc_conf->dma_xferlen * 575 AW_MMC_DMA_SEGS, AW_MMC_DMA_SEGS, /* maxsize, nsegments */ 576 sc->aw_mmc_conf->dma_xferlen, /* maxsegsize */ 577 BUS_DMA_ALLOCNOW, /* flags */ 578 NULL, NULL, /* lock, lockarg*/ 579 &sc->aw_dma_buf_tag); 580 if (error) 581 return (error); 582 error = bus_dmamap_create(sc->aw_dma_buf_tag, 0, 583 &sc->aw_dma_buf_map); 584 if (error) 585 return (error); 586 587 return (0); 588 } 589 590 static void 591 aw_mmc_teardown_dma(struct aw_mmc_softc *sc) 592 { 593 594 bus_dmamap_unload(sc->aw_dma_tag, sc->aw_dma_map); 595 bus_dmamem_free(sc->aw_dma_tag, sc->aw_dma_desc, sc->aw_dma_map); 596 if (bus_dma_tag_destroy(sc->aw_dma_tag) != 0) 597 device_printf(sc->aw_dev, "Cannot destroy the dma tag\n"); 598 599 bus_dmamap_unload(sc->aw_dma_buf_tag, sc->aw_dma_buf_map); 600 bus_dmamap_destroy(sc->aw_dma_buf_tag, sc->aw_dma_buf_map); 601 if (bus_dma_tag_destroy(sc->aw_dma_buf_tag) != 0) 602 device_printf(sc->aw_dev, "Cannot destroy the dma buf tag\n"); 603 } 604 605 static void 606 aw_dma_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err) 607 { 608 int i; 609 struct aw_mmc_dma_desc *dma_desc; 610 struct aw_mmc_softc *sc; 611 612 sc = (struct aw_mmc_softc *)arg; 613 sc->aw_dma_map_err = err; 614 615 if (err) 616 return; 617 618 dma_desc = sc->aw_dma_desc; 619 for (i = 0; i < nsegs; i++) { 620 if (segs[i].ds_len == sc->aw_mmc_conf->dma_xferlen) 621 dma_desc[i].buf_size = 0; /* Size of 0 indicate max len */ 622 else 623 dma_desc[i].buf_size = segs[i].ds_len; 624 dma_desc[i].buf_addr = segs[i].ds_addr; 625 dma_desc[i].config = AW_MMC_DMA_CONFIG_CH | 626 AW_MMC_DMA_CONFIG_OWN | AW_MMC_DMA_CONFIG_DIC; 627 628 dma_desc[i].next = sc->aw_dma_desc_phys + 629 ((i + 1) * sizeof(struct aw_mmc_dma_desc)); 630 } 631 632 dma_desc[0].config |= AW_MMC_DMA_CONFIG_FD; 633 dma_desc[nsegs - 1].config |= AW_MMC_DMA_CONFIG_LD | 634 AW_MMC_DMA_CONFIG_ER; 635 dma_desc[nsegs - 1].config &= ~AW_MMC_DMA_CONFIG_DIC; 636 dma_desc[nsegs - 1].next = 0; 637 } 638 639 static int 640 aw_mmc_prepare_dma(struct aw_mmc_softc *sc) 641 { 642 bus_dmasync_op_t sync_op; 643 int error; 644 struct mmc_command *cmd; 645 uint32_t val; 646 647 #ifdef MMCCAM 648 cmd = &sc->ccb->mmcio.cmd; 649 #else 650 cmd = sc->aw_req->cmd; 651 #endif 652 if (cmd->data->len > (sc->aw_mmc_conf->dma_xferlen * AW_MMC_DMA_SEGS)) 653 return (EFBIG); 654 error = bus_dmamap_load(sc->aw_dma_buf_tag, sc->aw_dma_buf_map, 655 cmd->data->data, cmd->data->len, aw_dma_cb, sc, 0); 656 if (error) 657 return (error); 658 if (sc->aw_dma_map_err) 659 return (sc->aw_dma_map_err); 660 661 if (cmd->data->flags & MMC_DATA_WRITE) 662 sync_op = BUS_DMASYNC_PREWRITE; 663 else 664 sync_op = BUS_DMASYNC_PREREAD; 665 bus_dmamap_sync(sc->aw_dma_buf_tag, sc->aw_dma_buf_map, sync_op); 666 bus_dmamap_sync(sc->aw_dma_tag, sc->aw_dma_map, BUS_DMASYNC_PREWRITE); 667 668 /* Enable DMA */ 669 val = AW_MMC_READ_4(sc, AW_MMC_GCTL); 670 val &= ~AW_MMC_GCTL_FIFO_AC_MOD; 671 val |= AW_MMC_GCTL_DMA_ENB; 672 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val); 673 674 /* Reset DMA */ 675 val |= AW_MMC_GCTL_DMA_RST; 676 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val); 677 678 AW_MMC_WRITE_4(sc, AW_MMC_DMAC, AW_MMC_DMAC_IDMAC_SOFT_RST); 679 AW_MMC_WRITE_4(sc, AW_MMC_DMAC, 680 AW_MMC_DMAC_IDMAC_IDMA_ON | AW_MMC_DMAC_IDMAC_FIX_BURST); 681 682 /* Enable RX or TX DMA interrupt */ 683 val = AW_MMC_READ_4(sc, AW_MMC_IDIE); 684 if (cmd->data->flags & MMC_DATA_WRITE) 685 val |= AW_MMC_IDST_TX_INT; 686 else 687 val |= AW_MMC_IDST_RX_INT; 688 AW_MMC_WRITE_4(sc, AW_MMC_IDIE, val); 689 690 /* Set DMA descritptor list address */ 691 AW_MMC_WRITE_4(sc, AW_MMC_DLBA, sc->aw_dma_desc_phys); 692 693 /* FIFO trigger level */ 694 AW_MMC_WRITE_4(sc, AW_MMC_FWLR, AW_MMC_DMA_FTRGLEVEL); 695 696 return (0); 697 } 698 699 static int 700 aw_mmc_reset(struct aw_mmc_softc *sc) 701 { 702 uint32_t reg; 703 int timeout; 704 705 reg = AW_MMC_READ_4(sc, AW_MMC_GCTL); 706 reg |= AW_MMC_GCTL_RESET; 707 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg); 708 timeout = AW_MMC_RESET_RETRY; 709 while (--timeout > 0) { 710 if ((AW_MMC_READ_4(sc, AW_MMC_GCTL) & AW_MMC_GCTL_RESET) == 0) 711 break; 712 DELAY(100); 713 } 714 if (timeout == 0) 715 return (ETIMEDOUT); 716 717 return (0); 718 } 719 720 static int 721 aw_mmc_init(struct aw_mmc_softc *sc) 722 { 723 uint32_t reg; 724 int ret; 725 726 ret = aw_mmc_reset(sc); 727 if (ret != 0) 728 return (ret); 729 730 /* Set the timeout. */ 731 AW_MMC_WRITE_4(sc, AW_MMC_TMOR, 732 AW_MMC_TMOR_DTO_LMT_SHIFT(AW_MMC_TMOR_DTO_LMT_MASK) | 733 AW_MMC_TMOR_RTO_LMT_SHIFT(AW_MMC_TMOR_RTO_LMT_MASK)); 734 735 /* Unmask interrupts. */ 736 AW_MMC_WRITE_4(sc, AW_MMC_IMKR, 0); 737 738 /* Clear pending interrupts. */ 739 AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff); 740 741 /* Debug register, undocumented */ 742 AW_MMC_WRITE_4(sc, AW_MMC_DBGC, 0xdeb); 743 744 /* Function select register */ 745 AW_MMC_WRITE_4(sc, AW_MMC_FUNS, 0xceaa0000); 746 747 AW_MMC_WRITE_4(sc, AW_MMC_IDST, 0xffffffff); 748 749 /* Enable interrupts and disable AHB access. */ 750 reg = AW_MMC_READ_4(sc, AW_MMC_GCTL); 751 reg |= AW_MMC_GCTL_INT_ENB; 752 reg &= ~AW_MMC_GCTL_FIFO_AC_MOD; 753 reg &= ~AW_MMC_GCTL_WAIT_MEM_ACCESS; 754 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg); 755 756 return (0); 757 } 758 759 static void 760 aw_mmc_req_done(struct aw_mmc_softc *sc) 761 { 762 struct mmc_command *cmd; 763 #ifdef MMCCAM 764 union ccb *ccb; 765 #else 766 struct mmc_request *req; 767 #endif 768 uint32_t val, mask; 769 int retry; 770 771 #ifdef MMCCAM 772 ccb = sc->ccb; 773 cmd = &ccb->mmcio.cmd; 774 #else 775 cmd = sc->aw_req->cmd; 776 #endif 777 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CMD)) { 778 device_printf(sc->aw_dev, "%s: cmd %d err %d\n", __func__, cmd->opcode, cmd->error); 779 } 780 if (cmd->error != MMC_ERR_NONE) { 781 /* Reset the FIFO and DMA engines. */ 782 mask = AW_MMC_GCTL_FIFO_RST | AW_MMC_GCTL_DMA_RST; 783 val = AW_MMC_READ_4(sc, AW_MMC_GCTL); 784 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val | mask); 785 786 retry = AW_MMC_RESET_RETRY; 787 while (--retry > 0) { 788 if ((AW_MMC_READ_4(sc, AW_MMC_GCTL) & 789 AW_MMC_GCTL_RESET) == 0) 790 break; 791 DELAY(100); 792 } 793 if (retry == 0) 794 device_printf(sc->aw_dev, 795 "timeout resetting DMA/FIFO\n"); 796 aw_mmc_update_clock(sc, 1); 797 } 798 799 if (!dumping) 800 callout_stop(&sc->aw_timeoutc); 801 sc->aw_intr = 0; 802 sc->aw_resid = 0; 803 sc->aw_dma_map_err = 0; 804 sc->aw_intr_wait = 0; 805 #ifdef MMCCAM 806 sc->ccb = NULL; 807 ccb->ccb_h.status = 808 (ccb->mmcio.cmd.error == 0 ? CAM_REQ_CMP : CAM_REQ_CMP_ERR); 809 xpt_done(ccb); 810 #else 811 req = sc->aw_req; 812 sc->aw_req = NULL; 813 req->done(req); 814 #endif 815 } 816 817 static void 818 aw_mmc_req_ok(struct aw_mmc_softc *sc) 819 { 820 int timeout; 821 struct mmc_command *cmd; 822 uint32_t status; 823 824 timeout = 1000; 825 while (--timeout > 0) { 826 status = AW_MMC_READ_4(sc, AW_MMC_STAR); 827 if ((status & AW_MMC_STAR_CARD_BUSY) == 0) 828 break; 829 DELAY(1000); 830 } 831 #ifdef MMCCAM 832 cmd = &sc->ccb->mmcio.cmd; 833 #else 834 cmd = sc->aw_req->cmd; 835 #endif 836 if (timeout == 0) { 837 cmd->error = MMC_ERR_FAILED; 838 aw_mmc_req_done(sc); 839 return; 840 } 841 if (cmd->flags & MMC_RSP_PRESENT) { 842 if (cmd->flags & MMC_RSP_136) { 843 cmd->resp[0] = AW_MMC_READ_4(sc, AW_MMC_RESP3); 844 cmd->resp[1] = AW_MMC_READ_4(sc, AW_MMC_RESP2); 845 cmd->resp[2] = AW_MMC_READ_4(sc, AW_MMC_RESP1); 846 cmd->resp[3] = AW_MMC_READ_4(sc, AW_MMC_RESP0); 847 } else 848 cmd->resp[0] = AW_MMC_READ_4(sc, AW_MMC_RESP0); 849 } 850 /* All data has been transferred ? */ 851 if (cmd->data != NULL && (sc->aw_resid << 2) < cmd->data->len) 852 cmd->error = MMC_ERR_FAILED; 853 aw_mmc_req_done(sc); 854 } 855 856 static inline void 857 set_mmc_error(struct aw_mmc_softc *sc, int error_code) 858 { 859 #ifdef MMCCAM 860 sc->ccb->mmcio.cmd.error = error_code; 861 #else 862 sc->aw_req->cmd->error = error_code; 863 #endif 864 } 865 866 static void 867 aw_mmc_timeout(void *arg) 868 { 869 struct aw_mmc_softc *sc; 870 871 sc = (struct aw_mmc_softc *)arg; 872 #ifdef MMCCAM 873 if (sc->ccb != NULL) { 874 #else 875 if (sc->aw_req != NULL) { 876 #endif 877 device_printf(sc->aw_dev, "controller timeout\n"); 878 set_mmc_error(sc, MMC_ERR_TIMEOUT); 879 aw_mmc_req_done(sc); 880 } else 881 device_printf(sc->aw_dev, 882 "Spurious timeout - no active request\n"); 883 } 884 885 static void 886 aw_mmc_print_error(uint32_t err) 887 { 888 if(err & AW_MMC_INT_RESP_ERR) 889 printf("AW_MMC_INT_RESP_ERR "); 890 if (err & AW_MMC_INT_RESP_CRC_ERR) 891 printf("AW_MMC_INT_RESP_CRC_ERR "); 892 if (err & AW_MMC_INT_DATA_CRC_ERR) 893 printf("AW_MMC_INT_DATA_CRC_ERR "); 894 if (err & AW_MMC_INT_RESP_TIMEOUT) 895 printf("AW_MMC_INT_RESP_TIMEOUT "); 896 if (err & AW_MMC_INT_FIFO_RUN_ERR) 897 printf("AW_MMC_INT_FIFO_RUN_ERR "); 898 if (err & AW_MMC_INT_CMD_BUSY) 899 printf("AW_MMC_INT_CMD_BUSY "); 900 if (err & AW_MMC_INT_DATA_START_ERR) 901 printf("AW_MMC_INT_DATA_START_ERR "); 902 if (err & AW_MMC_INT_DATA_END_BIT_ERR) 903 printf("AW_MMC_INT_DATA_END_BIT_ERR"); 904 printf("\n"); 905 } 906 907 static void 908 aw_mmc_intr(void *arg) 909 { 910 bus_dmasync_op_t sync_op; 911 struct aw_mmc_softc *sc; 912 struct mmc_data *data; 913 uint32_t idst, imask, rint; 914 915 sc = (struct aw_mmc_softc *)arg; 916 AW_MMC_LOCK(sc); 917 rint = AW_MMC_READ_4(sc, AW_MMC_RISR); 918 idst = AW_MMC_READ_4(sc, AW_MMC_IDST); 919 imask = AW_MMC_READ_4(sc, AW_MMC_IMKR); 920 if (idst == 0 && imask == 0 && rint == 0) { 921 AW_MMC_UNLOCK(sc); 922 return; 923 } 924 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_INT)) { 925 device_printf(sc->aw_dev, "idst: %#x, imask: %#x, rint: %#x\n", 926 idst, imask, rint); 927 } 928 #ifdef MMCCAM 929 if (sc->ccb == NULL) { 930 #else 931 if (sc->aw_req == NULL) { 932 #endif 933 device_printf(sc->aw_dev, 934 "Spurious interrupt - no active request, rint: 0x%08X\n", 935 rint); 936 aw_mmc_print_error(rint); 937 goto end; 938 } 939 if (rint & AW_MMC_INT_ERR_BIT) { 940 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_INT)) { 941 device_printf(sc->aw_dev, "error rint: 0x%08X\n", rint); 942 aw_mmc_print_error(rint); 943 } 944 if (rint & AW_MMC_INT_RESP_TIMEOUT) 945 set_mmc_error(sc, MMC_ERR_TIMEOUT); 946 else 947 set_mmc_error(sc, MMC_ERR_FAILED); 948 aw_mmc_req_done(sc); 949 goto end; 950 } 951 if (idst & AW_MMC_IDST_ERROR) { 952 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_INT)) 953 device_printf(sc->aw_dev, "error idst: 0x%08x\n", idst); 954 set_mmc_error(sc, MMC_ERR_FAILED); 955 aw_mmc_req_done(sc); 956 goto end; 957 } 958 959 sc->aw_intr |= rint; 960 #ifdef MMCCAM 961 data = sc->ccb->mmcio.cmd.data; 962 #else 963 data = sc->aw_req->cmd->data; 964 #endif 965 if (data != NULL && (idst & AW_MMC_IDST_COMPLETE) != 0) { 966 if (data->flags & MMC_DATA_WRITE) 967 sync_op = BUS_DMASYNC_POSTWRITE; 968 else 969 sync_op = BUS_DMASYNC_POSTREAD; 970 bus_dmamap_sync(sc->aw_dma_buf_tag, sc->aw_dma_buf_map, 971 sync_op); 972 bus_dmamap_sync(sc->aw_dma_tag, sc->aw_dma_map, 973 BUS_DMASYNC_POSTWRITE); 974 bus_dmamap_unload(sc->aw_dma_buf_tag, sc->aw_dma_buf_map); 975 sc->aw_resid = data->len >> 2; 976 } 977 if ((sc->aw_intr & sc->aw_intr_wait) == sc->aw_intr_wait) 978 aw_mmc_req_ok(sc); 979 980 end: 981 AW_MMC_WRITE_4(sc, AW_MMC_IDST, idst); 982 AW_MMC_WRITE_4(sc, AW_MMC_RISR, rint); 983 AW_MMC_UNLOCK(sc); 984 } 985 986 static int 987 aw_mmc_request(device_t bus, device_t child, struct mmc_request *req) 988 { 989 int blksz; 990 struct aw_mmc_softc *sc; 991 struct mmc_command *cmd; 992 uint32_t cmdreg, imask; 993 int err; 994 995 sc = device_get_softc(bus); 996 997 AW_MMC_LOCK(sc); 998 #ifdef MMCCAM 999 KASSERT(req == NULL, ("req should be NULL in MMCCAM case!")); 1000 /* 1001 * For MMCCAM, sc->ccb has been NULL-checked and populated 1002 * by aw_mmc_cam_request() already. 1003 */ 1004 cmd = &sc->ccb->mmcio.cmd; 1005 #else 1006 if (sc->aw_req) { 1007 AW_MMC_UNLOCK(sc); 1008 return (EBUSY); 1009 } 1010 sc->aw_req = req; 1011 cmd = req->cmd; 1012 1013 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CMD)) { 1014 device_printf(sc->aw_dev, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 1015 cmd->opcode, cmd->arg, cmd->flags, 1016 cmd->data != NULL ? (unsigned int)cmd->data->len : 0, 1017 cmd->data != NULL ? cmd->data->flags: 0); 1018 } 1019 #endif 1020 cmdreg = AW_MMC_CMDR_LOAD; 1021 imask = AW_MMC_INT_ERR_BIT; 1022 sc->aw_intr_wait = 0; 1023 sc->aw_intr = 0; 1024 sc->aw_resid = 0; 1025 cmd->error = MMC_ERR_NONE; 1026 1027 if (cmd->opcode == MMC_GO_IDLE_STATE) 1028 cmdreg |= AW_MMC_CMDR_SEND_INIT_SEQ; 1029 1030 if (cmd->flags & MMC_RSP_PRESENT) 1031 cmdreg |= AW_MMC_CMDR_RESP_RCV; 1032 if (cmd->flags & MMC_RSP_136) 1033 cmdreg |= AW_MMC_CMDR_LONG_RESP; 1034 if (cmd->flags & MMC_RSP_CRC) 1035 cmdreg |= AW_MMC_CMDR_CHK_RESP_CRC; 1036 1037 if (cmd->data) { 1038 cmdreg |= AW_MMC_CMDR_DATA_TRANS | AW_MMC_CMDR_WAIT_PRE_OVER; 1039 1040 if (cmd->data->flags & MMC_DATA_MULTI) { 1041 cmdreg |= AW_MMC_CMDR_STOP_CMD_FLAG; 1042 imask |= AW_MMC_INT_AUTO_STOP_DONE; 1043 sc->aw_intr_wait |= AW_MMC_INT_AUTO_STOP_DONE; 1044 } else { 1045 sc->aw_intr_wait |= AW_MMC_INT_DATA_OVER; 1046 imask |= AW_MMC_INT_DATA_OVER; 1047 } 1048 if (cmd->data->flags & MMC_DATA_WRITE) 1049 cmdreg |= AW_MMC_CMDR_DIR_WRITE; 1050 #ifdef MMCCAM 1051 if (cmd->data->flags & MMC_DATA_BLOCK_SIZE) { 1052 AW_MMC_WRITE_4(sc, AW_MMC_BKSR, cmd->data->block_size); 1053 AW_MMC_WRITE_4(sc, AW_MMC_BYCR, cmd->data->len); 1054 } else 1055 #endif 1056 { 1057 blksz = min(cmd->data->len, MMC_SECTOR_SIZE); 1058 AW_MMC_WRITE_4(sc, AW_MMC_BKSR, blksz); 1059 AW_MMC_WRITE_4(sc, AW_MMC_BYCR, cmd->data->len); 1060 } 1061 } else { 1062 imask |= AW_MMC_INT_CMD_DONE; 1063 } 1064 1065 /* Enable the interrupts we are interested in */ 1066 AW_MMC_WRITE_4(sc, AW_MMC_IMKR, imask); 1067 AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff); 1068 1069 /* Enable auto stop if needed */ 1070 AW_MMC_WRITE_4(sc, AW_MMC_A12A, 1071 cmdreg & AW_MMC_CMDR_STOP_CMD_FLAG ? 0 : 0xffff); 1072 1073 /* Write the command argument */ 1074 AW_MMC_WRITE_4(sc, AW_MMC_CAGR, cmd->arg); 1075 1076 /* 1077 * If we don't have data start the request 1078 * if we do prepare the dma request and start the request 1079 */ 1080 if (cmd->data == NULL) { 1081 AW_MMC_WRITE_4(sc, AW_MMC_CMDR, cmdreg | cmd->opcode); 1082 } else { 1083 err = aw_mmc_prepare_dma(sc); 1084 if (err != 0) 1085 device_printf(sc->aw_dev, "prepare_dma failed: %d\n", err); 1086 1087 AW_MMC_WRITE_4(sc, AW_MMC_CMDR, cmdreg | cmd->opcode); 1088 } 1089 1090 if (!dumping) { 1091 callout_reset(&sc->aw_timeoutc, sc->aw_timeout * hz, 1092 aw_mmc_timeout, sc); 1093 } 1094 AW_MMC_UNLOCK(sc); 1095 1096 return (0); 1097 } 1098 1099 static int 1100 aw_mmc_read_ivar(device_t bus, device_t child, int which, 1101 uintptr_t *result) 1102 { 1103 struct aw_mmc_softc *sc; 1104 1105 sc = device_get_softc(bus); 1106 switch (which) { 1107 default: 1108 return (EINVAL); 1109 case MMCBR_IVAR_BUS_MODE: 1110 *(int *)result = sc->aw_host.ios.bus_mode; 1111 break; 1112 case MMCBR_IVAR_BUS_WIDTH: 1113 *(int *)result = sc->aw_host.ios.bus_width; 1114 break; 1115 case MMCBR_IVAR_CHIP_SELECT: 1116 *(int *)result = sc->aw_host.ios.chip_select; 1117 break; 1118 case MMCBR_IVAR_CLOCK: 1119 *(int *)result = sc->aw_host.ios.clock; 1120 break; 1121 case MMCBR_IVAR_F_MIN: 1122 *(int *)result = sc->aw_host.f_min; 1123 break; 1124 case MMCBR_IVAR_F_MAX: 1125 *(int *)result = sc->aw_host.f_max; 1126 break; 1127 case MMCBR_IVAR_HOST_OCR: 1128 *(int *)result = sc->aw_host.host_ocr; 1129 break; 1130 case MMCBR_IVAR_MODE: 1131 *(int *)result = sc->aw_host.mode; 1132 break; 1133 case MMCBR_IVAR_OCR: 1134 *(int *)result = sc->aw_host.ocr; 1135 break; 1136 case MMCBR_IVAR_POWER_MODE: 1137 *(int *)result = sc->aw_host.ios.power_mode; 1138 break; 1139 case MMCBR_IVAR_VDD: 1140 *(int *)result = sc->aw_host.ios.vdd; 1141 break; 1142 case MMCBR_IVAR_VCCQ: 1143 *(int *)result = sc->aw_host.ios.vccq; 1144 break; 1145 case MMCBR_IVAR_CAPS: 1146 *(int *)result = sc->aw_host.caps; 1147 break; 1148 case MMCBR_IVAR_TIMING: 1149 *(int *)result = sc->aw_host.ios.timing; 1150 break; 1151 case MMCBR_IVAR_MAX_DATA: 1152 *(int *)result = (sc->aw_mmc_conf->dma_xferlen * 1153 AW_MMC_DMA_SEGS) / MMC_SECTOR_SIZE; 1154 break; 1155 case MMCBR_IVAR_RETUNE_REQ: 1156 *(int *)result = retune_req_none; 1157 break; 1158 } 1159 1160 return (0); 1161 } 1162 1163 static int 1164 aw_mmc_write_ivar(device_t bus, device_t child, int which, 1165 uintptr_t value) 1166 { 1167 struct aw_mmc_softc *sc; 1168 1169 sc = device_get_softc(bus); 1170 switch (which) { 1171 default: 1172 return (EINVAL); 1173 case MMCBR_IVAR_BUS_MODE: 1174 sc->aw_host.ios.bus_mode = value; 1175 break; 1176 case MMCBR_IVAR_BUS_WIDTH: 1177 sc->aw_host.ios.bus_width = value; 1178 break; 1179 case MMCBR_IVAR_CHIP_SELECT: 1180 sc->aw_host.ios.chip_select = value; 1181 break; 1182 case MMCBR_IVAR_CLOCK: 1183 sc->aw_host.ios.clock = value; 1184 break; 1185 case MMCBR_IVAR_MODE: 1186 sc->aw_host.mode = value; 1187 break; 1188 case MMCBR_IVAR_OCR: 1189 sc->aw_host.ocr = value; 1190 break; 1191 case MMCBR_IVAR_POWER_MODE: 1192 sc->aw_host.ios.power_mode = value; 1193 break; 1194 case MMCBR_IVAR_VDD: 1195 sc->aw_host.ios.vdd = value; 1196 break; 1197 case MMCBR_IVAR_VCCQ: 1198 sc->aw_host.ios.vccq = value; 1199 break; 1200 case MMCBR_IVAR_TIMING: 1201 sc->aw_host.ios.timing = value; 1202 break; 1203 /* These are read-only */ 1204 case MMCBR_IVAR_CAPS: 1205 case MMCBR_IVAR_HOST_OCR: 1206 case MMCBR_IVAR_F_MIN: 1207 case MMCBR_IVAR_F_MAX: 1208 case MMCBR_IVAR_MAX_DATA: 1209 return (EINVAL); 1210 } 1211 1212 return (0); 1213 } 1214 1215 static int 1216 aw_mmc_update_clock(struct aw_mmc_softc *sc, uint32_t clkon) 1217 { 1218 uint32_t reg; 1219 int retry; 1220 1221 reg = AW_MMC_READ_4(sc, AW_MMC_CKCR); 1222 reg &= ~(AW_MMC_CKCR_ENB | AW_MMC_CKCR_LOW_POWER | 1223 AW_MMC_CKCR_MASK_DATA0); 1224 1225 if (clkon) 1226 reg |= AW_MMC_CKCR_ENB; 1227 if (sc->aw_mmc_conf->mask_data0) 1228 reg |= AW_MMC_CKCR_MASK_DATA0; 1229 1230 AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg); 1231 1232 reg = AW_MMC_CMDR_LOAD | AW_MMC_CMDR_PRG_CLK | 1233 AW_MMC_CMDR_WAIT_PRE_OVER; 1234 AW_MMC_WRITE_4(sc, AW_MMC_CMDR, reg); 1235 retry = 0xfffff; 1236 1237 while (reg & AW_MMC_CMDR_LOAD && --retry > 0) { 1238 reg = AW_MMC_READ_4(sc, AW_MMC_CMDR); 1239 DELAY(10); 1240 } 1241 AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff); 1242 1243 if (reg & AW_MMC_CMDR_LOAD) { 1244 device_printf(sc->aw_dev, "timeout updating clock\n"); 1245 return (ETIMEDOUT); 1246 } 1247 1248 if (sc->aw_mmc_conf->mask_data0) { 1249 reg = AW_MMC_READ_4(sc, AW_MMC_CKCR); 1250 reg &= ~AW_MMC_CKCR_MASK_DATA0; 1251 AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg); 1252 } 1253 1254 return (0); 1255 } 1256 1257 #ifndef MMCCAM 1258 static int 1259 aw_mmc_switch_vccq(device_t bus, device_t child) 1260 { 1261 struct aw_mmc_softc *sc; 1262 int uvolt, err; 1263 1264 sc = device_get_softc(bus); 1265 1266 if (sc->mmc_helper.vqmmc_supply == NULL) 1267 return EOPNOTSUPP; 1268 1269 switch (sc->aw_host.ios.vccq) { 1270 case vccq_180: 1271 uvolt = 1800000; 1272 break; 1273 case vccq_330: 1274 uvolt = 3300000; 1275 break; 1276 default: 1277 return EINVAL; 1278 } 1279 1280 err = regulator_set_voltage(sc->mmc_helper.vqmmc_supply, uvolt, uvolt); 1281 if (err != 0) { 1282 device_printf(sc->aw_dev, 1283 "Cannot set vqmmc to %d<->%d\n", 1284 uvolt, 1285 uvolt); 1286 return (err); 1287 } 1288 1289 return (0); 1290 } 1291 #endif 1292 1293 static int 1294 aw_mmc_update_ios(device_t bus, device_t child) 1295 { 1296 int error; 1297 struct aw_mmc_softc *sc; 1298 struct mmc_ios *ios; 1299 unsigned int clock; 1300 uint32_t reg, div = 1; 1301 int reg_status; 1302 int rv; 1303 1304 sc = device_get_softc(bus); 1305 1306 ios = &sc->aw_host.ios; 1307 1308 /* Set the bus width. */ 1309 switch (ios->bus_width) { 1310 case bus_width_1: 1311 AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR1); 1312 break; 1313 case bus_width_4: 1314 AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR4); 1315 break; 1316 case bus_width_8: 1317 AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR8); 1318 break; 1319 } 1320 1321 switch (ios->power_mode) { 1322 case power_on: 1323 break; 1324 case power_off: 1325 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CARD)) 1326 device_printf(sc->aw_dev, "Powering down sd/mmc\n"); 1327 1328 if (sc->mmc_helper.vmmc_supply) { 1329 rv = regulator_status(sc->mmc_helper.vmmc_supply, ®_status); 1330 if (rv == 0 && reg_status == REGULATOR_STATUS_ENABLED) 1331 regulator_disable(sc->mmc_helper.vmmc_supply); 1332 } 1333 if (sc->mmc_helper.vqmmc_supply) { 1334 rv = regulator_status(sc->mmc_helper.vqmmc_supply, ®_status); 1335 if (rv == 0 && reg_status == REGULATOR_STATUS_ENABLED) 1336 regulator_disable(sc->mmc_helper.vqmmc_supply); 1337 } 1338 1339 if (sc->mmc_helper.mmc_pwrseq) 1340 MMC_PWRSEQ_SET_POWER(sc->mmc_helper.mmc_pwrseq, false); 1341 1342 aw_mmc_reset(sc); 1343 break; 1344 case power_up: 1345 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CARD)) 1346 device_printf(sc->aw_dev, "Powering up sd/mmc\n"); 1347 1348 if (sc->mmc_helper.vmmc_supply) { 1349 rv = regulator_status(sc->mmc_helper.vmmc_supply, ®_status); 1350 if (rv == 0 && reg_status != REGULATOR_STATUS_ENABLED) 1351 regulator_enable(sc->mmc_helper.vmmc_supply); 1352 } 1353 if (sc->mmc_helper.vqmmc_supply) { 1354 rv = regulator_status(sc->mmc_helper.vqmmc_supply, ®_status); 1355 if (rv == 0 && reg_status != REGULATOR_STATUS_ENABLED) 1356 regulator_enable(sc->mmc_helper.vqmmc_supply); 1357 } 1358 1359 if (sc->mmc_helper.mmc_pwrseq) 1360 MMC_PWRSEQ_SET_POWER(sc->mmc_helper.mmc_pwrseq, true); 1361 aw_mmc_init(sc); 1362 break; 1363 }; 1364 1365 /* Enable ddr mode if needed */ 1366 reg = AW_MMC_READ_4(sc, AW_MMC_GCTL); 1367 if (ios->timing == bus_timing_uhs_ddr50 || 1368 ios->timing == bus_timing_mmc_ddr52) 1369 reg |= AW_MMC_GCTL_DDR_MOD_SEL; 1370 else 1371 reg &= ~AW_MMC_GCTL_DDR_MOD_SEL; 1372 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg); 1373 1374 if (ios->clock && ios->clock != sc->aw_clock) { 1375 sc->aw_clock = clock = ios->clock; 1376 1377 /* Disable clock */ 1378 error = aw_mmc_update_clock(sc, 0); 1379 if (error != 0) 1380 return (error); 1381 1382 if (ios->timing == bus_timing_mmc_ddr52 && 1383 (sc->aw_mmc_conf->new_timing || 1384 ios->bus_width == bus_width_8)) { 1385 div = 2; 1386 clock <<= 1; 1387 } 1388 1389 /* Reset the divider. */ 1390 reg = AW_MMC_READ_4(sc, AW_MMC_CKCR); 1391 reg &= ~AW_MMC_CKCR_DIV; 1392 reg |= div - 1; 1393 AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg); 1394 1395 /* New timing mode if needed */ 1396 if (sc->aw_mmc_conf->new_timing) { 1397 reg = AW_MMC_READ_4(sc, AW_MMC_NTSR); 1398 reg |= AW_MMC_NTSR_MODE_SELECT; 1399 AW_MMC_WRITE_4(sc, AW_MMC_NTSR, reg); 1400 } 1401 1402 /* Set the MMC clock. */ 1403 error = clk_disable(sc->aw_clk_mmc); 1404 if (error != 0 && bootverbose) 1405 device_printf(sc->aw_dev, 1406 "failed to disable mmc clock: %d\n", error); 1407 error = clk_set_freq(sc->aw_clk_mmc, clock, 1408 CLK_SET_ROUND_DOWN); 1409 if (error != 0) { 1410 device_printf(sc->aw_dev, 1411 "failed to set frequency to %u Hz: %d\n", 1412 clock, error); 1413 return (error); 1414 } 1415 error = clk_enable(sc->aw_clk_mmc); 1416 if (error != 0 && bootverbose) 1417 device_printf(sc->aw_dev, 1418 "failed to re-enable mmc clock: %d\n", error); 1419 1420 if (sc->aw_mmc_conf->can_calibrate) 1421 AW_MMC_WRITE_4(sc, AW_MMC_SAMP_DL, AW_MMC_SAMP_DL_SW_EN); 1422 1423 /* Enable clock. */ 1424 error = aw_mmc_update_clock(sc, 1); 1425 if (error != 0) 1426 return (error); 1427 } 1428 1429 return (0); 1430 } 1431 1432 #ifndef MMCCAM 1433 static int 1434 aw_mmc_get_ro(device_t bus, device_t child) 1435 { 1436 struct aw_mmc_softc *sc; 1437 1438 sc = device_get_softc(bus); 1439 1440 return (mmc_fdt_gpio_get_readonly(&sc->mmc_helper)); 1441 } 1442 1443 static int 1444 aw_mmc_acquire_host(device_t bus, device_t child) 1445 { 1446 struct aw_mmc_softc *sc; 1447 int error; 1448 1449 sc = device_get_softc(bus); 1450 AW_MMC_LOCK(sc); 1451 while (sc->aw_bus_busy) { 1452 error = msleep(sc, &sc->aw_mtx, PCATCH, "mmchw", 0); 1453 if (error != 0) { 1454 AW_MMC_UNLOCK(sc); 1455 return (error); 1456 } 1457 } 1458 sc->aw_bus_busy++; 1459 AW_MMC_UNLOCK(sc); 1460 1461 return (0); 1462 } 1463 1464 static int 1465 aw_mmc_release_host(device_t bus, device_t child) 1466 { 1467 struct aw_mmc_softc *sc; 1468 1469 sc = device_get_softc(bus); 1470 AW_MMC_LOCK(sc); 1471 sc->aw_bus_busy--; 1472 wakeup(sc); 1473 AW_MMC_UNLOCK(sc); 1474 1475 return (0); 1476 } 1477 #endif 1478 1479 static device_method_t aw_mmc_methods[] = { 1480 /* Device interface */ 1481 DEVMETHOD(device_probe, aw_mmc_probe), 1482 DEVMETHOD(device_attach, aw_mmc_attach), 1483 DEVMETHOD(device_detach, aw_mmc_detach), 1484 1485 /* Bus interface */ 1486 DEVMETHOD(bus_read_ivar, aw_mmc_read_ivar), 1487 DEVMETHOD(bus_write_ivar, aw_mmc_write_ivar), 1488 DEVMETHOD(bus_add_child, bus_generic_add_child), 1489 1490 #ifndef MMCCAM 1491 /* MMC bridge interface */ 1492 DEVMETHOD(mmcbr_update_ios, aw_mmc_update_ios), 1493 DEVMETHOD(mmcbr_request, aw_mmc_request), 1494 DEVMETHOD(mmcbr_get_ro, aw_mmc_get_ro), 1495 DEVMETHOD(mmcbr_switch_vccq, aw_mmc_switch_vccq), 1496 DEVMETHOD(mmcbr_acquire_host, aw_mmc_acquire_host), 1497 DEVMETHOD(mmcbr_release_host, aw_mmc_release_host), 1498 #endif 1499 1500 #ifdef MMCCAM 1501 /* MMCCAM interface */ 1502 DEVMETHOD(mmc_sim_get_tran_settings, aw_mmc_get_tran_settings), 1503 DEVMETHOD(mmc_sim_set_tran_settings, aw_mmc_set_tran_settings), 1504 DEVMETHOD(mmc_sim_cam_request, aw_mmc_cam_request), 1505 DEVMETHOD(mmc_sim_cam_poll, aw_mmc_cam_poll), 1506 #endif 1507 1508 DEVMETHOD_END 1509 }; 1510 1511 static driver_t aw_mmc_driver = { 1512 "aw_mmc", 1513 aw_mmc_methods, 1514 sizeof(struct aw_mmc_softc), 1515 }; 1516 1517 DRIVER_MODULE(aw_mmc, simplebus, aw_mmc_driver, NULL, NULL); 1518 #ifndef MMCCAM 1519 MMC_DECLARE_BRIDGE(aw_mmc); 1520 #endif 1521 SIMPLEBUS_PNP_INFO(compat_data); 1522