1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org> 5 * Copyright (c) 2013 Alexander Fedorov 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/kernel.h> 37 #include <sys/lock.h> 38 #include <sys/malloc.h> 39 #include <sys/module.h> 40 #include <sys/mutex.h> 41 #include <sys/resource.h> 42 #include <sys/rman.h> 43 #include <sys/sysctl.h> 44 45 #include <machine/bus.h> 46 47 #include <dev/ofw/ofw_bus.h> 48 #include <dev/ofw/ofw_bus_subr.h> 49 50 #include <dev/mmc/bridge.h> 51 #include <dev/mmc/mmcbrvar.h> 52 53 #include <arm/allwinner/aw_mmc.h> 54 #include <dev/extres/clk/clk.h> 55 #include <dev/extres/hwreset/hwreset.h> 56 #include <dev/extres/regulator/regulator.h> 57 58 #include "opt_mmccam.h" 59 60 #ifdef MMCCAM 61 #include <cam/cam.h> 62 #include <cam/cam_ccb.h> 63 #include <cam/cam_debug.h> 64 #include <cam/cam_sim.h> 65 #include <cam/cam_xpt_sim.h> 66 #endif 67 68 #define AW_MMC_MEMRES 0 69 #define AW_MMC_IRQRES 1 70 #define AW_MMC_RESSZ 2 71 #define AW_MMC_DMA_SEGS (PAGE_SIZE / sizeof(struct aw_mmc_dma_desc)) 72 #define AW_MMC_DMA_DESC_SIZE (sizeof(struct aw_mmc_dma_desc) * AW_MMC_DMA_SEGS) 73 #define AW_MMC_DMA_FTRGLEVEL 0x20070008 74 75 #define AW_MMC_RESET_RETRY 1000 76 77 #define CARD_ID_FREQUENCY 400000 78 79 struct aw_mmc_conf { 80 uint32_t dma_xferlen; 81 bool mask_data0; 82 bool can_calibrate; 83 bool new_timing; 84 }; 85 86 static const struct aw_mmc_conf a10_mmc_conf = { 87 .dma_xferlen = 0x2000, 88 }; 89 90 static const struct aw_mmc_conf a13_mmc_conf = { 91 .dma_xferlen = 0x10000, 92 }; 93 94 static const struct aw_mmc_conf a64_mmc_conf = { 95 .dma_xferlen = 0x10000, 96 .mask_data0 = true, 97 .can_calibrate = true, 98 .new_timing = true, 99 }; 100 101 static const struct aw_mmc_conf a64_emmc_conf = { 102 .dma_xferlen = 0x2000, 103 .can_calibrate = true, 104 }; 105 106 static struct ofw_compat_data compat_data[] = { 107 {"allwinner,sun4i-a10-mmc", (uintptr_t)&a10_mmc_conf}, 108 {"allwinner,sun5i-a13-mmc", (uintptr_t)&a13_mmc_conf}, 109 {"allwinner,sun7i-a20-mmc", (uintptr_t)&a13_mmc_conf}, 110 {"allwinner,sun50i-a64-mmc", (uintptr_t)&a64_mmc_conf}, 111 {"allwinner,sun50i-a64-emmc", (uintptr_t)&a64_emmc_conf}, 112 {NULL, 0} 113 }; 114 115 struct aw_mmc_softc { 116 device_t aw_dev; 117 clk_t aw_clk_ahb; 118 clk_t aw_clk_mmc; 119 hwreset_t aw_rst_ahb; 120 int aw_bus_busy; 121 int aw_resid; 122 int aw_timeout; 123 struct callout aw_timeoutc; 124 struct mmc_host aw_host; 125 #ifdef MMCCAM 126 union ccb * ccb; 127 struct cam_devq * devq; 128 struct cam_sim * sim; 129 struct mtx sim_mtx; 130 #else 131 struct mmc_request * aw_req; 132 #endif 133 struct mtx aw_mtx; 134 struct resource * aw_res[AW_MMC_RESSZ]; 135 struct aw_mmc_conf * aw_mmc_conf; 136 uint32_t aw_intr; 137 uint32_t aw_intr_wait; 138 void * aw_intrhand; 139 regulator_t aw_reg_vmmc; 140 regulator_t aw_reg_vqmmc; 141 unsigned int aw_clock; 142 143 /* Fields required for DMA access. */ 144 bus_addr_t aw_dma_desc_phys; 145 bus_dmamap_t aw_dma_map; 146 bus_dma_tag_t aw_dma_tag; 147 void * aw_dma_desc; 148 bus_dmamap_t aw_dma_buf_map; 149 bus_dma_tag_t aw_dma_buf_tag; 150 int aw_dma_map_err; 151 }; 152 153 static struct resource_spec aw_mmc_res_spec[] = { 154 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 155 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 156 { -1, 0, 0 } 157 }; 158 159 static int aw_mmc_probe(device_t); 160 static int aw_mmc_attach(device_t); 161 static int aw_mmc_detach(device_t); 162 static int aw_mmc_setup_dma(struct aw_mmc_softc *); 163 static int aw_mmc_reset(struct aw_mmc_softc *); 164 static int aw_mmc_init(struct aw_mmc_softc *); 165 static void aw_mmc_intr(void *); 166 static int aw_mmc_update_clock(struct aw_mmc_softc *, uint32_t); 167 168 static void aw_mmc_print_error(uint32_t); 169 static int aw_mmc_update_ios(device_t, device_t); 170 static int aw_mmc_request(device_t, device_t, struct mmc_request *); 171 static int aw_mmc_get_ro(device_t, device_t); 172 static int aw_mmc_acquire_host(device_t, device_t); 173 static int aw_mmc_release_host(device_t, device_t); 174 #ifdef MMCCAM 175 static void aw_mmc_cam_action(struct cam_sim *, union ccb *); 176 static void aw_mmc_cam_poll(struct cam_sim *); 177 static int aw_mmc_cam_settran_settings(struct aw_mmc_softc *, union ccb *); 178 static int aw_mmc_cam_request(struct aw_mmc_softc *, union ccb *); 179 static void aw_mmc_cam_handle_mmcio(struct cam_sim *, union ccb *); 180 #endif 181 182 #define AW_MMC_LOCK(_sc) mtx_lock(&(_sc)->aw_mtx) 183 #define AW_MMC_UNLOCK(_sc) mtx_unlock(&(_sc)->aw_mtx) 184 #define AW_MMC_READ_4(_sc, _reg) \ 185 bus_read_4((_sc)->aw_res[AW_MMC_MEMRES], _reg) 186 #define AW_MMC_WRITE_4(_sc, _reg, _value) \ 187 bus_write_4((_sc)->aw_res[AW_MMC_MEMRES], _reg, _value) 188 189 #ifdef MMCCAM 190 static void 191 aw_mmc_cam_handle_mmcio(struct cam_sim *sim, union ccb *ccb) 192 { 193 struct aw_mmc_softc *sc; 194 195 sc = cam_sim_softc(sim); 196 197 aw_mmc_cam_request(sc, ccb); 198 } 199 200 static void 201 aw_mmc_cam_action(struct cam_sim *sim, union ccb *ccb) 202 { 203 struct aw_mmc_softc *sc; 204 205 sc = cam_sim_softc(sim); 206 if (sc == NULL) { 207 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 208 xpt_done(ccb); 209 return; 210 } 211 212 mtx_assert(&sc->sim_mtx, MA_OWNED); 213 214 switch (ccb->ccb_h.func_code) { 215 case XPT_PATH_INQ: 216 { 217 struct ccb_pathinq *cpi; 218 219 cpi = &ccb->cpi; 220 cpi->version_num = 1; 221 cpi->hba_inquiry = 0; 222 cpi->target_sprt = 0; 223 cpi->hba_misc = PIM_NOBUSRESET | PIM_SEQSCAN; 224 cpi->hba_eng_cnt = 0; 225 cpi->max_target = 0; 226 cpi->max_lun = 0; 227 cpi->initiator_id = 1; 228 cpi->maxio = (sc->aw_mmc_conf->dma_xferlen * 229 AW_MMC_DMA_SEGS) / MMC_SECTOR_SIZE; 230 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 231 strncpy(cpi->hba_vid, "Deglitch Networks", HBA_IDLEN); 232 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 233 cpi->unit_number = cam_sim_unit(sim); 234 cpi->bus_id = cam_sim_bus(sim); 235 cpi->protocol = PROTO_MMCSD; 236 cpi->protocol_version = SCSI_REV_0; 237 cpi->transport = XPORT_MMCSD; 238 cpi->transport_version = 1; 239 240 cpi->ccb_h.status = CAM_REQ_CMP; 241 break; 242 } 243 case XPT_GET_TRAN_SETTINGS: 244 { 245 struct ccb_trans_settings *cts = &ccb->cts; 246 247 if (bootverbose) 248 device_printf(sc->aw_dev, "Got XPT_GET_TRAN_SETTINGS\n"); 249 250 cts->protocol = PROTO_MMCSD; 251 cts->protocol_version = 1; 252 cts->transport = XPORT_MMCSD; 253 cts->transport_version = 1; 254 cts->xport_specific.valid = 0; 255 cts->proto_specific.mmc.host_ocr = sc->aw_host.host_ocr; 256 cts->proto_specific.mmc.host_f_min = sc->aw_host.f_min; 257 cts->proto_specific.mmc.host_f_max = sc->aw_host.f_max; 258 cts->proto_specific.mmc.host_caps = sc->aw_host.caps; 259 cts->proto_specific.mmc.host_max_data = (sc->aw_mmc_conf->dma_xferlen * 260 AW_MMC_DMA_SEGS) / MMC_SECTOR_SIZE; 261 memcpy(&cts->proto_specific.mmc.ios, &sc->aw_host.ios, sizeof(struct mmc_ios)); 262 ccb->ccb_h.status = CAM_REQ_CMP; 263 break; 264 } 265 case XPT_SET_TRAN_SETTINGS: 266 { 267 if (bootverbose) 268 device_printf(sc->aw_dev, "Got XPT_SET_TRAN_SETTINGS\n"); 269 aw_mmc_cam_settran_settings(sc, ccb); 270 ccb->ccb_h.status = CAM_REQ_CMP; 271 break; 272 } 273 case XPT_RESET_BUS: 274 if (bootverbose) 275 device_printf(sc->aw_dev, "Got XPT_RESET_BUS, ACK it...\n"); 276 ccb->ccb_h.status = CAM_REQ_CMP; 277 break; 278 case XPT_MMC_IO: 279 /* 280 * Here is the HW-dependent part of 281 * sending the command to the underlying h/w 282 * At some point in the future an interrupt comes. 283 * Then the request will be marked as completed. 284 */ 285 ccb->ccb_h.status = CAM_REQ_INPROG; 286 287 aw_mmc_cam_handle_mmcio(sim, ccb); 288 return; 289 /* NOTREACHED */ 290 break; 291 default: 292 ccb->ccb_h.status = CAM_REQ_INVALID; 293 break; 294 } 295 xpt_done(ccb); 296 return; 297 } 298 299 static void 300 aw_mmc_cam_poll(struct cam_sim *sim) 301 { 302 return; 303 } 304 305 static int 306 aw_mmc_cam_settran_settings(struct aw_mmc_softc *sc, union ccb *ccb) 307 { 308 struct mmc_ios *ios; 309 struct mmc_ios *new_ios; 310 struct ccb_trans_settings_mmc *cts; 311 312 ios = &sc->aw_host.ios; 313 314 cts = &ccb->cts.proto_specific.mmc; 315 new_ios = &cts->ios; 316 317 /* Update only requested fields */ 318 if (cts->ios_valid & MMC_CLK) { 319 ios->clock = new_ios->clock; 320 device_printf(sc->aw_dev, "Clock => %d\n", ios->clock); 321 } 322 if (cts->ios_valid & MMC_VDD) { 323 ios->vdd = new_ios->vdd; 324 device_printf(sc->aw_dev, "VDD => %d\n", ios->vdd); 325 } 326 if (cts->ios_valid & MMC_CS) { 327 ios->chip_select = new_ios->chip_select; 328 device_printf(sc->aw_dev, "CS => %d\n", ios->chip_select); 329 } 330 if (cts->ios_valid & MMC_BW) { 331 ios->bus_width = new_ios->bus_width; 332 device_printf(sc->aw_dev, "Bus width => %d\n", ios->bus_width); 333 } 334 if (cts->ios_valid & MMC_PM) { 335 ios->power_mode = new_ios->power_mode; 336 device_printf(sc->aw_dev, "Power mode => %d\n", ios->power_mode); 337 } 338 if (cts->ios_valid & MMC_BT) { 339 ios->timing = new_ios->timing; 340 device_printf(sc->aw_dev, "Timing => %d\n", ios->timing); 341 } 342 if (cts->ios_valid & MMC_BM) { 343 ios->bus_mode = new_ios->bus_mode; 344 device_printf(sc->aw_dev, "Bus mode => %d\n", ios->bus_mode); 345 } 346 347 return (aw_mmc_update_ios(sc->aw_dev, NULL)); 348 } 349 350 static int 351 aw_mmc_cam_request(struct aw_mmc_softc *sc, union ccb *ccb) 352 { 353 struct ccb_mmcio *mmcio; 354 355 mmcio = &ccb->mmcio; 356 357 AW_MMC_LOCK(sc); 358 359 #ifdef DEBUG 360 if (__predict_false(bootverbose)) { 361 device_printf(sc->aw_dev, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 362 mmcio->cmd.opcode, mmcio->cmd.arg, mmcio->cmd.flags, 363 mmcio->cmd.data != NULL ? (unsigned int) mmcio->cmd.data->len : 0, 364 mmcio->cmd.data != NULL ? mmcio->cmd.data->flags: 0); 365 } 366 #endif 367 if (mmcio->cmd.data != NULL) { 368 if (mmcio->cmd.data->len == 0 || mmcio->cmd.data->flags == 0) 369 panic("data->len = %d, data->flags = %d -- something is b0rked", 370 (int)mmcio->cmd.data->len, mmcio->cmd.data->flags); 371 } 372 if (sc->ccb != NULL) { 373 device_printf(sc->aw_dev, "Controller still has an active command\n"); 374 return (EBUSY); 375 } 376 sc->ccb = ccb; 377 /* aw_mmc_request locks again */ 378 AW_MMC_UNLOCK(sc); 379 aw_mmc_request(sc->aw_dev, NULL, NULL); 380 381 return (0); 382 } 383 #endif /* MMCCAM */ 384 385 static int 386 aw_mmc_probe(device_t dev) 387 { 388 389 if (!ofw_bus_status_okay(dev)) 390 return (ENXIO); 391 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 392 return (ENXIO); 393 394 device_set_desc(dev, "Allwinner Integrated MMC/SD controller"); 395 396 return (BUS_PROBE_DEFAULT); 397 } 398 399 static int 400 aw_mmc_attach(device_t dev) 401 { 402 device_t child; 403 struct aw_mmc_softc *sc; 404 struct sysctl_ctx_list *ctx; 405 struct sysctl_oid_list *tree; 406 uint32_t bus_width, max_freq; 407 phandle_t node; 408 int error; 409 410 node = ofw_bus_get_node(dev); 411 sc = device_get_softc(dev); 412 sc->aw_dev = dev; 413 414 sc->aw_mmc_conf = (struct aw_mmc_conf *)ofw_bus_search_compatible(dev, compat_data)->ocd_data; 415 416 #ifndef MMCCAM 417 sc->aw_req = NULL; 418 #endif 419 if (bus_alloc_resources(dev, aw_mmc_res_spec, sc->aw_res) != 0) { 420 device_printf(dev, "cannot allocate device resources\n"); 421 return (ENXIO); 422 } 423 if (bus_setup_intr(dev, sc->aw_res[AW_MMC_IRQRES], 424 INTR_TYPE_MISC | INTR_MPSAFE, NULL, aw_mmc_intr, sc, 425 &sc->aw_intrhand)) { 426 bus_release_resources(dev, aw_mmc_res_spec, sc->aw_res); 427 device_printf(dev, "cannot setup interrupt handler\n"); 428 return (ENXIO); 429 } 430 mtx_init(&sc->aw_mtx, device_get_nameunit(sc->aw_dev), "aw_mmc", 431 MTX_DEF); 432 callout_init_mtx(&sc->aw_timeoutc, &sc->aw_mtx, 0); 433 434 /* De-assert reset */ 435 if (hwreset_get_by_ofw_name(dev, 0, "ahb", &sc->aw_rst_ahb) == 0) { 436 error = hwreset_deassert(sc->aw_rst_ahb); 437 if (error != 0) { 438 device_printf(dev, "cannot de-assert reset\n"); 439 goto fail; 440 } 441 } 442 443 /* Activate the module clock. */ 444 error = clk_get_by_ofw_name(dev, 0, "ahb", &sc->aw_clk_ahb); 445 if (error != 0) { 446 device_printf(dev, "cannot get ahb clock\n"); 447 goto fail; 448 } 449 error = clk_enable(sc->aw_clk_ahb); 450 if (error != 0) { 451 device_printf(dev, "cannot enable ahb clock\n"); 452 goto fail; 453 } 454 error = clk_get_by_ofw_name(dev, 0, "mmc", &sc->aw_clk_mmc); 455 if (error != 0) { 456 device_printf(dev, "cannot get mmc clock\n"); 457 goto fail; 458 } 459 error = clk_set_freq(sc->aw_clk_mmc, CARD_ID_FREQUENCY, 460 CLK_SET_ROUND_DOWN); 461 if (error != 0) { 462 device_printf(dev, "cannot init mmc clock\n"); 463 goto fail; 464 } 465 error = clk_enable(sc->aw_clk_mmc); 466 if (error != 0) { 467 device_printf(dev, "cannot enable mmc clock\n"); 468 goto fail; 469 } 470 471 sc->aw_timeout = 10; 472 ctx = device_get_sysctl_ctx(dev); 473 tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 474 SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "req_timeout", CTLFLAG_RW, 475 &sc->aw_timeout, 0, "Request timeout in seconds"); 476 477 /* Soft Reset controller. */ 478 if (aw_mmc_reset(sc) != 0) { 479 device_printf(dev, "cannot reset the controller\n"); 480 goto fail; 481 } 482 483 if (aw_mmc_setup_dma(sc) != 0) { 484 device_printf(sc->aw_dev, "Couldn't setup DMA!\n"); 485 goto fail; 486 } 487 488 if (OF_getencprop(node, "bus-width", &bus_width, sizeof(uint32_t)) <= 0) 489 bus_width = 4; 490 491 if (regulator_get_by_ofw_property(dev, 0, "vmmc-supply", 492 &sc->aw_reg_vmmc) == 0) { 493 if (bootverbose) 494 device_printf(dev, "vmmc-supply regulator found\n"); 495 } 496 if (regulator_get_by_ofw_property(dev, 0, "vqmmc-supply", 497 &sc->aw_reg_vqmmc) == 0 && bootverbose) { 498 if (bootverbose) 499 device_printf(dev, "vqmmc-supply regulator found\n"); 500 } 501 502 sc->aw_host.f_min = 400000; 503 504 if (OF_getencprop(node, "max-frequency", &max_freq, 505 sizeof(uint32_t)) <= 0) 506 max_freq = 52000000; 507 sc->aw_host.f_max = max_freq; 508 509 sc->aw_host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340; 510 sc->aw_host.caps = MMC_CAP_HSPEED | MMC_CAP_UHS_SDR12 | 511 MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR50 | 512 MMC_CAP_UHS_DDR50 | MMC_CAP_MMC_DDR52; 513 514 if (sc->aw_reg_vqmmc != NULL) { 515 if (regulator_check_voltage(sc->aw_reg_vqmmc, 1800000) == 0) 516 sc->aw_host.caps |= MMC_CAP_SIGNALING_180; 517 if (regulator_check_voltage(sc->aw_reg_vqmmc, 3300000) == 0) 518 sc->aw_host.caps |= MMC_CAP_SIGNALING_330; 519 } else 520 sc->aw_host.caps |= MMC_CAP_SIGNALING_330; 521 522 if (bus_width >= 4) 523 sc->aw_host.caps |= MMC_CAP_4_BIT_DATA; 524 if (bus_width >= 8) 525 sc->aw_host.caps |= MMC_CAP_8_BIT_DATA; 526 527 #ifdef MMCCAM 528 child = NULL; /* Not used by MMCCAM, need to silence compiler warnings */ 529 sc->ccb = NULL; 530 if ((sc->devq = cam_simq_alloc(1)) == NULL) { 531 goto fail; 532 } 533 534 mtx_init(&sc->sim_mtx, "awmmcsim", NULL, MTX_DEF); 535 sc->sim = cam_sim_alloc_dev(aw_mmc_cam_action, aw_mmc_cam_poll, 536 "aw_mmc_sim", sc, dev, 537 &sc->sim_mtx, 1, 1, sc->devq); 538 539 if (sc->sim == NULL) { 540 cam_simq_free(sc->devq); 541 device_printf(dev, "cannot allocate CAM SIM\n"); 542 goto fail; 543 } 544 545 mtx_lock(&sc->sim_mtx); 546 if (xpt_bus_register(sc->sim, sc->aw_dev, 0) != 0) { 547 device_printf(dev, "cannot register SCSI pass-through bus\n"); 548 cam_sim_free(sc->sim, FALSE); 549 cam_simq_free(sc->devq); 550 mtx_unlock(&sc->sim_mtx); 551 goto fail; 552 } 553 554 mtx_unlock(&sc->sim_mtx); 555 #else /* !MMCCAM */ 556 child = device_add_child(dev, "mmc", -1); 557 if (child == NULL) { 558 device_printf(dev, "attaching MMC bus failed!\n"); 559 goto fail; 560 } 561 if (device_probe_and_attach(child) != 0) { 562 device_printf(dev, "attaching MMC child failed!\n"); 563 device_delete_child(dev, child); 564 goto fail; 565 } 566 #endif /* MMCCAM */ 567 return (0); 568 569 fail: 570 callout_drain(&sc->aw_timeoutc); 571 mtx_destroy(&sc->aw_mtx); 572 bus_teardown_intr(dev, sc->aw_res[AW_MMC_IRQRES], sc->aw_intrhand); 573 bus_release_resources(dev, aw_mmc_res_spec, sc->aw_res); 574 575 #ifdef MMCCAM 576 if (sc->sim != NULL) { 577 mtx_lock(&sc->sim_mtx); 578 xpt_bus_deregister(cam_sim_path(sc->sim)); 579 cam_sim_free(sc->sim, FALSE); 580 mtx_unlock(&sc->sim_mtx); 581 } 582 583 if (sc->devq != NULL) 584 cam_simq_free(sc->devq); 585 #endif 586 return (ENXIO); 587 } 588 589 static int 590 aw_mmc_detach(device_t dev) 591 { 592 593 return (EBUSY); 594 } 595 596 static void 597 aw_dma_desc_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err) 598 { 599 struct aw_mmc_softc *sc; 600 601 sc = (struct aw_mmc_softc *)arg; 602 if (err) { 603 sc->aw_dma_map_err = err; 604 return; 605 } 606 sc->aw_dma_desc_phys = segs[0].ds_addr; 607 } 608 609 static int 610 aw_mmc_setup_dma(struct aw_mmc_softc *sc) 611 { 612 int error; 613 614 /* Allocate the DMA descriptor memory. */ 615 error = bus_dma_tag_create( 616 bus_get_dma_tag(sc->aw_dev), /* parent */ 617 AW_MMC_DMA_ALIGN, 0, /* align, boundary */ 618 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 619 BUS_SPACE_MAXADDR, /* highaddr */ 620 NULL, NULL, /* filter, filterarg*/ 621 AW_MMC_DMA_DESC_SIZE, 1, /* maxsize, nsegment */ 622 AW_MMC_DMA_DESC_SIZE, /* maxsegsize */ 623 0, /* flags */ 624 NULL, NULL, /* lock, lockarg*/ 625 &sc->aw_dma_tag); 626 if (error) 627 return (error); 628 629 error = bus_dmamem_alloc(sc->aw_dma_tag, &sc->aw_dma_desc, 630 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, 631 &sc->aw_dma_map); 632 if (error) 633 return (error); 634 635 error = bus_dmamap_load(sc->aw_dma_tag, 636 sc->aw_dma_map, 637 sc->aw_dma_desc, AW_MMC_DMA_DESC_SIZE, 638 aw_dma_desc_cb, sc, 0); 639 if (error) 640 return (error); 641 if (sc->aw_dma_map_err) 642 return (sc->aw_dma_map_err); 643 644 /* Create the DMA map for data transfers. */ 645 error = bus_dma_tag_create( 646 bus_get_dma_tag(sc->aw_dev), /* parent */ 647 AW_MMC_DMA_ALIGN, 0, /* align, boundary */ 648 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 649 BUS_SPACE_MAXADDR, /* highaddr */ 650 NULL, NULL, /* filter, filterarg*/ 651 sc->aw_mmc_conf->dma_xferlen * 652 AW_MMC_DMA_SEGS, AW_MMC_DMA_SEGS, /* maxsize, nsegments */ 653 sc->aw_mmc_conf->dma_xferlen, /* maxsegsize */ 654 BUS_DMA_ALLOCNOW, /* flags */ 655 NULL, NULL, /* lock, lockarg*/ 656 &sc->aw_dma_buf_tag); 657 if (error) 658 return (error); 659 error = bus_dmamap_create(sc->aw_dma_buf_tag, 0, 660 &sc->aw_dma_buf_map); 661 if (error) 662 return (error); 663 664 return (0); 665 } 666 667 static void 668 aw_dma_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err) 669 { 670 int i; 671 struct aw_mmc_dma_desc *dma_desc; 672 struct aw_mmc_softc *sc; 673 674 sc = (struct aw_mmc_softc *)arg; 675 sc->aw_dma_map_err = err; 676 677 if (err) 678 return; 679 680 dma_desc = sc->aw_dma_desc; 681 for (i = 0; i < nsegs; i++) { 682 if (segs[i].ds_len == sc->aw_mmc_conf->dma_xferlen) 683 dma_desc[i].buf_size = 0; /* Size of 0 indicate max len */ 684 else 685 dma_desc[i].buf_size = segs[i].ds_len; 686 dma_desc[i].buf_addr = segs[i].ds_addr; 687 dma_desc[i].config = AW_MMC_DMA_CONFIG_CH | 688 AW_MMC_DMA_CONFIG_OWN | AW_MMC_DMA_CONFIG_DIC; 689 690 dma_desc[i].next = sc->aw_dma_desc_phys + 691 ((i + 1) * sizeof(struct aw_mmc_dma_desc)); 692 } 693 694 dma_desc[0].config |= AW_MMC_DMA_CONFIG_FD; 695 dma_desc[nsegs - 1].config |= AW_MMC_DMA_CONFIG_LD | 696 AW_MMC_DMA_CONFIG_ER; 697 dma_desc[nsegs - 1].config &= ~AW_MMC_DMA_CONFIG_DIC; 698 dma_desc[nsegs - 1].next = 0; 699 } 700 701 static int 702 aw_mmc_prepare_dma(struct aw_mmc_softc *sc) 703 { 704 bus_dmasync_op_t sync_op; 705 int error; 706 struct mmc_command *cmd; 707 uint32_t val; 708 709 #ifdef MMCCAM 710 cmd = &sc->ccb->mmcio.cmd; 711 #else 712 cmd = sc->aw_req->cmd; 713 #endif 714 if (cmd->data->len > (sc->aw_mmc_conf->dma_xferlen * AW_MMC_DMA_SEGS)) 715 return (EFBIG); 716 error = bus_dmamap_load(sc->aw_dma_buf_tag, sc->aw_dma_buf_map, 717 cmd->data->data, cmd->data->len, aw_dma_cb, sc, 0); 718 if (error) 719 return (error); 720 if (sc->aw_dma_map_err) 721 return (sc->aw_dma_map_err); 722 723 if (cmd->data->flags & MMC_DATA_WRITE) 724 sync_op = BUS_DMASYNC_PREWRITE; 725 else 726 sync_op = BUS_DMASYNC_PREREAD; 727 bus_dmamap_sync(sc->aw_dma_buf_tag, sc->aw_dma_buf_map, sync_op); 728 bus_dmamap_sync(sc->aw_dma_tag, sc->aw_dma_map, BUS_DMASYNC_PREWRITE); 729 730 /* Enable DMA */ 731 val = AW_MMC_READ_4(sc, AW_MMC_GCTL); 732 val &= ~AW_MMC_GCTL_FIFO_AC_MOD; 733 val |= AW_MMC_GCTL_DMA_ENB; 734 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val); 735 736 /* Reset DMA */ 737 val |= AW_MMC_GCTL_DMA_RST; 738 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val); 739 740 AW_MMC_WRITE_4(sc, AW_MMC_DMAC, AW_MMC_DMAC_IDMAC_SOFT_RST); 741 AW_MMC_WRITE_4(sc, AW_MMC_DMAC, 742 AW_MMC_DMAC_IDMAC_IDMA_ON | AW_MMC_DMAC_IDMAC_FIX_BURST); 743 744 /* Enable RX or TX DMA interrupt */ 745 val = AW_MMC_READ_4(sc, AW_MMC_IDIE); 746 if (cmd->data->flags & MMC_DATA_WRITE) 747 val |= AW_MMC_IDST_TX_INT; 748 else 749 val |= AW_MMC_IDST_RX_INT; 750 AW_MMC_WRITE_4(sc, AW_MMC_IDIE, val); 751 752 /* Set DMA descritptor list address */ 753 AW_MMC_WRITE_4(sc, AW_MMC_DLBA, sc->aw_dma_desc_phys); 754 755 /* FIFO trigger level */ 756 AW_MMC_WRITE_4(sc, AW_MMC_FWLR, AW_MMC_DMA_FTRGLEVEL); 757 758 return (0); 759 } 760 761 static int 762 aw_mmc_reset(struct aw_mmc_softc *sc) 763 { 764 uint32_t reg; 765 int timeout; 766 767 reg = AW_MMC_READ_4(sc, AW_MMC_GCTL); 768 reg |= AW_MMC_GCTL_RESET; 769 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg); 770 timeout = AW_MMC_RESET_RETRY; 771 while (--timeout > 0) { 772 if ((AW_MMC_READ_4(sc, AW_MMC_GCTL) & AW_MMC_GCTL_RESET) == 0) 773 break; 774 DELAY(100); 775 } 776 if (timeout == 0) 777 return (ETIMEDOUT); 778 779 return (0); 780 } 781 782 static int 783 aw_mmc_init(struct aw_mmc_softc *sc) 784 { 785 uint32_t reg; 786 int ret; 787 788 ret = aw_mmc_reset(sc); 789 if (ret != 0) 790 return (ret); 791 792 /* Set the timeout. */ 793 AW_MMC_WRITE_4(sc, AW_MMC_TMOR, 794 AW_MMC_TMOR_DTO_LMT_SHIFT(AW_MMC_TMOR_DTO_LMT_MASK) | 795 AW_MMC_TMOR_RTO_LMT_SHIFT(AW_MMC_TMOR_RTO_LMT_MASK)); 796 797 /* Unmask interrupts. */ 798 AW_MMC_WRITE_4(sc, AW_MMC_IMKR, 0); 799 800 /* Clear pending interrupts. */ 801 AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff); 802 803 /* Debug register, undocumented */ 804 AW_MMC_WRITE_4(sc, AW_MMC_DBGC, 0xdeb); 805 806 /* Function select register */ 807 AW_MMC_WRITE_4(sc, AW_MMC_FUNS, 0xceaa0000); 808 809 AW_MMC_WRITE_4(sc, AW_MMC_IDST, 0xffffffff); 810 811 /* Enable interrupts and disable AHB access. */ 812 reg = AW_MMC_READ_4(sc, AW_MMC_GCTL); 813 reg |= AW_MMC_GCTL_INT_ENB; 814 reg &= ~AW_MMC_GCTL_FIFO_AC_MOD; 815 reg &= ~AW_MMC_GCTL_WAIT_MEM_ACCESS; 816 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg); 817 818 return (0); 819 } 820 821 static void 822 aw_mmc_req_done(struct aw_mmc_softc *sc) 823 { 824 struct mmc_command *cmd; 825 #ifdef MMCCAM 826 union ccb *ccb; 827 #else 828 struct mmc_request *req; 829 #endif 830 uint32_t val, mask; 831 int retry; 832 833 #ifdef MMCCAM 834 ccb = sc->ccb; 835 cmd = &ccb->mmcio.cmd; 836 #else 837 cmd = sc->aw_req->cmd; 838 #endif 839 #ifdef DEBUG 840 if (bootverbose) { 841 device_printf(sc->aw_dev, "%s: cmd %d err %d\n", __func__, cmd->opcode, cmd->error); 842 } 843 #endif 844 if (cmd->error != MMC_ERR_NONE) { 845 /* Reset the FIFO and DMA engines. */ 846 mask = AW_MMC_GCTL_FIFO_RST | AW_MMC_GCTL_DMA_RST; 847 val = AW_MMC_READ_4(sc, AW_MMC_GCTL); 848 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val | mask); 849 850 retry = AW_MMC_RESET_RETRY; 851 while (--retry > 0) { 852 if ((AW_MMC_READ_4(sc, AW_MMC_GCTL) & 853 AW_MMC_GCTL_RESET) == 0) 854 break; 855 DELAY(100); 856 } 857 if (retry == 0) 858 device_printf(sc->aw_dev, 859 "timeout resetting DMA/FIFO\n"); 860 aw_mmc_update_clock(sc, 1); 861 } 862 863 callout_stop(&sc->aw_timeoutc); 864 sc->aw_intr = 0; 865 sc->aw_resid = 0; 866 sc->aw_dma_map_err = 0; 867 sc->aw_intr_wait = 0; 868 #ifdef MMCCAM 869 sc->ccb = NULL; 870 ccb->ccb_h.status = 871 (ccb->mmcio.cmd.error == 0 ? CAM_REQ_CMP : CAM_REQ_CMP_ERR); 872 xpt_done(ccb); 873 #else 874 req = sc->aw_req; 875 sc->aw_req = NULL; 876 req->done(req); 877 #endif 878 } 879 880 static void 881 aw_mmc_req_ok(struct aw_mmc_softc *sc) 882 { 883 int timeout; 884 struct mmc_command *cmd; 885 uint32_t status; 886 887 timeout = 1000; 888 while (--timeout > 0) { 889 status = AW_MMC_READ_4(sc, AW_MMC_STAR); 890 if ((status & AW_MMC_STAR_CARD_BUSY) == 0) 891 break; 892 DELAY(1000); 893 } 894 #ifdef MMCCAM 895 cmd = &sc->ccb->mmcio.cmd; 896 #else 897 cmd = sc->aw_req->cmd; 898 #endif 899 if (timeout == 0) { 900 cmd->error = MMC_ERR_FAILED; 901 aw_mmc_req_done(sc); 902 return; 903 } 904 if (cmd->flags & MMC_RSP_PRESENT) { 905 if (cmd->flags & MMC_RSP_136) { 906 cmd->resp[0] = AW_MMC_READ_4(sc, AW_MMC_RESP3); 907 cmd->resp[1] = AW_MMC_READ_4(sc, AW_MMC_RESP2); 908 cmd->resp[2] = AW_MMC_READ_4(sc, AW_MMC_RESP1); 909 cmd->resp[3] = AW_MMC_READ_4(sc, AW_MMC_RESP0); 910 } else 911 cmd->resp[0] = AW_MMC_READ_4(sc, AW_MMC_RESP0); 912 } 913 /* All data has been transferred ? */ 914 if (cmd->data != NULL && (sc->aw_resid << 2) < cmd->data->len) 915 cmd->error = MMC_ERR_FAILED; 916 aw_mmc_req_done(sc); 917 } 918 919 920 static inline void 921 set_mmc_error(struct aw_mmc_softc *sc, int error_code) 922 { 923 #ifdef MMCCAM 924 sc->ccb->mmcio.cmd.error = error_code; 925 #else 926 sc->aw_req->cmd->error = error_code; 927 #endif 928 } 929 930 static void 931 aw_mmc_timeout(void *arg) 932 { 933 struct aw_mmc_softc *sc; 934 935 sc = (struct aw_mmc_softc *)arg; 936 #ifdef MMCCAM 937 if (sc->ccb != NULL) { 938 #else 939 if (sc->aw_req != NULL) { 940 #endif 941 device_printf(sc->aw_dev, "controller timeout\n"); 942 set_mmc_error(sc, MMC_ERR_TIMEOUT); 943 aw_mmc_req_done(sc); 944 } else 945 device_printf(sc->aw_dev, 946 "Spurious timeout - no active request\n"); 947 } 948 949 static void 950 aw_mmc_print_error(uint32_t err) 951 { 952 if(err & AW_MMC_INT_RESP_ERR) 953 printf("AW_MMC_INT_RESP_ERR "); 954 if (err & AW_MMC_INT_RESP_CRC_ERR) 955 printf("AW_MMC_INT_RESP_CRC_ERR "); 956 if (err & AW_MMC_INT_DATA_CRC_ERR) 957 printf("AW_MMC_INT_DATA_CRC_ERR "); 958 if (err & AW_MMC_INT_RESP_TIMEOUT) 959 printf("AW_MMC_INT_RESP_TIMEOUT "); 960 if (err & AW_MMC_INT_FIFO_RUN_ERR) 961 printf("AW_MMC_INT_FIFO_RUN_ERR "); 962 if (err & AW_MMC_INT_CMD_BUSY) 963 printf("AW_MMC_INT_CMD_BUSY "); 964 if (err & AW_MMC_INT_DATA_START_ERR) 965 printf("AW_MMC_INT_DATA_START_ERR "); 966 if (err & AW_MMC_INT_DATA_END_BIT_ERR) 967 printf("AW_MMC_INT_DATA_END_BIT_ERR"); 968 printf("\n"); 969 } 970 971 static void 972 aw_mmc_intr(void *arg) 973 { 974 bus_dmasync_op_t sync_op; 975 struct aw_mmc_softc *sc; 976 struct mmc_data *data; 977 uint32_t idst, imask, rint; 978 979 sc = (struct aw_mmc_softc *)arg; 980 AW_MMC_LOCK(sc); 981 rint = AW_MMC_READ_4(sc, AW_MMC_RISR); 982 idst = AW_MMC_READ_4(sc, AW_MMC_IDST); 983 imask = AW_MMC_READ_4(sc, AW_MMC_IMKR); 984 if (idst == 0 && imask == 0 && rint == 0) { 985 AW_MMC_UNLOCK(sc); 986 return; 987 } 988 #ifdef DEBUG 989 device_printf(sc->aw_dev, "idst: %#x, imask: %#x, rint: %#x\n", 990 idst, imask, rint); 991 #endif 992 #ifdef MMCCAM 993 if (sc->ccb == NULL) { 994 #else 995 if (sc->aw_req == NULL) { 996 #endif 997 device_printf(sc->aw_dev, 998 "Spurious interrupt - no active request, rint: 0x%08X\n", 999 rint); 1000 aw_mmc_print_error(rint); 1001 goto end; 1002 } 1003 if (rint & AW_MMC_INT_ERR_BIT) { 1004 if (bootverbose) 1005 device_printf(sc->aw_dev, "error rint: 0x%08X\n", rint); 1006 aw_mmc_print_error(rint); 1007 if (rint & AW_MMC_INT_RESP_TIMEOUT) 1008 set_mmc_error(sc, MMC_ERR_TIMEOUT); 1009 else 1010 set_mmc_error(sc, MMC_ERR_FAILED); 1011 aw_mmc_req_done(sc); 1012 goto end; 1013 } 1014 if (idst & AW_MMC_IDST_ERROR) { 1015 device_printf(sc->aw_dev, "error idst: 0x%08x\n", idst); 1016 set_mmc_error(sc, MMC_ERR_FAILED); 1017 aw_mmc_req_done(sc); 1018 goto end; 1019 } 1020 1021 sc->aw_intr |= rint; 1022 #ifdef MMCCAM 1023 data = sc->ccb->mmcio.cmd.data; 1024 #else 1025 data = sc->aw_req->cmd->data; 1026 #endif 1027 if (data != NULL && (idst & AW_MMC_IDST_COMPLETE) != 0) { 1028 if (data->flags & MMC_DATA_WRITE) 1029 sync_op = BUS_DMASYNC_POSTWRITE; 1030 else 1031 sync_op = BUS_DMASYNC_POSTREAD; 1032 bus_dmamap_sync(sc->aw_dma_buf_tag, sc->aw_dma_buf_map, 1033 sync_op); 1034 bus_dmamap_sync(sc->aw_dma_tag, sc->aw_dma_map, 1035 BUS_DMASYNC_POSTWRITE); 1036 bus_dmamap_unload(sc->aw_dma_buf_tag, sc->aw_dma_buf_map); 1037 sc->aw_resid = data->len >> 2; 1038 } 1039 if ((sc->aw_intr & sc->aw_intr_wait) == sc->aw_intr_wait) 1040 aw_mmc_req_ok(sc); 1041 1042 end: 1043 AW_MMC_WRITE_4(sc, AW_MMC_IDST, idst); 1044 AW_MMC_WRITE_4(sc, AW_MMC_RISR, rint); 1045 AW_MMC_UNLOCK(sc); 1046 } 1047 1048 static int 1049 aw_mmc_request(device_t bus, device_t child, struct mmc_request *req) 1050 { 1051 int blksz; 1052 struct aw_mmc_softc *sc; 1053 struct mmc_command *cmd; 1054 uint32_t cmdreg, imask; 1055 int err; 1056 1057 sc = device_get_softc(bus); 1058 1059 AW_MMC_LOCK(sc); 1060 #ifdef MMCCAM 1061 KASSERT(req == NULL, ("req should be NULL in MMCCAM case!")); 1062 /* 1063 * For MMCCAM, sc->ccb has been NULL-checked and populated 1064 * by aw_mmc_cam_request() already. 1065 */ 1066 cmd = &sc->ccb->mmcio.cmd; 1067 #else 1068 if (sc->aw_req) { 1069 AW_MMC_UNLOCK(sc); 1070 return (EBUSY); 1071 } 1072 sc->aw_req = req; 1073 cmd = req->cmd; 1074 1075 #ifdef DEBUG 1076 if (bootverbose) 1077 device_printf(sc->aw_dev, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 1078 cmd->opcode, cmd->arg, cmd->flags, 1079 cmd->data != NULL ? (unsigned int)cmd->data->len : 0, 1080 cmd->data != NULL ? cmd->data->flags: 0); 1081 #endif 1082 #endif 1083 cmdreg = AW_MMC_CMDR_LOAD; 1084 imask = AW_MMC_INT_ERR_BIT; 1085 sc->aw_intr_wait = 0; 1086 sc->aw_intr = 0; 1087 sc->aw_resid = 0; 1088 cmd->error = MMC_ERR_NONE; 1089 1090 if (cmd->opcode == MMC_GO_IDLE_STATE) 1091 cmdreg |= AW_MMC_CMDR_SEND_INIT_SEQ; 1092 1093 if (cmd->flags & MMC_RSP_PRESENT) 1094 cmdreg |= AW_MMC_CMDR_RESP_RCV; 1095 if (cmd->flags & MMC_RSP_136) 1096 cmdreg |= AW_MMC_CMDR_LONG_RESP; 1097 if (cmd->flags & MMC_RSP_CRC) 1098 cmdreg |= AW_MMC_CMDR_CHK_RESP_CRC; 1099 1100 if (cmd->data) { 1101 cmdreg |= AW_MMC_CMDR_DATA_TRANS | AW_MMC_CMDR_WAIT_PRE_OVER; 1102 1103 if (cmd->data->flags & MMC_DATA_MULTI) { 1104 cmdreg |= AW_MMC_CMDR_STOP_CMD_FLAG; 1105 imask |= AW_MMC_INT_AUTO_STOP_DONE; 1106 sc->aw_intr_wait |= AW_MMC_INT_AUTO_STOP_DONE; 1107 } else { 1108 sc->aw_intr_wait |= AW_MMC_INT_DATA_OVER; 1109 imask |= AW_MMC_INT_DATA_OVER; 1110 } 1111 if (cmd->data->flags & MMC_DATA_WRITE) 1112 cmdreg |= AW_MMC_CMDR_DIR_WRITE; 1113 #ifdef MMCCAM 1114 if (cmd->data->flags & MMC_DATA_BLOCK_SIZE) { 1115 AW_MMC_WRITE_4(sc, AW_MMC_BKSR, cmd->data->block_size); 1116 AW_MMC_WRITE_4(sc, AW_MMC_BYCR, cmd->data->len); 1117 } else 1118 #endif 1119 { 1120 blksz = min(cmd->data->len, MMC_SECTOR_SIZE); 1121 AW_MMC_WRITE_4(sc, AW_MMC_BKSR, blksz); 1122 AW_MMC_WRITE_4(sc, AW_MMC_BYCR, cmd->data->len); 1123 } 1124 } else { 1125 imask |= AW_MMC_INT_CMD_DONE; 1126 } 1127 1128 /* Enable the interrupts we are interested in */ 1129 AW_MMC_WRITE_4(sc, AW_MMC_IMKR, imask); 1130 AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff); 1131 1132 /* Enable auto stop if needed */ 1133 AW_MMC_WRITE_4(sc, AW_MMC_A12A, 1134 cmdreg & AW_MMC_CMDR_STOP_CMD_FLAG ? 0 : 0xffff); 1135 1136 /* Write the command argument */ 1137 AW_MMC_WRITE_4(sc, AW_MMC_CAGR, cmd->arg); 1138 1139 /* 1140 * If we don't have data start the request 1141 * if we do prepare the dma request and start the request 1142 */ 1143 if (cmd->data == NULL) { 1144 AW_MMC_WRITE_4(sc, AW_MMC_CMDR, cmdreg | cmd->opcode); 1145 } else { 1146 err = aw_mmc_prepare_dma(sc); 1147 if (err != 0) 1148 device_printf(sc->aw_dev, "prepare_dma failed: %d\n", err); 1149 1150 AW_MMC_WRITE_4(sc, AW_MMC_CMDR, cmdreg | cmd->opcode); 1151 } 1152 1153 callout_reset(&sc->aw_timeoutc, sc->aw_timeout * hz, 1154 aw_mmc_timeout, sc); 1155 AW_MMC_UNLOCK(sc); 1156 1157 return (0); 1158 } 1159 1160 static int 1161 aw_mmc_read_ivar(device_t bus, device_t child, int which, 1162 uintptr_t *result) 1163 { 1164 struct aw_mmc_softc *sc; 1165 1166 sc = device_get_softc(bus); 1167 switch (which) { 1168 default: 1169 return (EINVAL); 1170 case MMCBR_IVAR_BUS_MODE: 1171 *(int *)result = sc->aw_host.ios.bus_mode; 1172 break; 1173 case MMCBR_IVAR_BUS_WIDTH: 1174 *(int *)result = sc->aw_host.ios.bus_width; 1175 break; 1176 case MMCBR_IVAR_CHIP_SELECT: 1177 *(int *)result = sc->aw_host.ios.chip_select; 1178 break; 1179 case MMCBR_IVAR_CLOCK: 1180 *(int *)result = sc->aw_host.ios.clock; 1181 break; 1182 case MMCBR_IVAR_F_MIN: 1183 *(int *)result = sc->aw_host.f_min; 1184 break; 1185 case MMCBR_IVAR_F_MAX: 1186 *(int *)result = sc->aw_host.f_max; 1187 break; 1188 case MMCBR_IVAR_HOST_OCR: 1189 *(int *)result = sc->aw_host.host_ocr; 1190 break; 1191 case MMCBR_IVAR_MODE: 1192 *(int *)result = sc->aw_host.mode; 1193 break; 1194 case MMCBR_IVAR_OCR: 1195 *(int *)result = sc->aw_host.ocr; 1196 break; 1197 case MMCBR_IVAR_POWER_MODE: 1198 *(int *)result = sc->aw_host.ios.power_mode; 1199 break; 1200 case MMCBR_IVAR_VDD: 1201 *(int *)result = sc->aw_host.ios.vdd; 1202 break; 1203 case MMCBR_IVAR_VCCQ: 1204 *(int *)result = sc->aw_host.ios.vccq; 1205 break; 1206 case MMCBR_IVAR_CAPS: 1207 *(int *)result = sc->aw_host.caps; 1208 break; 1209 case MMCBR_IVAR_TIMING: 1210 *(int *)result = sc->aw_host.ios.timing; 1211 break; 1212 case MMCBR_IVAR_MAX_DATA: 1213 *(int *)result = (sc->aw_mmc_conf->dma_xferlen * 1214 AW_MMC_DMA_SEGS) / MMC_SECTOR_SIZE; 1215 break; 1216 case MMCBR_IVAR_RETUNE_REQ: 1217 *(int *)result = retune_req_none; 1218 break; 1219 } 1220 1221 return (0); 1222 } 1223 1224 static int 1225 aw_mmc_write_ivar(device_t bus, device_t child, int which, 1226 uintptr_t value) 1227 { 1228 struct aw_mmc_softc *sc; 1229 1230 sc = device_get_softc(bus); 1231 switch (which) { 1232 default: 1233 return (EINVAL); 1234 case MMCBR_IVAR_BUS_MODE: 1235 sc->aw_host.ios.bus_mode = value; 1236 break; 1237 case MMCBR_IVAR_BUS_WIDTH: 1238 sc->aw_host.ios.bus_width = value; 1239 break; 1240 case MMCBR_IVAR_CHIP_SELECT: 1241 sc->aw_host.ios.chip_select = value; 1242 break; 1243 case MMCBR_IVAR_CLOCK: 1244 sc->aw_host.ios.clock = value; 1245 break; 1246 case MMCBR_IVAR_MODE: 1247 sc->aw_host.mode = value; 1248 break; 1249 case MMCBR_IVAR_OCR: 1250 sc->aw_host.ocr = value; 1251 break; 1252 case MMCBR_IVAR_POWER_MODE: 1253 sc->aw_host.ios.power_mode = value; 1254 break; 1255 case MMCBR_IVAR_VDD: 1256 sc->aw_host.ios.vdd = value; 1257 break; 1258 case MMCBR_IVAR_VCCQ: 1259 sc->aw_host.ios.vccq = value; 1260 break; 1261 case MMCBR_IVAR_TIMING: 1262 sc->aw_host.ios.timing = value; 1263 break; 1264 /* These are read-only */ 1265 case MMCBR_IVAR_CAPS: 1266 case MMCBR_IVAR_HOST_OCR: 1267 case MMCBR_IVAR_F_MIN: 1268 case MMCBR_IVAR_F_MAX: 1269 case MMCBR_IVAR_MAX_DATA: 1270 return (EINVAL); 1271 } 1272 1273 return (0); 1274 } 1275 1276 static int 1277 aw_mmc_update_clock(struct aw_mmc_softc *sc, uint32_t clkon) 1278 { 1279 uint32_t reg; 1280 int retry; 1281 1282 reg = AW_MMC_READ_4(sc, AW_MMC_CKCR); 1283 reg &= ~(AW_MMC_CKCR_ENB | AW_MMC_CKCR_LOW_POWER | 1284 AW_MMC_CKCR_MASK_DATA0); 1285 1286 if (clkon) 1287 reg |= AW_MMC_CKCR_ENB; 1288 if (sc->aw_mmc_conf->mask_data0) 1289 reg |= AW_MMC_CKCR_MASK_DATA0; 1290 1291 AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg); 1292 1293 reg = AW_MMC_CMDR_LOAD | AW_MMC_CMDR_PRG_CLK | 1294 AW_MMC_CMDR_WAIT_PRE_OVER; 1295 AW_MMC_WRITE_4(sc, AW_MMC_CMDR, reg); 1296 retry = 0xfffff; 1297 1298 while (reg & AW_MMC_CMDR_LOAD && --retry > 0) { 1299 reg = AW_MMC_READ_4(sc, AW_MMC_CMDR); 1300 DELAY(10); 1301 } 1302 AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff); 1303 1304 if (reg & AW_MMC_CMDR_LOAD) { 1305 device_printf(sc->aw_dev, "timeout updating clock\n"); 1306 return (ETIMEDOUT); 1307 } 1308 1309 if (sc->aw_mmc_conf->mask_data0) { 1310 reg = AW_MMC_READ_4(sc, AW_MMC_CKCR); 1311 reg &= ~AW_MMC_CKCR_MASK_DATA0; 1312 AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg); 1313 } 1314 1315 return (0); 1316 } 1317 1318 static int 1319 aw_mmc_switch_vccq(device_t bus, device_t child) 1320 { 1321 struct aw_mmc_softc *sc; 1322 int uvolt, err; 1323 1324 sc = device_get_softc(bus); 1325 1326 if (sc->aw_reg_vqmmc == NULL) 1327 return EOPNOTSUPP; 1328 1329 switch (sc->aw_host.ios.vccq) { 1330 case vccq_180: 1331 uvolt = 1800000; 1332 break; 1333 case vccq_330: 1334 uvolt = 3300000; 1335 break; 1336 default: 1337 return EINVAL; 1338 } 1339 1340 err = regulator_set_voltage(sc->aw_reg_vqmmc, uvolt, uvolt); 1341 if (err != 0) { 1342 device_printf(sc->aw_dev, 1343 "Cannot set vqmmc to %d<->%d\n", 1344 uvolt, 1345 uvolt); 1346 return (err); 1347 } 1348 1349 return (0); 1350 } 1351 1352 static int 1353 aw_mmc_update_ios(device_t bus, device_t child) 1354 { 1355 int error; 1356 struct aw_mmc_softc *sc; 1357 struct mmc_ios *ios; 1358 unsigned int clock; 1359 uint32_t reg, div = 1; 1360 1361 sc = device_get_softc(bus); 1362 1363 ios = &sc->aw_host.ios; 1364 1365 /* Set the bus width. */ 1366 switch (ios->bus_width) { 1367 case bus_width_1: 1368 AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR1); 1369 break; 1370 case bus_width_4: 1371 AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR4); 1372 break; 1373 case bus_width_8: 1374 AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR8); 1375 break; 1376 } 1377 1378 switch (ios->power_mode) { 1379 case power_on: 1380 break; 1381 case power_off: 1382 if (bootverbose) 1383 device_printf(sc->aw_dev, "Powering down sd/mmc\n"); 1384 1385 if (sc->aw_reg_vmmc) 1386 regulator_disable(sc->aw_reg_vmmc); 1387 if (sc->aw_reg_vqmmc) 1388 regulator_disable(sc->aw_reg_vqmmc); 1389 1390 aw_mmc_reset(sc); 1391 break; 1392 case power_up: 1393 if (bootverbose) 1394 device_printf(sc->aw_dev, "Powering up sd/mmc\n"); 1395 1396 if (sc->aw_reg_vmmc) 1397 regulator_enable(sc->aw_reg_vmmc); 1398 if (sc->aw_reg_vqmmc) 1399 regulator_enable(sc->aw_reg_vqmmc); 1400 aw_mmc_init(sc); 1401 break; 1402 }; 1403 1404 /* Enable ddr mode if needed */ 1405 reg = AW_MMC_READ_4(sc, AW_MMC_GCTL); 1406 if (ios->timing == bus_timing_uhs_ddr50 || 1407 ios->timing == bus_timing_mmc_ddr52) 1408 reg |= AW_MMC_GCTL_DDR_MOD_SEL; 1409 else 1410 reg &= ~AW_MMC_GCTL_DDR_MOD_SEL; 1411 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg); 1412 1413 if (ios->clock && ios->clock != sc->aw_clock) { 1414 sc->aw_clock = clock = ios->clock; 1415 1416 /* Disable clock */ 1417 error = aw_mmc_update_clock(sc, 0); 1418 if (error != 0) 1419 return (error); 1420 1421 if (ios->timing == bus_timing_mmc_ddr52 && 1422 (sc->aw_mmc_conf->new_timing || 1423 ios->bus_width == bus_width_8)) { 1424 div = 2; 1425 clock <<= 1; 1426 } 1427 1428 /* Reset the divider. */ 1429 reg = AW_MMC_READ_4(sc, AW_MMC_CKCR); 1430 reg &= ~AW_MMC_CKCR_DIV; 1431 reg |= div - 1; 1432 AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg); 1433 1434 /* New timing mode if needed */ 1435 if (sc->aw_mmc_conf->new_timing) { 1436 reg = AW_MMC_READ_4(sc, AW_MMC_NTSR); 1437 reg |= AW_MMC_NTSR_MODE_SELECT; 1438 AW_MMC_WRITE_4(sc, AW_MMC_NTSR, reg); 1439 } 1440 1441 /* Set the MMC clock. */ 1442 error = clk_disable(sc->aw_clk_mmc); 1443 if (error != 0 && bootverbose) 1444 device_printf(sc->aw_dev, 1445 "failed to disable mmc clock: %d\n", error); 1446 error = clk_set_freq(sc->aw_clk_mmc, clock, 1447 CLK_SET_ROUND_DOWN); 1448 if (error != 0) { 1449 device_printf(sc->aw_dev, 1450 "failed to set frequency to %u Hz: %d\n", 1451 clock, error); 1452 return (error); 1453 } 1454 error = clk_enable(sc->aw_clk_mmc); 1455 if (error != 0 && bootverbose) 1456 device_printf(sc->aw_dev, 1457 "failed to re-enable mmc clock: %d\n", error); 1458 1459 if (sc->aw_mmc_conf->can_calibrate) 1460 AW_MMC_WRITE_4(sc, AW_MMC_SAMP_DL, AW_MMC_SAMP_DL_SW_EN); 1461 1462 /* Enable clock. */ 1463 error = aw_mmc_update_clock(sc, 1); 1464 if (error != 0) 1465 return (error); 1466 } 1467 1468 1469 return (0); 1470 } 1471 1472 static int 1473 aw_mmc_get_ro(device_t bus, device_t child) 1474 { 1475 1476 return (0); 1477 } 1478 1479 static int 1480 aw_mmc_acquire_host(device_t bus, device_t child) 1481 { 1482 struct aw_mmc_softc *sc; 1483 int error; 1484 1485 sc = device_get_softc(bus); 1486 AW_MMC_LOCK(sc); 1487 while (sc->aw_bus_busy) { 1488 error = msleep(sc, &sc->aw_mtx, PCATCH, "mmchw", 0); 1489 if (error != 0) { 1490 AW_MMC_UNLOCK(sc); 1491 return (error); 1492 } 1493 } 1494 sc->aw_bus_busy++; 1495 AW_MMC_UNLOCK(sc); 1496 1497 return (0); 1498 } 1499 1500 static int 1501 aw_mmc_release_host(device_t bus, device_t child) 1502 { 1503 struct aw_mmc_softc *sc; 1504 1505 sc = device_get_softc(bus); 1506 AW_MMC_LOCK(sc); 1507 sc->aw_bus_busy--; 1508 wakeup(sc); 1509 AW_MMC_UNLOCK(sc); 1510 1511 return (0); 1512 } 1513 1514 static device_method_t aw_mmc_methods[] = { 1515 /* Device interface */ 1516 DEVMETHOD(device_probe, aw_mmc_probe), 1517 DEVMETHOD(device_attach, aw_mmc_attach), 1518 DEVMETHOD(device_detach, aw_mmc_detach), 1519 1520 /* Bus interface */ 1521 DEVMETHOD(bus_read_ivar, aw_mmc_read_ivar), 1522 DEVMETHOD(bus_write_ivar, aw_mmc_write_ivar), 1523 DEVMETHOD(bus_add_child, bus_generic_add_child), 1524 1525 /* MMC bridge interface */ 1526 DEVMETHOD(mmcbr_update_ios, aw_mmc_update_ios), 1527 DEVMETHOD(mmcbr_request, aw_mmc_request), 1528 DEVMETHOD(mmcbr_get_ro, aw_mmc_get_ro), 1529 DEVMETHOD(mmcbr_switch_vccq, aw_mmc_switch_vccq), 1530 DEVMETHOD(mmcbr_acquire_host, aw_mmc_acquire_host), 1531 DEVMETHOD(mmcbr_release_host, aw_mmc_release_host), 1532 1533 DEVMETHOD_END 1534 }; 1535 1536 static devclass_t aw_mmc_devclass; 1537 1538 static driver_t aw_mmc_driver = { 1539 "aw_mmc", 1540 aw_mmc_methods, 1541 sizeof(struct aw_mmc_softc), 1542 }; 1543 1544 DRIVER_MODULE(aw_mmc, simplebus, aw_mmc_driver, aw_mmc_devclass, NULL, 1545 NULL); 1546 #ifndef MMCCAM 1547 MMC_DECLARE_BRIDGE(aw_mmc); 1548 #endif 1549