1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org> 5 * Copyright (c) 2013 Alexander Fedorov 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/kernel.h> 37 #include <sys/lock.h> 38 #include <sys/malloc.h> 39 #include <sys/module.h> 40 #include <sys/mutex.h> 41 #include <sys/resource.h> 42 #include <sys/rman.h> 43 #include <sys/sysctl.h> 44 #include <sys/queue.h> 45 #include <sys/taskqueue.h> 46 47 #include <machine/bus.h> 48 49 #include <dev/ofw/ofw_bus.h> 50 #include <dev/ofw/ofw_bus_subr.h> 51 52 #include <dev/mmc/bridge.h> 53 #include <dev/mmc/mmcbrvar.h> 54 #include <dev/mmc/mmc_fdt_helpers.h> 55 56 #include <arm/allwinner/aw_mmc.h> 57 #include <dev/extres/clk/clk.h> 58 #include <dev/extres/hwreset/hwreset.h> 59 #include <dev/extres/regulator/regulator.h> 60 61 #include "opt_mmccam.h" 62 63 #ifdef MMCCAM 64 #include <cam/cam.h> 65 #include <cam/cam_ccb.h> 66 #include <cam/cam_debug.h> 67 #include <cam/cam_sim.h> 68 #include <cam/cam_xpt_sim.h> 69 #endif 70 71 #define AW_MMC_MEMRES 0 72 #define AW_MMC_IRQRES 1 73 #define AW_MMC_RESSZ 2 74 #define AW_MMC_DMA_SEGS (PAGE_SIZE / sizeof(struct aw_mmc_dma_desc)) 75 #define AW_MMC_DMA_DESC_SIZE (sizeof(struct aw_mmc_dma_desc) * AW_MMC_DMA_SEGS) 76 #define AW_MMC_DMA_FTRGLEVEL 0x20070008 77 78 #define AW_MMC_RESET_RETRY 1000 79 80 #define CARD_ID_FREQUENCY 400000 81 82 struct aw_mmc_conf { 83 uint32_t dma_xferlen; 84 bool mask_data0; 85 bool can_calibrate; 86 bool new_timing; 87 }; 88 89 static const struct aw_mmc_conf a10_mmc_conf = { 90 .dma_xferlen = 0x2000, 91 }; 92 93 static const struct aw_mmc_conf a13_mmc_conf = { 94 .dma_xferlen = 0x10000, 95 }; 96 97 static const struct aw_mmc_conf a64_mmc_conf = { 98 .dma_xferlen = 0x10000, 99 .mask_data0 = true, 100 .can_calibrate = true, 101 .new_timing = true, 102 }; 103 104 static const struct aw_mmc_conf a64_emmc_conf = { 105 .dma_xferlen = 0x2000, 106 .can_calibrate = true, 107 }; 108 109 static struct ofw_compat_data compat_data[] = { 110 {"allwinner,sun4i-a10-mmc", (uintptr_t)&a10_mmc_conf}, 111 {"allwinner,sun5i-a13-mmc", (uintptr_t)&a13_mmc_conf}, 112 {"allwinner,sun7i-a20-mmc", (uintptr_t)&a13_mmc_conf}, 113 {"allwinner,sun50i-a64-mmc", (uintptr_t)&a64_mmc_conf}, 114 {"allwinner,sun50i-a64-emmc", (uintptr_t)&a64_emmc_conf}, 115 {NULL, 0} 116 }; 117 118 struct aw_mmc_softc { 119 device_t aw_dev; 120 clk_t aw_clk_ahb; 121 clk_t aw_clk_mmc; 122 hwreset_t aw_rst_ahb; 123 int aw_bus_busy; 124 int aw_resid; 125 int aw_timeout; 126 struct callout aw_timeoutc; 127 struct mmc_host aw_host; 128 struct mmc_fdt_helper mmc_helper; 129 #ifdef MMCCAM 130 union ccb * ccb; 131 struct cam_devq * devq; 132 struct cam_sim * sim; 133 struct mtx sim_mtx; 134 #else 135 struct mmc_request * aw_req; 136 #endif 137 struct mtx aw_mtx; 138 struct resource * aw_res[AW_MMC_RESSZ]; 139 struct aw_mmc_conf * aw_mmc_conf; 140 uint32_t aw_intr; 141 uint32_t aw_intr_wait; 142 void * aw_intrhand; 143 unsigned int aw_clock; 144 device_t child; 145 146 /* Fields required for DMA access. */ 147 bus_addr_t aw_dma_desc_phys; 148 bus_dmamap_t aw_dma_map; 149 bus_dma_tag_t aw_dma_tag; 150 void * aw_dma_desc; 151 bus_dmamap_t aw_dma_buf_map; 152 bus_dma_tag_t aw_dma_buf_tag; 153 int aw_dma_map_err; 154 }; 155 156 static struct resource_spec aw_mmc_res_spec[] = { 157 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 158 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 159 { -1, 0, 0 } 160 }; 161 162 static int aw_mmc_probe(device_t); 163 static int aw_mmc_attach(device_t); 164 static int aw_mmc_detach(device_t); 165 static int aw_mmc_setup_dma(struct aw_mmc_softc *); 166 static void aw_mmc_teardown_dma(struct aw_mmc_softc *sc); 167 static int aw_mmc_reset(struct aw_mmc_softc *); 168 static int aw_mmc_init(struct aw_mmc_softc *); 169 static void aw_mmc_intr(void *); 170 static int aw_mmc_update_clock(struct aw_mmc_softc *, uint32_t); 171 static void aw_mmc_helper_cd_handler(device_t, bool); 172 173 static void aw_mmc_print_error(uint32_t); 174 static int aw_mmc_update_ios(device_t, device_t); 175 static int aw_mmc_request(device_t, device_t, struct mmc_request *); 176 static int aw_mmc_get_ro(device_t, device_t); 177 static int aw_mmc_acquire_host(device_t, device_t); 178 static int aw_mmc_release_host(device_t, device_t); 179 #ifdef MMCCAM 180 static void aw_mmc_cam_action(struct cam_sim *, union ccb *); 181 static void aw_mmc_cam_poll(struct cam_sim *); 182 static int aw_mmc_cam_settran_settings(struct aw_mmc_softc *, union ccb *); 183 static int aw_mmc_cam_request(struct aw_mmc_softc *, union ccb *); 184 static void aw_mmc_cam_handle_mmcio(struct cam_sim *, union ccb *); 185 #endif 186 187 #define AW_MMC_LOCK(_sc) mtx_lock(&(_sc)->aw_mtx) 188 #define AW_MMC_UNLOCK(_sc) mtx_unlock(&(_sc)->aw_mtx) 189 #define AW_MMC_READ_4(_sc, _reg) \ 190 bus_read_4((_sc)->aw_res[AW_MMC_MEMRES], _reg) 191 #define AW_MMC_WRITE_4(_sc, _reg, _value) \ 192 bus_write_4((_sc)->aw_res[AW_MMC_MEMRES], _reg, _value) 193 194 #ifdef MMCCAM 195 static void 196 aw_mmc_cam_handle_mmcio(struct cam_sim *sim, union ccb *ccb) 197 { 198 struct aw_mmc_softc *sc; 199 200 sc = cam_sim_softc(sim); 201 202 aw_mmc_cam_request(sc, ccb); 203 } 204 205 static void 206 aw_mmc_cam_action(struct cam_sim *sim, union ccb *ccb) 207 { 208 struct aw_mmc_softc *sc; 209 210 sc = cam_sim_softc(sim); 211 if (sc == NULL) { 212 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 213 xpt_done(ccb); 214 return; 215 } 216 217 mtx_assert(&sc->sim_mtx, MA_OWNED); 218 219 switch (ccb->ccb_h.func_code) { 220 case XPT_PATH_INQ: 221 mmc_path_inq(&ccb->cpi, "Deglitch Networks", sim, 222 (sc->aw_mmc_conf->dma_xferlen * AW_MMC_DMA_SEGS) / 223 MMC_SECTOR_SIZE); 224 break; 225 226 case XPT_GET_TRAN_SETTINGS: 227 { 228 struct ccb_trans_settings *cts = &ccb->cts; 229 230 if (bootverbose) 231 device_printf(sc->aw_dev, "Got XPT_GET_TRAN_SETTINGS\n"); 232 233 cts->protocol = PROTO_MMCSD; 234 cts->protocol_version = 1; 235 cts->transport = XPORT_MMCSD; 236 cts->transport_version = 1; 237 cts->xport_specific.valid = 0; 238 cts->proto_specific.mmc.host_ocr = sc->aw_host.host_ocr; 239 cts->proto_specific.mmc.host_f_min = sc->aw_host.f_min; 240 cts->proto_specific.mmc.host_f_max = sc->aw_host.f_max; 241 cts->proto_specific.mmc.host_caps = sc->aw_host.caps; 242 cts->proto_specific.mmc.host_max_data = (sc->aw_mmc_conf->dma_xferlen * 243 AW_MMC_DMA_SEGS) / MMC_SECTOR_SIZE; 244 memcpy(&cts->proto_specific.mmc.ios, &sc->aw_host.ios, sizeof(struct mmc_ios)); 245 ccb->ccb_h.status = CAM_REQ_CMP; 246 break; 247 } 248 case XPT_SET_TRAN_SETTINGS: 249 { 250 if (bootverbose) 251 device_printf(sc->aw_dev, "Got XPT_SET_TRAN_SETTINGS\n"); 252 aw_mmc_cam_settran_settings(sc, ccb); 253 ccb->ccb_h.status = CAM_REQ_CMP; 254 break; 255 } 256 case XPT_RESET_BUS: 257 if (bootverbose) 258 device_printf(sc->aw_dev, "Got XPT_RESET_BUS, ACK it...\n"); 259 ccb->ccb_h.status = CAM_REQ_CMP; 260 break; 261 case XPT_MMC_IO: 262 /* 263 * Here is the HW-dependent part of 264 * sending the command to the underlying h/w 265 * At some point in the future an interrupt comes. 266 * Then the request will be marked as completed. 267 */ 268 ccb->ccb_h.status = CAM_REQ_INPROG; 269 270 aw_mmc_cam_handle_mmcio(sim, ccb); 271 return; 272 /* NOTREACHED */ 273 break; 274 default: 275 ccb->ccb_h.status = CAM_REQ_INVALID; 276 break; 277 } 278 xpt_done(ccb); 279 return; 280 } 281 282 static void 283 aw_mmc_cam_poll(struct cam_sim *sim) 284 { 285 return; 286 } 287 288 static int 289 aw_mmc_cam_settran_settings(struct aw_mmc_softc *sc, union ccb *ccb) 290 { 291 struct mmc_ios *ios; 292 struct mmc_ios *new_ios; 293 struct ccb_trans_settings_mmc *cts; 294 295 ios = &sc->aw_host.ios; 296 297 cts = &ccb->cts.proto_specific.mmc; 298 new_ios = &cts->ios; 299 300 /* Update only requested fields */ 301 if (cts->ios_valid & MMC_CLK) { 302 ios->clock = new_ios->clock; 303 if (bootverbose) 304 device_printf(sc->aw_dev, "Clock => %d\n", ios->clock); 305 } 306 if (cts->ios_valid & MMC_VDD) { 307 ios->vdd = new_ios->vdd; 308 if (bootverbose) 309 device_printf(sc->aw_dev, "VDD => %d\n", ios->vdd); 310 } 311 if (cts->ios_valid & MMC_CS) { 312 ios->chip_select = new_ios->chip_select; 313 if (bootverbose) 314 device_printf(sc->aw_dev, "CS => %d\n", ios->chip_select); 315 } 316 if (cts->ios_valid & MMC_BW) { 317 ios->bus_width = new_ios->bus_width; 318 if (bootverbose) 319 device_printf(sc->aw_dev, "Bus width => %d\n", ios->bus_width); 320 } 321 if (cts->ios_valid & MMC_PM) { 322 ios->power_mode = new_ios->power_mode; 323 if (bootverbose) 324 device_printf(sc->aw_dev, "Power mode => %d\n", ios->power_mode); 325 } 326 if (cts->ios_valid & MMC_BT) { 327 ios->timing = new_ios->timing; 328 if (bootverbose) 329 device_printf(sc->aw_dev, "Timing => %d\n", ios->timing); 330 } 331 if (cts->ios_valid & MMC_BM) { 332 ios->bus_mode = new_ios->bus_mode; 333 if (bootverbose) 334 device_printf(sc->aw_dev, "Bus mode => %d\n", ios->bus_mode); 335 } 336 337 return (aw_mmc_update_ios(sc->aw_dev, NULL)); 338 } 339 340 static int 341 aw_mmc_cam_request(struct aw_mmc_softc *sc, union ccb *ccb) 342 { 343 struct ccb_mmcio *mmcio; 344 345 mmcio = &ccb->mmcio; 346 347 AW_MMC_LOCK(sc); 348 349 #ifdef DEBUG 350 if (__predict_false(bootverbose)) { 351 device_printf(sc->aw_dev, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 352 mmcio->cmd.opcode, mmcio->cmd.arg, mmcio->cmd.flags, 353 mmcio->cmd.data != NULL ? (unsigned int) mmcio->cmd.data->len : 0, 354 mmcio->cmd.data != NULL ? mmcio->cmd.data->flags: 0); 355 } 356 #endif 357 if (mmcio->cmd.data != NULL) { 358 if (mmcio->cmd.data->len == 0 || mmcio->cmd.data->flags == 0) 359 panic("data->len = %d, data->flags = %d -- something is b0rked", 360 (int)mmcio->cmd.data->len, mmcio->cmd.data->flags); 361 } 362 if (sc->ccb != NULL) { 363 device_printf(sc->aw_dev, "Controller still has an active command\n"); 364 return (EBUSY); 365 } 366 sc->ccb = ccb; 367 /* aw_mmc_request locks again */ 368 AW_MMC_UNLOCK(sc); 369 aw_mmc_request(sc->aw_dev, NULL, NULL); 370 371 return (0); 372 } 373 #endif /* MMCCAM */ 374 375 static void 376 aw_mmc_helper_cd_handler(device_t dev, bool present) 377 { 378 struct aw_mmc_softc *sc; 379 380 sc = device_get_softc(dev); 381 #ifdef MMCCAM 382 mmccam_start_discovery(sc->sim); 383 #else 384 AW_MMC_LOCK(sc); 385 if (present) { 386 if (sc->child == NULL) { 387 if (bootverbose) 388 device_printf(sc->aw_dev, "Card inserted\n"); 389 390 sc->child = device_add_child(sc->aw_dev, "mmc", -1); 391 AW_MMC_UNLOCK(sc); 392 if (sc->child) { 393 device_set_ivars(sc->child, sc); 394 (void)device_probe_and_attach(sc->child); 395 } 396 } else 397 AW_MMC_UNLOCK(sc); 398 } else { 399 /* Card isn't present, detach if necessary */ 400 if (sc->child != NULL) { 401 if (bootverbose) 402 device_printf(sc->aw_dev, "Card removed\n"); 403 404 AW_MMC_UNLOCK(sc); 405 device_delete_child(sc->aw_dev, sc->child); 406 sc->child = NULL; 407 } else 408 AW_MMC_UNLOCK(sc); 409 } 410 #endif /* MMCCAM */ 411 } 412 413 static int 414 aw_mmc_probe(device_t dev) 415 { 416 417 if (!ofw_bus_status_okay(dev)) 418 return (ENXIO); 419 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 420 return (ENXIO); 421 422 device_set_desc(dev, "Allwinner Integrated MMC/SD controller"); 423 424 return (BUS_PROBE_DEFAULT); 425 } 426 427 static int 428 aw_mmc_attach(device_t dev) 429 { 430 struct aw_mmc_softc *sc; 431 struct sysctl_ctx_list *ctx; 432 struct sysctl_oid_list *tree; 433 int error; 434 435 sc = device_get_softc(dev); 436 sc->aw_dev = dev; 437 438 sc->aw_mmc_conf = (struct aw_mmc_conf *)ofw_bus_search_compatible(dev, compat_data)->ocd_data; 439 440 #ifndef MMCCAM 441 sc->aw_req = NULL; 442 #endif 443 if (bus_alloc_resources(dev, aw_mmc_res_spec, sc->aw_res) != 0) { 444 device_printf(dev, "cannot allocate device resources\n"); 445 return (ENXIO); 446 } 447 if (bus_setup_intr(dev, sc->aw_res[AW_MMC_IRQRES], 448 INTR_TYPE_NET | INTR_MPSAFE, NULL, aw_mmc_intr, sc, 449 &sc->aw_intrhand)) { 450 bus_release_resources(dev, aw_mmc_res_spec, sc->aw_res); 451 device_printf(dev, "cannot setup interrupt handler\n"); 452 return (ENXIO); 453 } 454 mtx_init(&sc->aw_mtx, device_get_nameunit(sc->aw_dev), "aw_mmc", 455 MTX_DEF); 456 callout_init_mtx(&sc->aw_timeoutc, &sc->aw_mtx, 0); 457 458 /* De-assert reset */ 459 if (hwreset_get_by_ofw_name(dev, 0, "ahb", &sc->aw_rst_ahb) == 0) { 460 error = hwreset_deassert(sc->aw_rst_ahb); 461 if (error != 0) { 462 device_printf(dev, "cannot de-assert reset\n"); 463 goto fail; 464 } 465 } 466 467 /* Activate the module clock. */ 468 error = clk_get_by_ofw_name(dev, 0, "ahb", &sc->aw_clk_ahb); 469 if (error != 0) { 470 device_printf(dev, "cannot get ahb clock\n"); 471 goto fail; 472 } 473 error = clk_enable(sc->aw_clk_ahb); 474 if (error != 0) { 475 device_printf(dev, "cannot enable ahb clock\n"); 476 goto fail; 477 } 478 error = clk_get_by_ofw_name(dev, 0, "mmc", &sc->aw_clk_mmc); 479 if (error != 0) { 480 device_printf(dev, "cannot get mmc clock\n"); 481 goto fail; 482 } 483 error = clk_set_freq(sc->aw_clk_mmc, CARD_ID_FREQUENCY, 484 CLK_SET_ROUND_DOWN); 485 if (error != 0) { 486 device_printf(dev, "cannot init mmc clock\n"); 487 goto fail; 488 } 489 error = clk_enable(sc->aw_clk_mmc); 490 if (error != 0) { 491 device_printf(dev, "cannot enable mmc clock\n"); 492 goto fail; 493 } 494 495 sc->aw_timeout = 10; 496 ctx = device_get_sysctl_ctx(dev); 497 tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 498 SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "req_timeout", CTLFLAG_RW, 499 &sc->aw_timeout, 0, "Request timeout in seconds"); 500 501 /* Soft Reset controller. */ 502 if (aw_mmc_reset(sc) != 0) { 503 device_printf(dev, "cannot reset the controller\n"); 504 goto fail; 505 } 506 507 if (aw_mmc_setup_dma(sc) != 0) { 508 device_printf(sc->aw_dev, "Couldn't setup DMA!\n"); 509 goto fail; 510 } 511 512 /* Set some defaults for freq and supported mode */ 513 sc->aw_host.f_min = 400000; 514 sc->aw_host.f_max = 52000000; 515 sc->aw_host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340; 516 sc->aw_host.caps |= MMC_CAP_HSPEED | MMC_CAP_SIGNALING_330; 517 mmc_fdt_parse(dev, 0, &sc->mmc_helper, &sc->aw_host); 518 mmc_fdt_gpio_setup(dev, 0, &sc->mmc_helper, aw_mmc_helper_cd_handler); 519 520 #ifdef MMCCAM 521 sc->ccb = NULL; 522 if ((sc->devq = cam_simq_alloc(1)) == NULL) { 523 goto fail; 524 } 525 526 mtx_init(&sc->sim_mtx, "awmmcsim", NULL, MTX_DEF); 527 sc->sim = cam_sim_alloc_dev(aw_mmc_cam_action, aw_mmc_cam_poll, 528 "aw_mmc_sim", sc, dev, 529 &sc->sim_mtx, 1, 1, sc->devq); 530 531 if (sc->sim == NULL) { 532 cam_simq_free(sc->devq); 533 device_printf(dev, "cannot allocate CAM SIM\n"); 534 goto fail; 535 } 536 537 mtx_lock(&sc->sim_mtx); 538 if (xpt_bus_register(sc->sim, sc->aw_dev, 0) != 0) { 539 device_printf(dev, "cannot register SCSI pass-through bus\n"); 540 cam_sim_free(sc->sim, FALSE); 541 cam_simq_free(sc->devq); 542 mtx_unlock(&sc->sim_mtx); 543 goto fail; 544 } 545 546 mtx_unlock(&sc->sim_mtx); 547 #endif /* MMCCAM */ 548 549 return (0); 550 551 fail: 552 callout_drain(&sc->aw_timeoutc); 553 mtx_destroy(&sc->aw_mtx); 554 bus_teardown_intr(dev, sc->aw_res[AW_MMC_IRQRES], sc->aw_intrhand); 555 bus_release_resources(dev, aw_mmc_res_spec, sc->aw_res); 556 557 #ifdef MMCCAM 558 if (sc->sim != NULL) { 559 mtx_lock(&sc->sim_mtx); 560 xpt_bus_deregister(cam_sim_path(sc->sim)); 561 cam_sim_free(sc->sim, FALSE); 562 mtx_unlock(&sc->sim_mtx); 563 } 564 565 if (sc->devq != NULL) 566 cam_simq_free(sc->devq); 567 #endif 568 return (ENXIO); 569 } 570 571 static int 572 aw_mmc_detach(device_t dev) 573 { 574 struct aw_mmc_softc *sc; 575 device_t d; 576 577 sc = device_get_softc(dev); 578 579 clk_disable(sc->aw_clk_mmc); 580 clk_disable(sc->aw_clk_ahb); 581 hwreset_assert(sc->aw_rst_ahb); 582 583 mmc_fdt_gpio_teardown(&sc->mmc_helper); 584 585 callout_drain(&sc->aw_timeoutc); 586 587 AW_MMC_LOCK(sc); 588 d = sc->child; 589 sc->child = NULL; 590 AW_MMC_UNLOCK(sc); 591 if (d != NULL) 592 device_delete_child(sc->aw_dev, d); 593 594 aw_mmc_teardown_dma(sc); 595 596 mtx_destroy(&sc->aw_mtx); 597 598 bus_teardown_intr(dev, sc->aw_res[AW_MMC_IRQRES], sc->aw_intrhand); 599 bus_release_resources(dev, aw_mmc_res_spec, sc->aw_res); 600 601 #ifdef MMCCAM 602 if (sc->sim != NULL) { 603 mtx_lock(&sc->sim_mtx); 604 xpt_bus_deregister(cam_sim_path(sc->sim)); 605 cam_sim_free(sc->sim, FALSE); 606 mtx_unlock(&sc->sim_mtx); 607 } 608 609 if (sc->devq != NULL) 610 cam_simq_free(sc->devq); 611 #endif 612 613 return (0); 614 } 615 616 static void 617 aw_dma_desc_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err) 618 { 619 struct aw_mmc_softc *sc; 620 621 sc = (struct aw_mmc_softc *)arg; 622 if (err) { 623 sc->aw_dma_map_err = err; 624 return; 625 } 626 sc->aw_dma_desc_phys = segs[0].ds_addr; 627 } 628 629 static int 630 aw_mmc_setup_dma(struct aw_mmc_softc *sc) 631 { 632 int error; 633 634 /* Allocate the DMA descriptor memory. */ 635 error = bus_dma_tag_create( 636 bus_get_dma_tag(sc->aw_dev), /* parent */ 637 AW_MMC_DMA_ALIGN, 0, /* align, boundary */ 638 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 639 BUS_SPACE_MAXADDR, /* highaddr */ 640 NULL, NULL, /* filter, filterarg*/ 641 AW_MMC_DMA_DESC_SIZE, 1, /* maxsize, nsegment */ 642 AW_MMC_DMA_DESC_SIZE, /* maxsegsize */ 643 0, /* flags */ 644 NULL, NULL, /* lock, lockarg*/ 645 &sc->aw_dma_tag); 646 if (error) 647 return (error); 648 649 error = bus_dmamem_alloc(sc->aw_dma_tag, &sc->aw_dma_desc, 650 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, 651 &sc->aw_dma_map); 652 if (error) 653 return (error); 654 655 error = bus_dmamap_load(sc->aw_dma_tag, 656 sc->aw_dma_map, 657 sc->aw_dma_desc, AW_MMC_DMA_DESC_SIZE, 658 aw_dma_desc_cb, sc, 0); 659 if (error) 660 return (error); 661 if (sc->aw_dma_map_err) 662 return (sc->aw_dma_map_err); 663 664 /* Create the DMA map for data transfers. */ 665 error = bus_dma_tag_create( 666 bus_get_dma_tag(sc->aw_dev), /* parent */ 667 AW_MMC_DMA_ALIGN, 0, /* align, boundary */ 668 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 669 BUS_SPACE_MAXADDR, /* highaddr */ 670 NULL, NULL, /* filter, filterarg*/ 671 sc->aw_mmc_conf->dma_xferlen * 672 AW_MMC_DMA_SEGS, AW_MMC_DMA_SEGS, /* maxsize, nsegments */ 673 sc->aw_mmc_conf->dma_xferlen, /* maxsegsize */ 674 BUS_DMA_ALLOCNOW, /* flags */ 675 NULL, NULL, /* lock, lockarg*/ 676 &sc->aw_dma_buf_tag); 677 if (error) 678 return (error); 679 error = bus_dmamap_create(sc->aw_dma_buf_tag, 0, 680 &sc->aw_dma_buf_map); 681 if (error) 682 return (error); 683 684 return (0); 685 } 686 687 static void 688 aw_mmc_teardown_dma(struct aw_mmc_softc *sc) 689 { 690 691 bus_dmamap_unload(sc->aw_dma_tag, sc->aw_dma_map); 692 bus_dmamem_free(sc->aw_dma_tag, sc->aw_dma_desc, sc->aw_dma_map); 693 if (bus_dma_tag_destroy(sc->aw_dma_tag) != 0) 694 device_printf(sc->aw_dev, "Cannot destroy the dma tag\n"); 695 696 bus_dmamap_unload(sc->aw_dma_buf_tag, sc->aw_dma_buf_map); 697 bus_dmamap_destroy(sc->aw_dma_buf_tag, sc->aw_dma_buf_map); 698 if (bus_dma_tag_destroy(sc->aw_dma_buf_tag) != 0) 699 device_printf(sc->aw_dev, "Cannot destroy the dma buf tag\n"); 700 } 701 702 static void 703 aw_dma_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err) 704 { 705 int i; 706 struct aw_mmc_dma_desc *dma_desc; 707 struct aw_mmc_softc *sc; 708 709 sc = (struct aw_mmc_softc *)arg; 710 sc->aw_dma_map_err = err; 711 712 if (err) 713 return; 714 715 dma_desc = sc->aw_dma_desc; 716 for (i = 0; i < nsegs; i++) { 717 if (segs[i].ds_len == sc->aw_mmc_conf->dma_xferlen) 718 dma_desc[i].buf_size = 0; /* Size of 0 indicate max len */ 719 else 720 dma_desc[i].buf_size = segs[i].ds_len; 721 dma_desc[i].buf_addr = segs[i].ds_addr; 722 dma_desc[i].config = AW_MMC_DMA_CONFIG_CH | 723 AW_MMC_DMA_CONFIG_OWN | AW_MMC_DMA_CONFIG_DIC; 724 725 dma_desc[i].next = sc->aw_dma_desc_phys + 726 ((i + 1) * sizeof(struct aw_mmc_dma_desc)); 727 } 728 729 dma_desc[0].config |= AW_MMC_DMA_CONFIG_FD; 730 dma_desc[nsegs - 1].config |= AW_MMC_DMA_CONFIG_LD | 731 AW_MMC_DMA_CONFIG_ER; 732 dma_desc[nsegs - 1].config &= ~AW_MMC_DMA_CONFIG_DIC; 733 dma_desc[nsegs - 1].next = 0; 734 } 735 736 static int 737 aw_mmc_prepare_dma(struct aw_mmc_softc *sc) 738 { 739 bus_dmasync_op_t sync_op; 740 int error; 741 struct mmc_command *cmd; 742 uint32_t val; 743 744 #ifdef MMCCAM 745 cmd = &sc->ccb->mmcio.cmd; 746 #else 747 cmd = sc->aw_req->cmd; 748 #endif 749 if (cmd->data->len > (sc->aw_mmc_conf->dma_xferlen * AW_MMC_DMA_SEGS)) 750 return (EFBIG); 751 error = bus_dmamap_load(sc->aw_dma_buf_tag, sc->aw_dma_buf_map, 752 cmd->data->data, cmd->data->len, aw_dma_cb, sc, 0); 753 if (error) 754 return (error); 755 if (sc->aw_dma_map_err) 756 return (sc->aw_dma_map_err); 757 758 if (cmd->data->flags & MMC_DATA_WRITE) 759 sync_op = BUS_DMASYNC_PREWRITE; 760 else 761 sync_op = BUS_DMASYNC_PREREAD; 762 bus_dmamap_sync(sc->aw_dma_buf_tag, sc->aw_dma_buf_map, sync_op); 763 bus_dmamap_sync(sc->aw_dma_tag, sc->aw_dma_map, BUS_DMASYNC_PREWRITE); 764 765 /* Enable DMA */ 766 val = AW_MMC_READ_4(sc, AW_MMC_GCTL); 767 val &= ~AW_MMC_GCTL_FIFO_AC_MOD; 768 val |= AW_MMC_GCTL_DMA_ENB; 769 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val); 770 771 /* Reset DMA */ 772 val |= AW_MMC_GCTL_DMA_RST; 773 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val); 774 775 AW_MMC_WRITE_4(sc, AW_MMC_DMAC, AW_MMC_DMAC_IDMAC_SOFT_RST); 776 AW_MMC_WRITE_4(sc, AW_MMC_DMAC, 777 AW_MMC_DMAC_IDMAC_IDMA_ON | AW_MMC_DMAC_IDMAC_FIX_BURST); 778 779 /* Enable RX or TX DMA interrupt */ 780 val = AW_MMC_READ_4(sc, AW_MMC_IDIE); 781 if (cmd->data->flags & MMC_DATA_WRITE) 782 val |= AW_MMC_IDST_TX_INT; 783 else 784 val |= AW_MMC_IDST_RX_INT; 785 AW_MMC_WRITE_4(sc, AW_MMC_IDIE, val); 786 787 /* Set DMA descritptor list address */ 788 AW_MMC_WRITE_4(sc, AW_MMC_DLBA, sc->aw_dma_desc_phys); 789 790 /* FIFO trigger level */ 791 AW_MMC_WRITE_4(sc, AW_MMC_FWLR, AW_MMC_DMA_FTRGLEVEL); 792 793 return (0); 794 } 795 796 static int 797 aw_mmc_reset(struct aw_mmc_softc *sc) 798 { 799 uint32_t reg; 800 int timeout; 801 802 reg = AW_MMC_READ_4(sc, AW_MMC_GCTL); 803 reg |= AW_MMC_GCTL_RESET; 804 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg); 805 timeout = AW_MMC_RESET_RETRY; 806 while (--timeout > 0) { 807 if ((AW_MMC_READ_4(sc, AW_MMC_GCTL) & AW_MMC_GCTL_RESET) == 0) 808 break; 809 DELAY(100); 810 } 811 if (timeout == 0) 812 return (ETIMEDOUT); 813 814 return (0); 815 } 816 817 static int 818 aw_mmc_init(struct aw_mmc_softc *sc) 819 { 820 uint32_t reg; 821 int ret; 822 823 ret = aw_mmc_reset(sc); 824 if (ret != 0) 825 return (ret); 826 827 /* Set the timeout. */ 828 AW_MMC_WRITE_4(sc, AW_MMC_TMOR, 829 AW_MMC_TMOR_DTO_LMT_SHIFT(AW_MMC_TMOR_DTO_LMT_MASK) | 830 AW_MMC_TMOR_RTO_LMT_SHIFT(AW_MMC_TMOR_RTO_LMT_MASK)); 831 832 /* Unmask interrupts. */ 833 AW_MMC_WRITE_4(sc, AW_MMC_IMKR, 0); 834 835 /* Clear pending interrupts. */ 836 AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff); 837 838 /* Debug register, undocumented */ 839 AW_MMC_WRITE_4(sc, AW_MMC_DBGC, 0xdeb); 840 841 /* Function select register */ 842 AW_MMC_WRITE_4(sc, AW_MMC_FUNS, 0xceaa0000); 843 844 AW_MMC_WRITE_4(sc, AW_MMC_IDST, 0xffffffff); 845 846 /* Enable interrupts and disable AHB access. */ 847 reg = AW_MMC_READ_4(sc, AW_MMC_GCTL); 848 reg |= AW_MMC_GCTL_INT_ENB; 849 reg &= ~AW_MMC_GCTL_FIFO_AC_MOD; 850 reg &= ~AW_MMC_GCTL_WAIT_MEM_ACCESS; 851 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg); 852 853 return (0); 854 } 855 856 static void 857 aw_mmc_req_done(struct aw_mmc_softc *sc) 858 { 859 struct mmc_command *cmd; 860 #ifdef MMCCAM 861 union ccb *ccb; 862 #else 863 struct mmc_request *req; 864 #endif 865 uint32_t val, mask; 866 int retry; 867 868 #ifdef MMCCAM 869 ccb = sc->ccb; 870 cmd = &ccb->mmcio.cmd; 871 #else 872 cmd = sc->aw_req->cmd; 873 #endif 874 #ifdef DEBUG 875 if (bootverbose) { 876 device_printf(sc->aw_dev, "%s: cmd %d err %d\n", __func__, cmd->opcode, cmd->error); 877 } 878 #endif 879 if (cmd->error != MMC_ERR_NONE) { 880 /* Reset the FIFO and DMA engines. */ 881 mask = AW_MMC_GCTL_FIFO_RST | AW_MMC_GCTL_DMA_RST; 882 val = AW_MMC_READ_4(sc, AW_MMC_GCTL); 883 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val | mask); 884 885 retry = AW_MMC_RESET_RETRY; 886 while (--retry > 0) { 887 if ((AW_MMC_READ_4(sc, AW_MMC_GCTL) & 888 AW_MMC_GCTL_RESET) == 0) 889 break; 890 DELAY(100); 891 } 892 if (retry == 0) 893 device_printf(sc->aw_dev, 894 "timeout resetting DMA/FIFO\n"); 895 aw_mmc_update_clock(sc, 1); 896 } 897 898 callout_stop(&sc->aw_timeoutc); 899 sc->aw_intr = 0; 900 sc->aw_resid = 0; 901 sc->aw_dma_map_err = 0; 902 sc->aw_intr_wait = 0; 903 #ifdef MMCCAM 904 sc->ccb = NULL; 905 ccb->ccb_h.status = 906 (ccb->mmcio.cmd.error == 0 ? CAM_REQ_CMP : CAM_REQ_CMP_ERR); 907 xpt_done(ccb); 908 #else 909 req = sc->aw_req; 910 sc->aw_req = NULL; 911 req->done(req); 912 #endif 913 } 914 915 static void 916 aw_mmc_req_ok(struct aw_mmc_softc *sc) 917 { 918 int timeout; 919 struct mmc_command *cmd; 920 uint32_t status; 921 922 timeout = 1000; 923 while (--timeout > 0) { 924 status = AW_MMC_READ_4(sc, AW_MMC_STAR); 925 if ((status & AW_MMC_STAR_CARD_BUSY) == 0) 926 break; 927 DELAY(1000); 928 } 929 #ifdef MMCCAM 930 cmd = &sc->ccb->mmcio.cmd; 931 #else 932 cmd = sc->aw_req->cmd; 933 #endif 934 if (timeout == 0) { 935 cmd->error = MMC_ERR_FAILED; 936 aw_mmc_req_done(sc); 937 return; 938 } 939 if (cmd->flags & MMC_RSP_PRESENT) { 940 if (cmd->flags & MMC_RSP_136) { 941 cmd->resp[0] = AW_MMC_READ_4(sc, AW_MMC_RESP3); 942 cmd->resp[1] = AW_MMC_READ_4(sc, AW_MMC_RESP2); 943 cmd->resp[2] = AW_MMC_READ_4(sc, AW_MMC_RESP1); 944 cmd->resp[3] = AW_MMC_READ_4(sc, AW_MMC_RESP0); 945 } else 946 cmd->resp[0] = AW_MMC_READ_4(sc, AW_MMC_RESP0); 947 } 948 /* All data has been transferred ? */ 949 if (cmd->data != NULL && (sc->aw_resid << 2) < cmd->data->len) 950 cmd->error = MMC_ERR_FAILED; 951 aw_mmc_req_done(sc); 952 } 953 954 955 static inline void 956 set_mmc_error(struct aw_mmc_softc *sc, int error_code) 957 { 958 #ifdef MMCCAM 959 sc->ccb->mmcio.cmd.error = error_code; 960 #else 961 sc->aw_req->cmd->error = error_code; 962 #endif 963 } 964 965 static void 966 aw_mmc_timeout(void *arg) 967 { 968 struct aw_mmc_softc *sc; 969 970 sc = (struct aw_mmc_softc *)arg; 971 #ifdef MMCCAM 972 if (sc->ccb != NULL) { 973 #else 974 if (sc->aw_req != NULL) { 975 #endif 976 device_printf(sc->aw_dev, "controller timeout\n"); 977 set_mmc_error(sc, MMC_ERR_TIMEOUT); 978 aw_mmc_req_done(sc); 979 } else 980 device_printf(sc->aw_dev, 981 "Spurious timeout - no active request\n"); 982 } 983 984 static void 985 aw_mmc_print_error(uint32_t err) 986 { 987 if(err & AW_MMC_INT_RESP_ERR) 988 printf("AW_MMC_INT_RESP_ERR "); 989 if (err & AW_MMC_INT_RESP_CRC_ERR) 990 printf("AW_MMC_INT_RESP_CRC_ERR "); 991 if (err & AW_MMC_INT_DATA_CRC_ERR) 992 printf("AW_MMC_INT_DATA_CRC_ERR "); 993 if (err & AW_MMC_INT_RESP_TIMEOUT) 994 printf("AW_MMC_INT_RESP_TIMEOUT "); 995 if (err & AW_MMC_INT_FIFO_RUN_ERR) 996 printf("AW_MMC_INT_FIFO_RUN_ERR "); 997 if (err & AW_MMC_INT_CMD_BUSY) 998 printf("AW_MMC_INT_CMD_BUSY "); 999 if (err & AW_MMC_INT_DATA_START_ERR) 1000 printf("AW_MMC_INT_DATA_START_ERR "); 1001 if (err & AW_MMC_INT_DATA_END_BIT_ERR) 1002 printf("AW_MMC_INT_DATA_END_BIT_ERR"); 1003 printf("\n"); 1004 } 1005 1006 static void 1007 aw_mmc_intr(void *arg) 1008 { 1009 bus_dmasync_op_t sync_op; 1010 struct aw_mmc_softc *sc; 1011 struct mmc_data *data; 1012 uint32_t idst, imask, rint; 1013 1014 sc = (struct aw_mmc_softc *)arg; 1015 AW_MMC_LOCK(sc); 1016 rint = AW_MMC_READ_4(sc, AW_MMC_RISR); 1017 idst = AW_MMC_READ_4(sc, AW_MMC_IDST); 1018 imask = AW_MMC_READ_4(sc, AW_MMC_IMKR); 1019 if (idst == 0 && imask == 0 && rint == 0) { 1020 AW_MMC_UNLOCK(sc); 1021 return; 1022 } 1023 #ifdef DEBUG 1024 device_printf(sc->aw_dev, "idst: %#x, imask: %#x, rint: %#x\n", 1025 idst, imask, rint); 1026 #endif 1027 #ifdef MMCCAM 1028 if (sc->ccb == NULL) { 1029 #else 1030 if (sc->aw_req == NULL) { 1031 #endif 1032 device_printf(sc->aw_dev, 1033 "Spurious interrupt - no active request, rint: 0x%08X\n", 1034 rint); 1035 aw_mmc_print_error(rint); 1036 goto end; 1037 } 1038 if (rint & AW_MMC_INT_ERR_BIT) { 1039 if (bootverbose) 1040 device_printf(sc->aw_dev, "error rint: 0x%08X\n", rint); 1041 aw_mmc_print_error(rint); 1042 if (rint & AW_MMC_INT_RESP_TIMEOUT) 1043 set_mmc_error(sc, MMC_ERR_TIMEOUT); 1044 else 1045 set_mmc_error(sc, MMC_ERR_FAILED); 1046 aw_mmc_req_done(sc); 1047 goto end; 1048 } 1049 if (idst & AW_MMC_IDST_ERROR) { 1050 device_printf(sc->aw_dev, "error idst: 0x%08x\n", idst); 1051 set_mmc_error(sc, MMC_ERR_FAILED); 1052 aw_mmc_req_done(sc); 1053 goto end; 1054 } 1055 1056 sc->aw_intr |= rint; 1057 #ifdef MMCCAM 1058 data = sc->ccb->mmcio.cmd.data; 1059 #else 1060 data = sc->aw_req->cmd->data; 1061 #endif 1062 if (data != NULL && (idst & AW_MMC_IDST_COMPLETE) != 0) { 1063 if (data->flags & MMC_DATA_WRITE) 1064 sync_op = BUS_DMASYNC_POSTWRITE; 1065 else 1066 sync_op = BUS_DMASYNC_POSTREAD; 1067 bus_dmamap_sync(sc->aw_dma_buf_tag, sc->aw_dma_buf_map, 1068 sync_op); 1069 bus_dmamap_sync(sc->aw_dma_tag, sc->aw_dma_map, 1070 BUS_DMASYNC_POSTWRITE); 1071 bus_dmamap_unload(sc->aw_dma_buf_tag, sc->aw_dma_buf_map); 1072 sc->aw_resid = data->len >> 2; 1073 } 1074 if ((sc->aw_intr & sc->aw_intr_wait) == sc->aw_intr_wait) 1075 aw_mmc_req_ok(sc); 1076 1077 end: 1078 AW_MMC_WRITE_4(sc, AW_MMC_IDST, idst); 1079 AW_MMC_WRITE_4(sc, AW_MMC_RISR, rint); 1080 AW_MMC_UNLOCK(sc); 1081 } 1082 1083 static int 1084 aw_mmc_request(device_t bus, device_t child, struct mmc_request *req) 1085 { 1086 int blksz; 1087 struct aw_mmc_softc *sc; 1088 struct mmc_command *cmd; 1089 uint32_t cmdreg, imask; 1090 int err; 1091 1092 sc = device_get_softc(bus); 1093 1094 AW_MMC_LOCK(sc); 1095 #ifdef MMCCAM 1096 KASSERT(req == NULL, ("req should be NULL in MMCCAM case!")); 1097 /* 1098 * For MMCCAM, sc->ccb has been NULL-checked and populated 1099 * by aw_mmc_cam_request() already. 1100 */ 1101 cmd = &sc->ccb->mmcio.cmd; 1102 #else 1103 if (sc->aw_req) { 1104 AW_MMC_UNLOCK(sc); 1105 return (EBUSY); 1106 } 1107 sc->aw_req = req; 1108 cmd = req->cmd; 1109 1110 #ifdef DEBUG 1111 if (bootverbose) 1112 device_printf(sc->aw_dev, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 1113 cmd->opcode, cmd->arg, cmd->flags, 1114 cmd->data != NULL ? (unsigned int)cmd->data->len : 0, 1115 cmd->data != NULL ? cmd->data->flags: 0); 1116 #endif 1117 #endif 1118 cmdreg = AW_MMC_CMDR_LOAD; 1119 imask = AW_MMC_INT_ERR_BIT; 1120 sc->aw_intr_wait = 0; 1121 sc->aw_intr = 0; 1122 sc->aw_resid = 0; 1123 cmd->error = MMC_ERR_NONE; 1124 1125 if (cmd->opcode == MMC_GO_IDLE_STATE) 1126 cmdreg |= AW_MMC_CMDR_SEND_INIT_SEQ; 1127 1128 if (cmd->flags & MMC_RSP_PRESENT) 1129 cmdreg |= AW_MMC_CMDR_RESP_RCV; 1130 if (cmd->flags & MMC_RSP_136) 1131 cmdreg |= AW_MMC_CMDR_LONG_RESP; 1132 if (cmd->flags & MMC_RSP_CRC) 1133 cmdreg |= AW_MMC_CMDR_CHK_RESP_CRC; 1134 1135 if (cmd->data) { 1136 cmdreg |= AW_MMC_CMDR_DATA_TRANS | AW_MMC_CMDR_WAIT_PRE_OVER; 1137 1138 if (cmd->data->flags & MMC_DATA_MULTI) { 1139 cmdreg |= AW_MMC_CMDR_STOP_CMD_FLAG; 1140 imask |= AW_MMC_INT_AUTO_STOP_DONE; 1141 sc->aw_intr_wait |= AW_MMC_INT_AUTO_STOP_DONE; 1142 } else { 1143 sc->aw_intr_wait |= AW_MMC_INT_DATA_OVER; 1144 imask |= AW_MMC_INT_DATA_OVER; 1145 } 1146 if (cmd->data->flags & MMC_DATA_WRITE) 1147 cmdreg |= AW_MMC_CMDR_DIR_WRITE; 1148 #ifdef MMCCAM 1149 if (cmd->data->flags & MMC_DATA_BLOCK_SIZE) { 1150 AW_MMC_WRITE_4(sc, AW_MMC_BKSR, cmd->data->block_size); 1151 AW_MMC_WRITE_4(sc, AW_MMC_BYCR, cmd->data->len); 1152 } else 1153 #endif 1154 { 1155 blksz = min(cmd->data->len, MMC_SECTOR_SIZE); 1156 AW_MMC_WRITE_4(sc, AW_MMC_BKSR, blksz); 1157 AW_MMC_WRITE_4(sc, AW_MMC_BYCR, cmd->data->len); 1158 } 1159 } else { 1160 imask |= AW_MMC_INT_CMD_DONE; 1161 } 1162 1163 /* Enable the interrupts we are interested in */ 1164 AW_MMC_WRITE_4(sc, AW_MMC_IMKR, imask); 1165 AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff); 1166 1167 /* Enable auto stop if needed */ 1168 AW_MMC_WRITE_4(sc, AW_MMC_A12A, 1169 cmdreg & AW_MMC_CMDR_STOP_CMD_FLAG ? 0 : 0xffff); 1170 1171 /* Write the command argument */ 1172 AW_MMC_WRITE_4(sc, AW_MMC_CAGR, cmd->arg); 1173 1174 /* 1175 * If we don't have data start the request 1176 * if we do prepare the dma request and start the request 1177 */ 1178 if (cmd->data == NULL) { 1179 AW_MMC_WRITE_4(sc, AW_MMC_CMDR, cmdreg | cmd->opcode); 1180 } else { 1181 err = aw_mmc_prepare_dma(sc); 1182 if (err != 0) 1183 device_printf(sc->aw_dev, "prepare_dma failed: %d\n", err); 1184 1185 AW_MMC_WRITE_4(sc, AW_MMC_CMDR, cmdreg | cmd->opcode); 1186 } 1187 1188 callout_reset(&sc->aw_timeoutc, sc->aw_timeout * hz, 1189 aw_mmc_timeout, sc); 1190 AW_MMC_UNLOCK(sc); 1191 1192 return (0); 1193 } 1194 1195 static int 1196 aw_mmc_read_ivar(device_t bus, device_t child, int which, 1197 uintptr_t *result) 1198 { 1199 struct aw_mmc_softc *sc; 1200 1201 sc = device_get_softc(bus); 1202 switch (which) { 1203 default: 1204 return (EINVAL); 1205 case MMCBR_IVAR_BUS_MODE: 1206 *(int *)result = sc->aw_host.ios.bus_mode; 1207 break; 1208 case MMCBR_IVAR_BUS_WIDTH: 1209 *(int *)result = sc->aw_host.ios.bus_width; 1210 break; 1211 case MMCBR_IVAR_CHIP_SELECT: 1212 *(int *)result = sc->aw_host.ios.chip_select; 1213 break; 1214 case MMCBR_IVAR_CLOCK: 1215 *(int *)result = sc->aw_host.ios.clock; 1216 break; 1217 case MMCBR_IVAR_F_MIN: 1218 *(int *)result = sc->aw_host.f_min; 1219 break; 1220 case MMCBR_IVAR_F_MAX: 1221 *(int *)result = sc->aw_host.f_max; 1222 break; 1223 case MMCBR_IVAR_HOST_OCR: 1224 *(int *)result = sc->aw_host.host_ocr; 1225 break; 1226 case MMCBR_IVAR_MODE: 1227 *(int *)result = sc->aw_host.mode; 1228 break; 1229 case MMCBR_IVAR_OCR: 1230 *(int *)result = sc->aw_host.ocr; 1231 break; 1232 case MMCBR_IVAR_POWER_MODE: 1233 *(int *)result = sc->aw_host.ios.power_mode; 1234 break; 1235 case MMCBR_IVAR_VDD: 1236 *(int *)result = sc->aw_host.ios.vdd; 1237 break; 1238 case MMCBR_IVAR_VCCQ: 1239 *(int *)result = sc->aw_host.ios.vccq; 1240 break; 1241 case MMCBR_IVAR_CAPS: 1242 *(int *)result = sc->aw_host.caps; 1243 break; 1244 case MMCBR_IVAR_TIMING: 1245 *(int *)result = sc->aw_host.ios.timing; 1246 break; 1247 case MMCBR_IVAR_MAX_DATA: 1248 *(int *)result = (sc->aw_mmc_conf->dma_xferlen * 1249 AW_MMC_DMA_SEGS) / MMC_SECTOR_SIZE; 1250 break; 1251 case MMCBR_IVAR_RETUNE_REQ: 1252 *(int *)result = retune_req_none; 1253 break; 1254 } 1255 1256 return (0); 1257 } 1258 1259 static int 1260 aw_mmc_write_ivar(device_t bus, device_t child, int which, 1261 uintptr_t value) 1262 { 1263 struct aw_mmc_softc *sc; 1264 1265 sc = device_get_softc(bus); 1266 switch (which) { 1267 default: 1268 return (EINVAL); 1269 case MMCBR_IVAR_BUS_MODE: 1270 sc->aw_host.ios.bus_mode = value; 1271 break; 1272 case MMCBR_IVAR_BUS_WIDTH: 1273 sc->aw_host.ios.bus_width = value; 1274 break; 1275 case MMCBR_IVAR_CHIP_SELECT: 1276 sc->aw_host.ios.chip_select = value; 1277 break; 1278 case MMCBR_IVAR_CLOCK: 1279 sc->aw_host.ios.clock = value; 1280 break; 1281 case MMCBR_IVAR_MODE: 1282 sc->aw_host.mode = value; 1283 break; 1284 case MMCBR_IVAR_OCR: 1285 sc->aw_host.ocr = value; 1286 break; 1287 case MMCBR_IVAR_POWER_MODE: 1288 sc->aw_host.ios.power_mode = value; 1289 break; 1290 case MMCBR_IVAR_VDD: 1291 sc->aw_host.ios.vdd = value; 1292 break; 1293 case MMCBR_IVAR_VCCQ: 1294 sc->aw_host.ios.vccq = value; 1295 break; 1296 case MMCBR_IVAR_TIMING: 1297 sc->aw_host.ios.timing = value; 1298 break; 1299 /* These are read-only */ 1300 case MMCBR_IVAR_CAPS: 1301 case MMCBR_IVAR_HOST_OCR: 1302 case MMCBR_IVAR_F_MIN: 1303 case MMCBR_IVAR_F_MAX: 1304 case MMCBR_IVAR_MAX_DATA: 1305 return (EINVAL); 1306 } 1307 1308 return (0); 1309 } 1310 1311 static int 1312 aw_mmc_update_clock(struct aw_mmc_softc *sc, uint32_t clkon) 1313 { 1314 uint32_t reg; 1315 int retry; 1316 1317 reg = AW_MMC_READ_4(sc, AW_MMC_CKCR); 1318 reg &= ~(AW_MMC_CKCR_ENB | AW_MMC_CKCR_LOW_POWER | 1319 AW_MMC_CKCR_MASK_DATA0); 1320 1321 if (clkon) 1322 reg |= AW_MMC_CKCR_ENB; 1323 if (sc->aw_mmc_conf->mask_data0) 1324 reg |= AW_MMC_CKCR_MASK_DATA0; 1325 1326 AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg); 1327 1328 reg = AW_MMC_CMDR_LOAD | AW_MMC_CMDR_PRG_CLK | 1329 AW_MMC_CMDR_WAIT_PRE_OVER; 1330 AW_MMC_WRITE_4(sc, AW_MMC_CMDR, reg); 1331 retry = 0xfffff; 1332 1333 while (reg & AW_MMC_CMDR_LOAD && --retry > 0) { 1334 reg = AW_MMC_READ_4(sc, AW_MMC_CMDR); 1335 DELAY(10); 1336 } 1337 AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff); 1338 1339 if (reg & AW_MMC_CMDR_LOAD) { 1340 device_printf(sc->aw_dev, "timeout updating clock\n"); 1341 return (ETIMEDOUT); 1342 } 1343 1344 if (sc->aw_mmc_conf->mask_data0) { 1345 reg = AW_MMC_READ_4(sc, AW_MMC_CKCR); 1346 reg &= ~AW_MMC_CKCR_MASK_DATA0; 1347 AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg); 1348 } 1349 1350 return (0); 1351 } 1352 1353 static int 1354 aw_mmc_switch_vccq(device_t bus, device_t child) 1355 { 1356 struct aw_mmc_softc *sc; 1357 int uvolt, err; 1358 1359 sc = device_get_softc(bus); 1360 1361 if (sc->mmc_helper.vqmmc_supply == NULL) 1362 return EOPNOTSUPP; 1363 1364 switch (sc->aw_host.ios.vccq) { 1365 case vccq_180: 1366 uvolt = 1800000; 1367 break; 1368 case vccq_330: 1369 uvolt = 3300000; 1370 break; 1371 default: 1372 return EINVAL; 1373 } 1374 1375 err = regulator_set_voltage(sc->mmc_helper.vqmmc_supply, uvolt, uvolt); 1376 if (err != 0) { 1377 device_printf(sc->aw_dev, 1378 "Cannot set vqmmc to %d<->%d\n", 1379 uvolt, 1380 uvolt); 1381 return (err); 1382 } 1383 1384 return (0); 1385 } 1386 1387 static int 1388 aw_mmc_update_ios(device_t bus, device_t child) 1389 { 1390 int error; 1391 struct aw_mmc_softc *sc; 1392 struct mmc_ios *ios; 1393 unsigned int clock; 1394 uint32_t reg, div = 1; 1395 1396 sc = device_get_softc(bus); 1397 1398 ios = &sc->aw_host.ios; 1399 1400 /* Set the bus width. */ 1401 switch (ios->bus_width) { 1402 case bus_width_1: 1403 AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR1); 1404 break; 1405 case bus_width_4: 1406 AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR4); 1407 break; 1408 case bus_width_8: 1409 AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR8); 1410 break; 1411 } 1412 1413 switch (ios->power_mode) { 1414 case power_on: 1415 break; 1416 case power_off: 1417 if (bootverbose) 1418 device_printf(sc->aw_dev, "Powering down sd/mmc\n"); 1419 1420 if (sc->mmc_helper.vmmc_supply) 1421 regulator_disable(sc->mmc_helper.vmmc_supply); 1422 if (sc->mmc_helper.vqmmc_supply) 1423 regulator_disable(sc->mmc_helper.vqmmc_supply); 1424 1425 aw_mmc_reset(sc); 1426 break; 1427 case power_up: 1428 if (bootverbose) 1429 device_printf(sc->aw_dev, "Powering up sd/mmc\n"); 1430 1431 if (sc->mmc_helper.vmmc_supply) 1432 regulator_enable(sc->mmc_helper.vmmc_supply); 1433 if (sc->mmc_helper.vqmmc_supply) 1434 regulator_enable(sc->mmc_helper.vqmmc_supply); 1435 aw_mmc_init(sc); 1436 break; 1437 }; 1438 1439 /* Enable ddr mode if needed */ 1440 reg = AW_MMC_READ_4(sc, AW_MMC_GCTL); 1441 if (ios->timing == bus_timing_uhs_ddr50 || 1442 ios->timing == bus_timing_mmc_ddr52) 1443 reg |= AW_MMC_GCTL_DDR_MOD_SEL; 1444 else 1445 reg &= ~AW_MMC_GCTL_DDR_MOD_SEL; 1446 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg); 1447 1448 if (ios->clock && ios->clock != sc->aw_clock) { 1449 sc->aw_clock = clock = ios->clock; 1450 1451 /* Disable clock */ 1452 error = aw_mmc_update_clock(sc, 0); 1453 if (error != 0) 1454 return (error); 1455 1456 if (ios->timing == bus_timing_mmc_ddr52 && 1457 (sc->aw_mmc_conf->new_timing || 1458 ios->bus_width == bus_width_8)) { 1459 div = 2; 1460 clock <<= 1; 1461 } 1462 1463 /* Reset the divider. */ 1464 reg = AW_MMC_READ_4(sc, AW_MMC_CKCR); 1465 reg &= ~AW_MMC_CKCR_DIV; 1466 reg |= div - 1; 1467 AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg); 1468 1469 /* New timing mode if needed */ 1470 if (sc->aw_mmc_conf->new_timing) { 1471 reg = AW_MMC_READ_4(sc, AW_MMC_NTSR); 1472 reg |= AW_MMC_NTSR_MODE_SELECT; 1473 AW_MMC_WRITE_4(sc, AW_MMC_NTSR, reg); 1474 } 1475 1476 /* Set the MMC clock. */ 1477 error = clk_disable(sc->aw_clk_mmc); 1478 if (error != 0 && bootverbose) 1479 device_printf(sc->aw_dev, 1480 "failed to disable mmc clock: %d\n", error); 1481 error = clk_set_freq(sc->aw_clk_mmc, clock, 1482 CLK_SET_ROUND_DOWN); 1483 if (error != 0) { 1484 device_printf(sc->aw_dev, 1485 "failed to set frequency to %u Hz: %d\n", 1486 clock, error); 1487 return (error); 1488 } 1489 error = clk_enable(sc->aw_clk_mmc); 1490 if (error != 0 && bootverbose) 1491 device_printf(sc->aw_dev, 1492 "failed to re-enable mmc clock: %d\n", error); 1493 1494 if (sc->aw_mmc_conf->can_calibrate) 1495 AW_MMC_WRITE_4(sc, AW_MMC_SAMP_DL, AW_MMC_SAMP_DL_SW_EN); 1496 1497 /* Enable clock. */ 1498 error = aw_mmc_update_clock(sc, 1); 1499 if (error != 0) 1500 return (error); 1501 } 1502 1503 1504 return (0); 1505 } 1506 1507 static int 1508 aw_mmc_get_ro(device_t bus, device_t child) 1509 { 1510 struct aw_mmc_softc *sc; 1511 1512 sc = device_get_softc(bus); 1513 1514 return (mmc_fdt_gpio_get_readonly(&sc->mmc_helper)); 1515 } 1516 1517 static int 1518 aw_mmc_acquire_host(device_t bus, device_t child) 1519 { 1520 struct aw_mmc_softc *sc; 1521 int error; 1522 1523 sc = device_get_softc(bus); 1524 AW_MMC_LOCK(sc); 1525 while (sc->aw_bus_busy) { 1526 error = msleep(sc, &sc->aw_mtx, PCATCH, "mmchw", 0); 1527 if (error != 0) { 1528 AW_MMC_UNLOCK(sc); 1529 return (error); 1530 } 1531 } 1532 sc->aw_bus_busy++; 1533 AW_MMC_UNLOCK(sc); 1534 1535 return (0); 1536 } 1537 1538 static int 1539 aw_mmc_release_host(device_t bus, device_t child) 1540 { 1541 struct aw_mmc_softc *sc; 1542 1543 sc = device_get_softc(bus); 1544 AW_MMC_LOCK(sc); 1545 sc->aw_bus_busy--; 1546 wakeup(sc); 1547 AW_MMC_UNLOCK(sc); 1548 1549 return (0); 1550 } 1551 1552 static device_method_t aw_mmc_methods[] = { 1553 /* Device interface */ 1554 DEVMETHOD(device_probe, aw_mmc_probe), 1555 DEVMETHOD(device_attach, aw_mmc_attach), 1556 DEVMETHOD(device_detach, aw_mmc_detach), 1557 1558 /* Bus interface */ 1559 DEVMETHOD(bus_read_ivar, aw_mmc_read_ivar), 1560 DEVMETHOD(bus_write_ivar, aw_mmc_write_ivar), 1561 DEVMETHOD(bus_add_child, bus_generic_add_child), 1562 1563 /* MMC bridge interface */ 1564 DEVMETHOD(mmcbr_update_ios, aw_mmc_update_ios), 1565 DEVMETHOD(mmcbr_request, aw_mmc_request), 1566 DEVMETHOD(mmcbr_get_ro, aw_mmc_get_ro), 1567 DEVMETHOD(mmcbr_switch_vccq, aw_mmc_switch_vccq), 1568 DEVMETHOD(mmcbr_acquire_host, aw_mmc_acquire_host), 1569 DEVMETHOD(mmcbr_release_host, aw_mmc_release_host), 1570 1571 DEVMETHOD_END 1572 }; 1573 1574 static devclass_t aw_mmc_devclass; 1575 1576 static driver_t aw_mmc_driver = { 1577 "aw_mmc", 1578 aw_mmc_methods, 1579 sizeof(struct aw_mmc_softc), 1580 }; 1581 1582 DRIVER_MODULE(aw_mmc, simplebus, aw_mmc_driver, aw_mmc_devclass, NULL, 1583 NULL); 1584 #ifndef MMCCAM 1585 MMC_DECLARE_BRIDGE(aw_mmc); 1586 #endif 1587 SIMPLEBUS_PNP_INFO(compat_data); 1588