1 /*- 2 * Copyright (c) 2013 Alexander Fedorov 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/kernel.h> 34 #include <sys/lock.h> 35 #include <sys/malloc.h> 36 #include <sys/module.h> 37 #include <sys/mutex.h> 38 #include <sys/resource.h> 39 #include <sys/rman.h> 40 #include <sys/sysctl.h> 41 42 #include <machine/bus.h> 43 44 #include <dev/ofw/ofw_bus.h> 45 #include <dev/ofw/ofw_bus_subr.h> 46 47 #include <dev/mmc/bridge.h> 48 #include <dev/mmc/mmcbrvar.h> 49 50 #include <arm/allwinner/aw_mmc.h> 51 #include <dev/extres/clk/clk.h> 52 #include <dev/extres/hwreset/hwreset.h> 53 54 #define AW_MMC_MEMRES 0 55 #define AW_MMC_IRQRES 1 56 #define AW_MMC_RESSZ 2 57 #define AW_MMC_DMA_SEGS ((MAXPHYS / PAGE_SIZE) + 1) 58 #define AW_MMC_DMA_MAX_SIZE 0x2000 59 #define AW_MMC_DMA_FTRGLEVEL 0x20070008 60 #define AW_MMC_RESET_RETRY 1000 61 62 #define CARD_ID_FREQUENCY 400000 63 64 static struct ofw_compat_data compat_data[] = { 65 {"allwinner,sun4i-a10-mmc", 1}, 66 {"allwinner,sun5i-a13-mmc", 1}, 67 {"allwinner,sun7i-a20-mmc", 1}, 68 {"allwinner,sun50i-a64-mmc", 1}, 69 {NULL, 0} 70 }; 71 72 struct aw_mmc_softc { 73 device_t aw_dev; 74 clk_t aw_clk_ahb; 75 clk_t aw_clk_mmc; 76 hwreset_t aw_rst_ahb; 77 int aw_bus_busy; 78 int aw_resid; 79 int aw_timeout; 80 struct callout aw_timeoutc; 81 struct mmc_host aw_host; 82 struct mmc_request * aw_req; 83 struct mtx aw_mtx; 84 struct resource * aw_res[AW_MMC_RESSZ]; 85 uint32_t aw_intr; 86 uint32_t aw_intr_wait; 87 void * aw_intrhand; 88 89 /* Fields required for DMA access. */ 90 bus_addr_t aw_dma_desc_phys; 91 bus_dmamap_t aw_dma_map; 92 bus_dma_tag_t aw_dma_tag; 93 void * aw_dma_desc; 94 bus_dmamap_t aw_dma_buf_map; 95 bus_dma_tag_t aw_dma_buf_tag; 96 int aw_dma_map_err; 97 }; 98 99 static struct resource_spec aw_mmc_res_spec[] = { 100 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 101 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 102 { -1, 0, 0 } 103 }; 104 105 static int aw_mmc_probe(device_t); 106 static int aw_mmc_attach(device_t); 107 static int aw_mmc_detach(device_t); 108 static int aw_mmc_setup_dma(struct aw_mmc_softc *); 109 static int aw_mmc_reset(struct aw_mmc_softc *); 110 static void aw_mmc_intr(void *); 111 static int aw_mmc_update_clock(struct aw_mmc_softc *, uint32_t); 112 113 static int aw_mmc_update_ios(device_t, device_t); 114 static int aw_mmc_request(device_t, device_t, struct mmc_request *); 115 static int aw_mmc_get_ro(device_t, device_t); 116 static int aw_mmc_acquire_host(device_t, device_t); 117 static int aw_mmc_release_host(device_t, device_t); 118 119 #define AW_MMC_LOCK(_sc) mtx_lock(&(_sc)->aw_mtx) 120 #define AW_MMC_UNLOCK(_sc) mtx_unlock(&(_sc)->aw_mtx) 121 #define AW_MMC_READ_4(_sc, _reg) \ 122 bus_read_4((_sc)->aw_res[AW_MMC_MEMRES], _reg) 123 #define AW_MMC_WRITE_4(_sc, _reg, _value) \ 124 bus_write_4((_sc)->aw_res[AW_MMC_MEMRES], _reg, _value) 125 126 static int 127 aw_mmc_probe(device_t dev) 128 { 129 130 if (!ofw_bus_status_okay(dev)) 131 return (ENXIO); 132 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 133 return (ENXIO); 134 135 device_set_desc(dev, "Allwinner Integrated MMC/SD controller"); 136 137 return (BUS_PROBE_DEFAULT); 138 } 139 140 static int 141 aw_mmc_attach(device_t dev) 142 { 143 device_t child; 144 struct aw_mmc_softc *sc; 145 struct sysctl_ctx_list *ctx; 146 struct sysctl_oid_list *tree; 147 uint32_t bus_width; 148 phandle_t node; 149 int error; 150 151 node = ofw_bus_get_node(dev); 152 sc = device_get_softc(dev); 153 sc->aw_dev = dev; 154 sc->aw_req = NULL; 155 if (bus_alloc_resources(dev, aw_mmc_res_spec, sc->aw_res) != 0) { 156 device_printf(dev, "cannot allocate device resources\n"); 157 return (ENXIO); 158 } 159 if (bus_setup_intr(dev, sc->aw_res[AW_MMC_IRQRES], 160 INTR_TYPE_MISC | INTR_MPSAFE, NULL, aw_mmc_intr, sc, 161 &sc->aw_intrhand)) { 162 bus_release_resources(dev, aw_mmc_res_spec, sc->aw_res); 163 device_printf(dev, "cannot setup interrupt handler\n"); 164 return (ENXIO); 165 } 166 mtx_init(&sc->aw_mtx, device_get_nameunit(sc->aw_dev), "aw_mmc", 167 MTX_DEF); 168 callout_init_mtx(&sc->aw_timeoutc, &sc->aw_mtx, 0); 169 170 /* De-assert reset */ 171 if (hwreset_get_by_ofw_name(dev, 0, "ahb", &sc->aw_rst_ahb) == 0) { 172 error = hwreset_deassert(sc->aw_rst_ahb); 173 if (error != 0) { 174 device_printf(dev, "cannot de-assert reset\n"); 175 goto fail; 176 } 177 } 178 179 /* Activate the module clock. */ 180 error = clk_get_by_ofw_name(dev, 0, "ahb", &sc->aw_clk_ahb); 181 if (error != 0) { 182 device_printf(dev, "cannot get ahb clock\n"); 183 goto fail; 184 } 185 error = clk_enable(sc->aw_clk_ahb); 186 if (error != 0) { 187 device_printf(dev, "cannot enable ahb clock\n"); 188 goto fail; 189 } 190 error = clk_get_by_ofw_name(dev, 0, "mmc", &sc->aw_clk_mmc); 191 if (error != 0) { 192 device_printf(dev, "cannot get mmc clock\n"); 193 goto fail; 194 } 195 error = clk_set_freq(sc->aw_clk_mmc, CARD_ID_FREQUENCY, 196 CLK_SET_ROUND_DOWN); 197 if (error != 0) { 198 device_printf(dev, "cannot init mmc clock\n"); 199 goto fail; 200 } 201 error = clk_enable(sc->aw_clk_mmc); 202 if (error != 0) { 203 device_printf(dev, "cannot enable mmc clock\n"); 204 goto fail; 205 } 206 207 sc->aw_timeout = 10; 208 ctx = device_get_sysctl_ctx(dev); 209 tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 210 SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "req_timeout", CTLFLAG_RW, 211 &sc->aw_timeout, 0, "Request timeout in seconds"); 212 213 /* Hardware reset */ 214 AW_MMC_WRITE_4(sc, AW_MMC_HWRST, 1); 215 DELAY(100); 216 AW_MMC_WRITE_4(sc, AW_MMC_HWRST, 0); 217 DELAY(500); 218 219 /* Soft Reset controller. */ 220 if (aw_mmc_reset(sc) != 0) { 221 device_printf(dev, "cannot reset the controller\n"); 222 goto fail; 223 } 224 225 if (aw_mmc_setup_dma(sc) != 0) { 226 device_printf(sc->aw_dev, "Couldn't setup DMA!\n"); 227 goto fail; 228 } 229 230 if (OF_getencprop(node, "bus-width", &bus_width, sizeof(uint32_t)) <= 0) 231 bus_width = 4; 232 233 sc->aw_host.f_min = 400000; 234 sc->aw_host.f_max = 52000000; 235 sc->aw_host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340; 236 sc->aw_host.mode = mode_sd; 237 sc->aw_host.caps = MMC_CAP_HSPEED; 238 if (bus_width >= 4) 239 sc->aw_host.caps |= MMC_CAP_4_BIT_DATA; 240 if (bus_width >= 8) 241 sc->aw_host.caps |= MMC_CAP_8_BIT_DATA; 242 243 child = device_add_child(dev, "mmc", -1); 244 if (child == NULL) { 245 device_printf(dev, "attaching MMC bus failed!\n"); 246 goto fail; 247 } 248 if (device_probe_and_attach(child) != 0) { 249 device_printf(dev, "attaching MMC child failed!\n"); 250 device_delete_child(dev, child); 251 goto fail; 252 } 253 254 return (0); 255 256 fail: 257 callout_drain(&sc->aw_timeoutc); 258 mtx_destroy(&sc->aw_mtx); 259 bus_teardown_intr(dev, sc->aw_res[AW_MMC_IRQRES], sc->aw_intrhand); 260 bus_release_resources(dev, aw_mmc_res_spec, sc->aw_res); 261 262 return (ENXIO); 263 } 264 265 static int 266 aw_mmc_detach(device_t dev) 267 { 268 269 return (EBUSY); 270 } 271 272 static void 273 aw_dma_desc_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err) 274 { 275 struct aw_mmc_softc *sc; 276 277 sc = (struct aw_mmc_softc *)arg; 278 if (err) { 279 sc->aw_dma_map_err = err; 280 return; 281 } 282 sc->aw_dma_desc_phys = segs[0].ds_addr; 283 } 284 285 static int 286 aw_mmc_setup_dma(struct aw_mmc_softc *sc) 287 { 288 int dma_desc_size, error; 289 290 /* Allocate the DMA descriptor memory. */ 291 dma_desc_size = sizeof(struct aw_mmc_dma_desc) * AW_MMC_DMA_SEGS; 292 error = bus_dma_tag_create(bus_get_dma_tag(sc->aw_dev), 293 AW_MMC_DMA_ALIGN, 0, 294 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 295 dma_desc_size, 1, dma_desc_size, 0, NULL, NULL, &sc->aw_dma_tag); 296 if (error) 297 return (error); 298 error = bus_dmamem_alloc(sc->aw_dma_tag, &sc->aw_dma_desc, 299 BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->aw_dma_map); 300 if (error) 301 return (error); 302 303 error = bus_dmamap_load(sc->aw_dma_tag, sc->aw_dma_map, 304 sc->aw_dma_desc, dma_desc_size, aw_dma_desc_cb, sc, 0); 305 if (error) 306 return (error); 307 if (sc->aw_dma_map_err) 308 return (sc->aw_dma_map_err); 309 310 /* Create the DMA map for data transfers. */ 311 error = bus_dma_tag_create(bus_get_dma_tag(sc->aw_dev), 312 AW_MMC_DMA_ALIGN, 0, 313 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 314 AW_MMC_DMA_MAX_SIZE * AW_MMC_DMA_SEGS, AW_MMC_DMA_SEGS, 315 AW_MMC_DMA_MAX_SIZE, BUS_DMA_ALLOCNOW, NULL, NULL, 316 &sc->aw_dma_buf_tag); 317 if (error) 318 return (error); 319 error = bus_dmamap_create(sc->aw_dma_buf_tag, 0, 320 &sc->aw_dma_buf_map); 321 if (error) 322 return (error); 323 324 return (0); 325 } 326 327 static void 328 aw_dma_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err) 329 { 330 int i; 331 struct aw_mmc_dma_desc *dma_desc; 332 struct aw_mmc_softc *sc; 333 334 sc = (struct aw_mmc_softc *)arg; 335 sc->aw_dma_map_err = err; 336 337 if (err) 338 return; 339 340 dma_desc = sc->aw_dma_desc; 341 for (i = 0; i < nsegs; i++) { 342 dma_desc[i].buf_size = segs[i].ds_len; 343 dma_desc[i].buf_addr = segs[i].ds_addr; 344 dma_desc[i].config = AW_MMC_DMA_CONFIG_CH | 345 AW_MMC_DMA_CONFIG_OWN; 346 if (i == 0) 347 dma_desc[i].config |= AW_MMC_DMA_CONFIG_FD; 348 if (i < (nsegs - 1)) { 349 dma_desc[i].config |= AW_MMC_DMA_CONFIG_DIC; 350 dma_desc[i].next = sc->aw_dma_desc_phys + 351 ((i + 1) * sizeof(struct aw_mmc_dma_desc)); 352 } else { 353 dma_desc[i].config |= AW_MMC_DMA_CONFIG_LD | 354 AW_MMC_DMA_CONFIG_ER; 355 dma_desc[i].next = 0; 356 } 357 } 358 } 359 360 static int 361 aw_mmc_prepare_dma(struct aw_mmc_softc *sc) 362 { 363 bus_dmasync_op_t sync_op; 364 int error; 365 struct mmc_command *cmd; 366 uint32_t val; 367 368 cmd = sc->aw_req->cmd; 369 if (cmd->data->len > AW_MMC_DMA_MAX_SIZE * AW_MMC_DMA_SEGS) 370 return (EFBIG); 371 error = bus_dmamap_load(sc->aw_dma_buf_tag, sc->aw_dma_buf_map, 372 cmd->data->data, cmd->data->len, aw_dma_cb, sc, 0); 373 if (error) 374 return (error); 375 if (sc->aw_dma_map_err) 376 return (sc->aw_dma_map_err); 377 378 if (cmd->data->flags & MMC_DATA_WRITE) 379 sync_op = BUS_DMASYNC_PREWRITE; 380 else 381 sync_op = BUS_DMASYNC_PREREAD; 382 bus_dmamap_sync(sc->aw_dma_buf_tag, sc->aw_dma_buf_map, sync_op); 383 bus_dmamap_sync(sc->aw_dma_tag, sc->aw_dma_map, BUS_DMASYNC_PREWRITE); 384 385 /* Enable DMA */ 386 val = AW_MMC_READ_4(sc, AW_MMC_GCTL); 387 val &= ~AW_MMC_CTRL_FIFO_AC_MOD; 388 val |= AW_MMC_CTRL_DMA_ENB; 389 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val); 390 391 /* Reset DMA */ 392 val |= AW_MMC_CTRL_DMA_RST; 393 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val); 394 395 AW_MMC_WRITE_4(sc, AW_MMC_DMAC, AW_MMC_DMAC_IDMAC_SOFT_RST); 396 AW_MMC_WRITE_4(sc, AW_MMC_DMAC, 397 AW_MMC_DMAC_IDMAC_IDMA_ON | AW_MMC_DMAC_IDMAC_FIX_BURST); 398 399 /* Enable RX or TX DMA interrupt */ 400 if (cmd->data->flags & MMC_DATA_WRITE) 401 val |= AW_MMC_IDST_TX_INT; 402 else 403 val |= AW_MMC_IDST_RX_INT; 404 AW_MMC_WRITE_4(sc, AW_MMC_IDIE, val); 405 406 /* Set DMA descritptor list address */ 407 AW_MMC_WRITE_4(sc, AW_MMC_DLBA, sc->aw_dma_desc_phys); 408 409 /* FIFO trigger level */ 410 AW_MMC_WRITE_4(sc, AW_MMC_FWLR, AW_MMC_DMA_FTRGLEVEL); 411 412 return (0); 413 } 414 415 static int 416 aw_mmc_reset(struct aw_mmc_softc *sc) 417 { 418 int timeout; 419 420 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, AW_MMC_RESET); 421 timeout = 1000; 422 while (--timeout > 0) { 423 if ((AW_MMC_READ_4(sc, AW_MMC_GCTL) & AW_MMC_RESET) == 0) 424 break; 425 DELAY(100); 426 } 427 if (timeout == 0) 428 return (ETIMEDOUT); 429 430 /* Set the timeout. */ 431 AW_MMC_WRITE_4(sc, AW_MMC_TMOR, 432 AW_MMC_TMOR_DTO_LMT_SHIFT(AW_MMC_TMOR_DTO_LMT_MASK) | 433 AW_MMC_TMOR_RTO_LMT_SHIFT(AW_MMC_TMOR_RTO_LMT_MASK)); 434 435 /* Clear pending interrupts. */ 436 AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff); 437 AW_MMC_WRITE_4(sc, AW_MMC_IDST, 0xffffffff); 438 /* Unmask interrupts. */ 439 AW_MMC_WRITE_4(sc, AW_MMC_IMKR, 440 AW_MMC_INT_CMD_DONE | AW_MMC_INT_ERR_BIT | 441 AW_MMC_INT_DATA_OVER | AW_MMC_INT_AUTO_STOP_DONE); 442 /* Enable interrupts and AHB access. */ 443 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, 444 AW_MMC_READ_4(sc, AW_MMC_GCTL) | AW_MMC_CTRL_INT_ENB); 445 446 return (0); 447 } 448 449 static void 450 aw_mmc_req_done(struct aw_mmc_softc *sc) 451 { 452 struct mmc_command *cmd; 453 struct mmc_request *req; 454 uint32_t val, mask; 455 int retry; 456 457 cmd = sc->aw_req->cmd; 458 if (cmd->error != MMC_ERR_NONE) { 459 /* Reset the FIFO and DMA engines. */ 460 mask = AW_MMC_CTRL_FIFO_RST | AW_MMC_CTRL_DMA_RST; 461 val = AW_MMC_READ_4(sc, AW_MMC_GCTL); 462 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val | mask); 463 464 retry = AW_MMC_RESET_RETRY; 465 while (--retry > 0) { 466 val = AW_MMC_READ_4(sc, AW_MMC_GCTL); 467 if ((val & mask) == 0) 468 break; 469 DELAY(10); 470 } 471 if (retry == 0) 472 device_printf(sc->aw_dev, 473 "timeout resetting DMA/FIFO\n"); 474 aw_mmc_update_clock(sc, 1); 475 } 476 477 req = sc->aw_req; 478 callout_stop(&sc->aw_timeoutc); 479 sc->aw_req = NULL; 480 sc->aw_intr = 0; 481 sc->aw_resid = 0; 482 sc->aw_dma_map_err = 0; 483 sc->aw_intr_wait = 0; 484 req->done(req); 485 } 486 487 static void 488 aw_mmc_req_ok(struct aw_mmc_softc *sc) 489 { 490 int timeout; 491 struct mmc_command *cmd; 492 uint32_t status; 493 494 timeout = 1000; 495 while (--timeout > 0) { 496 status = AW_MMC_READ_4(sc, AW_MMC_STAR); 497 if ((status & AW_MMC_STAR_CARD_BUSY) == 0) 498 break; 499 DELAY(1000); 500 } 501 cmd = sc->aw_req->cmd; 502 if (timeout == 0) { 503 cmd->error = MMC_ERR_FAILED; 504 aw_mmc_req_done(sc); 505 return; 506 } 507 if (cmd->flags & MMC_RSP_PRESENT) { 508 if (cmd->flags & MMC_RSP_136) { 509 cmd->resp[0] = AW_MMC_READ_4(sc, AW_MMC_RESP3); 510 cmd->resp[1] = AW_MMC_READ_4(sc, AW_MMC_RESP2); 511 cmd->resp[2] = AW_MMC_READ_4(sc, AW_MMC_RESP1); 512 cmd->resp[3] = AW_MMC_READ_4(sc, AW_MMC_RESP0); 513 } else 514 cmd->resp[0] = AW_MMC_READ_4(sc, AW_MMC_RESP0); 515 } 516 /* All data has been transferred ? */ 517 if (cmd->data != NULL && (sc->aw_resid << 2) < cmd->data->len) 518 cmd->error = MMC_ERR_FAILED; 519 aw_mmc_req_done(sc); 520 } 521 522 static void 523 aw_mmc_timeout(void *arg) 524 { 525 struct aw_mmc_softc *sc; 526 527 sc = (struct aw_mmc_softc *)arg; 528 if (sc->aw_req != NULL) { 529 device_printf(sc->aw_dev, "controller timeout\n"); 530 sc->aw_req->cmd->error = MMC_ERR_TIMEOUT; 531 aw_mmc_req_done(sc); 532 } else 533 device_printf(sc->aw_dev, 534 "Spurious timeout - no active request\n"); 535 } 536 537 static void 538 aw_mmc_intr(void *arg) 539 { 540 bus_dmasync_op_t sync_op; 541 struct aw_mmc_softc *sc; 542 struct mmc_data *data; 543 uint32_t idst, imask, rint; 544 545 sc = (struct aw_mmc_softc *)arg; 546 AW_MMC_LOCK(sc); 547 rint = AW_MMC_READ_4(sc, AW_MMC_RISR); 548 idst = AW_MMC_READ_4(sc, AW_MMC_IDST); 549 imask = AW_MMC_READ_4(sc, AW_MMC_IMKR); 550 if (idst == 0 && imask == 0 && rint == 0) { 551 AW_MMC_UNLOCK(sc); 552 return; 553 } 554 #ifdef DEBUG 555 device_printf(sc->aw_dev, "idst: %#x, imask: %#x, rint: %#x\n", 556 idst, imask, rint); 557 #endif 558 if (sc->aw_req == NULL) { 559 device_printf(sc->aw_dev, 560 "Spurious interrupt - no active request, rint: 0x%08X\n", 561 rint); 562 goto end; 563 } 564 if (rint & AW_MMC_INT_ERR_BIT) { 565 device_printf(sc->aw_dev, "error rint: 0x%08X\n", rint); 566 if (rint & AW_MMC_INT_RESP_TIMEOUT) 567 sc->aw_req->cmd->error = MMC_ERR_TIMEOUT; 568 else 569 sc->aw_req->cmd->error = MMC_ERR_FAILED; 570 aw_mmc_req_done(sc); 571 goto end; 572 } 573 if (idst & AW_MMC_IDST_ERROR) { 574 device_printf(sc->aw_dev, "error idst: 0x%08x\n", idst); 575 sc->aw_req->cmd->error = MMC_ERR_FAILED; 576 aw_mmc_req_done(sc); 577 goto end; 578 } 579 580 sc->aw_intr |= rint; 581 data = sc->aw_req->cmd->data; 582 if (data != NULL && (idst & AW_MMC_IDST_COMPLETE) != 0) { 583 if (data->flags & MMC_DATA_WRITE) 584 sync_op = BUS_DMASYNC_POSTWRITE; 585 else 586 sync_op = BUS_DMASYNC_POSTREAD; 587 bus_dmamap_sync(sc->aw_dma_buf_tag, sc->aw_dma_buf_map, 588 sync_op); 589 bus_dmamap_sync(sc->aw_dma_tag, sc->aw_dma_map, 590 BUS_DMASYNC_POSTWRITE); 591 bus_dmamap_unload(sc->aw_dma_buf_tag, sc->aw_dma_buf_map); 592 sc->aw_resid = data->len >> 2; 593 } 594 if ((sc->aw_intr & sc->aw_intr_wait) == sc->aw_intr_wait) 595 aw_mmc_req_ok(sc); 596 597 end: 598 AW_MMC_WRITE_4(sc, AW_MMC_IDST, idst); 599 AW_MMC_WRITE_4(sc, AW_MMC_RISR, rint); 600 AW_MMC_UNLOCK(sc); 601 } 602 603 static int 604 aw_mmc_request(device_t bus, device_t child, struct mmc_request *req) 605 { 606 int blksz; 607 struct aw_mmc_softc *sc; 608 struct mmc_command *cmd; 609 uint32_t cmdreg; 610 int err; 611 612 sc = device_get_softc(bus); 613 AW_MMC_LOCK(sc); 614 if (sc->aw_req) { 615 AW_MMC_UNLOCK(sc); 616 return (EBUSY); 617 } 618 sc->aw_req = req; 619 cmd = req->cmd; 620 cmdreg = AW_MMC_CMDR_LOAD; 621 if (cmd->opcode == MMC_GO_IDLE_STATE) 622 cmdreg |= AW_MMC_CMDR_SEND_INIT_SEQ; 623 if (cmd->flags & MMC_RSP_PRESENT) 624 cmdreg |= AW_MMC_CMDR_RESP_RCV; 625 if (cmd->flags & MMC_RSP_136) 626 cmdreg |= AW_MMC_CMDR_LONG_RESP; 627 if (cmd->flags & MMC_RSP_CRC) 628 cmdreg |= AW_MMC_CMDR_CHK_RESP_CRC; 629 630 sc->aw_intr = 0; 631 sc->aw_resid = 0; 632 sc->aw_intr_wait = AW_MMC_INT_CMD_DONE; 633 cmd->error = MMC_ERR_NONE; 634 if (cmd->data != NULL) { 635 sc->aw_intr_wait |= AW_MMC_INT_DATA_OVER; 636 cmdreg |= AW_MMC_CMDR_DATA_TRANS | AW_MMC_CMDR_WAIT_PRE_OVER; 637 if (cmd->data->flags & MMC_DATA_MULTI) { 638 cmdreg |= AW_MMC_CMDR_STOP_CMD_FLAG; 639 sc->aw_intr_wait |= AW_MMC_INT_AUTO_STOP_DONE; 640 } 641 if (cmd->data->flags & MMC_DATA_WRITE) 642 cmdreg |= AW_MMC_CMDR_DIR_WRITE; 643 blksz = min(cmd->data->len, MMC_SECTOR_SIZE); 644 AW_MMC_WRITE_4(sc, AW_MMC_BKSR, blksz); 645 AW_MMC_WRITE_4(sc, AW_MMC_BYCR, cmd->data->len); 646 647 err = aw_mmc_prepare_dma(sc); 648 if (err != 0) 649 device_printf(sc->aw_dev, "prepare_dma failed: %d\n", err); 650 } 651 652 AW_MMC_WRITE_4(sc, AW_MMC_CAGR, cmd->arg); 653 AW_MMC_WRITE_4(sc, AW_MMC_CMDR, cmdreg | cmd->opcode); 654 callout_reset(&sc->aw_timeoutc, sc->aw_timeout * hz, 655 aw_mmc_timeout, sc); 656 AW_MMC_UNLOCK(sc); 657 658 return (0); 659 } 660 661 static int 662 aw_mmc_read_ivar(device_t bus, device_t child, int which, 663 uintptr_t *result) 664 { 665 struct aw_mmc_softc *sc; 666 667 sc = device_get_softc(bus); 668 switch (which) { 669 default: 670 return (EINVAL); 671 case MMCBR_IVAR_BUS_MODE: 672 *(int *)result = sc->aw_host.ios.bus_mode; 673 break; 674 case MMCBR_IVAR_BUS_WIDTH: 675 *(int *)result = sc->aw_host.ios.bus_width; 676 break; 677 case MMCBR_IVAR_CHIP_SELECT: 678 *(int *)result = sc->aw_host.ios.chip_select; 679 break; 680 case MMCBR_IVAR_CLOCK: 681 *(int *)result = sc->aw_host.ios.clock; 682 break; 683 case MMCBR_IVAR_F_MIN: 684 *(int *)result = sc->aw_host.f_min; 685 break; 686 case MMCBR_IVAR_F_MAX: 687 *(int *)result = sc->aw_host.f_max; 688 break; 689 case MMCBR_IVAR_HOST_OCR: 690 *(int *)result = sc->aw_host.host_ocr; 691 break; 692 case MMCBR_IVAR_MODE: 693 *(int *)result = sc->aw_host.mode; 694 break; 695 case MMCBR_IVAR_OCR: 696 *(int *)result = sc->aw_host.ocr; 697 break; 698 case MMCBR_IVAR_POWER_MODE: 699 *(int *)result = sc->aw_host.ios.power_mode; 700 break; 701 case MMCBR_IVAR_VDD: 702 *(int *)result = sc->aw_host.ios.vdd; 703 break; 704 case MMCBR_IVAR_CAPS: 705 *(int *)result = sc->aw_host.caps; 706 break; 707 case MMCBR_IVAR_MAX_DATA: 708 *(int *)result = 65535; 709 break; 710 } 711 712 return (0); 713 } 714 715 static int 716 aw_mmc_write_ivar(device_t bus, device_t child, int which, 717 uintptr_t value) 718 { 719 struct aw_mmc_softc *sc; 720 721 sc = device_get_softc(bus); 722 switch (which) { 723 default: 724 return (EINVAL); 725 case MMCBR_IVAR_BUS_MODE: 726 sc->aw_host.ios.bus_mode = value; 727 break; 728 case MMCBR_IVAR_BUS_WIDTH: 729 sc->aw_host.ios.bus_width = value; 730 break; 731 case MMCBR_IVAR_CHIP_SELECT: 732 sc->aw_host.ios.chip_select = value; 733 break; 734 case MMCBR_IVAR_CLOCK: 735 sc->aw_host.ios.clock = value; 736 break; 737 case MMCBR_IVAR_MODE: 738 sc->aw_host.mode = value; 739 break; 740 case MMCBR_IVAR_OCR: 741 sc->aw_host.ocr = value; 742 break; 743 case MMCBR_IVAR_POWER_MODE: 744 sc->aw_host.ios.power_mode = value; 745 break; 746 case MMCBR_IVAR_VDD: 747 sc->aw_host.ios.vdd = value; 748 break; 749 /* These are read-only */ 750 case MMCBR_IVAR_CAPS: 751 case MMCBR_IVAR_HOST_OCR: 752 case MMCBR_IVAR_F_MIN: 753 case MMCBR_IVAR_F_MAX: 754 case MMCBR_IVAR_MAX_DATA: 755 return (EINVAL); 756 } 757 758 return (0); 759 } 760 761 static int 762 aw_mmc_update_clock(struct aw_mmc_softc *sc, uint32_t clkon) 763 { 764 uint32_t cmdreg; 765 int retry; 766 uint32_t ckcr; 767 768 ckcr = AW_MMC_READ_4(sc, AW_MMC_CKCR); 769 ckcr &= ~(AW_MMC_CKCR_CCLK_ENB | AW_MMC_CKCR_CCLK_CTRL); 770 771 if (clkon) 772 ckcr |= AW_MMC_CKCR_CCLK_ENB; 773 774 AW_MMC_WRITE_4(sc, AW_MMC_CKCR, ckcr); 775 776 cmdreg = AW_MMC_CMDR_LOAD | AW_MMC_CMDR_PRG_CLK | 777 AW_MMC_CMDR_WAIT_PRE_OVER; 778 AW_MMC_WRITE_4(sc, AW_MMC_CMDR, cmdreg); 779 retry = 0xfffff; 780 while (--retry > 0) { 781 if ((AW_MMC_READ_4(sc, AW_MMC_CMDR) & AW_MMC_CMDR_LOAD) == 0) { 782 AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff); 783 return (0); 784 } 785 DELAY(10); 786 } 787 AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff); 788 device_printf(sc->aw_dev, "timeout updating clock\n"); 789 790 return (ETIMEDOUT); 791 } 792 793 static int 794 aw_mmc_update_ios(device_t bus, device_t child) 795 { 796 int error; 797 struct aw_mmc_softc *sc; 798 struct mmc_ios *ios; 799 uint32_t ckcr; 800 801 sc = device_get_softc(bus); 802 803 ios = &sc->aw_host.ios; 804 805 /* Set the bus width. */ 806 switch (ios->bus_width) { 807 case bus_width_1: 808 AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR1); 809 break; 810 case bus_width_4: 811 AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR4); 812 break; 813 case bus_width_8: 814 AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR8); 815 break; 816 } 817 818 if (ios->clock) { 819 820 /* Disable clock */ 821 error = aw_mmc_update_clock(sc, 0); 822 if (error != 0) 823 return (error); 824 825 /* Reset the divider. */ 826 ckcr = AW_MMC_READ_4(sc, AW_MMC_CKCR); 827 ckcr &= ~AW_MMC_CKCR_CCLK_DIV; 828 AW_MMC_WRITE_4(sc, AW_MMC_CKCR, ckcr); 829 830 /* Set the MMC clock. */ 831 error = clk_set_freq(sc->aw_clk_mmc, ios->clock, 832 CLK_SET_ROUND_DOWN); 833 if (error != 0) { 834 device_printf(sc->aw_dev, 835 "failed to set frequency to %u Hz: %d\n", 836 ios->clock, error); 837 return (error); 838 } 839 840 /* Enable clock. */ 841 error = aw_mmc_update_clock(sc, 1); 842 if (error != 0) 843 return (error); 844 } 845 846 847 return (0); 848 } 849 850 static int 851 aw_mmc_get_ro(device_t bus, device_t child) 852 { 853 854 return (0); 855 } 856 857 static int 858 aw_mmc_acquire_host(device_t bus, device_t child) 859 { 860 struct aw_mmc_softc *sc; 861 int error; 862 863 sc = device_get_softc(bus); 864 AW_MMC_LOCK(sc); 865 while (sc->aw_bus_busy) { 866 error = msleep(sc, &sc->aw_mtx, PCATCH, "mmchw", 0); 867 if (error != 0) { 868 AW_MMC_UNLOCK(sc); 869 return (error); 870 } 871 } 872 sc->aw_bus_busy++; 873 AW_MMC_UNLOCK(sc); 874 875 return (0); 876 } 877 878 static int 879 aw_mmc_release_host(device_t bus, device_t child) 880 { 881 struct aw_mmc_softc *sc; 882 883 sc = device_get_softc(bus); 884 AW_MMC_LOCK(sc); 885 sc->aw_bus_busy--; 886 wakeup(sc); 887 AW_MMC_UNLOCK(sc); 888 889 return (0); 890 } 891 892 static device_method_t aw_mmc_methods[] = { 893 /* Device interface */ 894 DEVMETHOD(device_probe, aw_mmc_probe), 895 DEVMETHOD(device_attach, aw_mmc_attach), 896 DEVMETHOD(device_detach, aw_mmc_detach), 897 898 /* Bus interface */ 899 DEVMETHOD(bus_read_ivar, aw_mmc_read_ivar), 900 DEVMETHOD(bus_write_ivar, aw_mmc_write_ivar), 901 902 /* MMC bridge interface */ 903 DEVMETHOD(mmcbr_update_ios, aw_mmc_update_ios), 904 DEVMETHOD(mmcbr_request, aw_mmc_request), 905 DEVMETHOD(mmcbr_get_ro, aw_mmc_get_ro), 906 DEVMETHOD(mmcbr_acquire_host, aw_mmc_acquire_host), 907 DEVMETHOD(mmcbr_release_host, aw_mmc_release_host), 908 909 DEVMETHOD_END 910 }; 911 912 static devclass_t aw_mmc_devclass; 913 914 static driver_t aw_mmc_driver = { 915 "aw_mmc", 916 aw_mmc_methods, 917 sizeof(struct aw_mmc_softc), 918 }; 919 920 DRIVER_MODULE(aw_mmc, simplebus, aw_mmc_driver, aw_mmc_devclass, NULL, 921 NULL); 922 MMC_DECLARE_BRIDGE(aw_mmc); 923