1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org> 5 * Copyright (c) 2013 Alexander Fedorov 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/kernel.h> 37 #include <sys/lock.h> 38 #include <sys/malloc.h> 39 #include <sys/module.h> 40 #include <sys/mutex.h> 41 #include <sys/resource.h> 42 #include <sys/rman.h> 43 #include <sys/sysctl.h> 44 #include <sys/queue.h> 45 #include <sys/taskqueue.h> 46 47 #include <machine/bus.h> 48 49 #include <dev/ofw/ofw_bus.h> 50 #include <dev/ofw/ofw_bus_subr.h> 51 52 #include <dev/mmc/bridge.h> 53 #include <dev/mmc/mmcbrvar.h> 54 #include <dev/mmc/mmc_fdt_helpers.h> 55 56 #include <arm/allwinner/aw_mmc.h> 57 #include <dev/extres/clk/clk.h> 58 #include <dev/extres/hwreset/hwreset.h> 59 #include <dev/extres/regulator/regulator.h> 60 61 #include "opt_mmccam.h" 62 63 #ifdef MMCCAM 64 #include <cam/cam.h> 65 #include <cam/cam_ccb.h> 66 #include <cam/cam_debug.h> 67 #include <cam/cam_sim.h> 68 #include <cam/cam_xpt_sim.h> 69 #endif 70 71 #define AW_MMC_MEMRES 0 72 #define AW_MMC_IRQRES 1 73 #define AW_MMC_RESSZ 2 74 #define AW_MMC_DMA_SEGS (PAGE_SIZE / sizeof(struct aw_mmc_dma_desc)) 75 #define AW_MMC_DMA_DESC_SIZE (sizeof(struct aw_mmc_dma_desc) * AW_MMC_DMA_SEGS) 76 #define AW_MMC_DMA_FTRGLEVEL 0x20070008 77 78 #define AW_MMC_RESET_RETRY 1000 79 80 #define CARD_ID_FREQUENCY 400000 81 82 struct aw_mmc_conf { 83 uint32_t dma_xferlen; 84 bool mask_data0; 85 bool can_calibrate; 86 bool new_timing; 87 }; 88 89 static const struct aw_mmc_conf a10_mmc_conf = { 90 .dma_xferlen = 0x2000, 91 }; 92 93 static const struct aw_mmc_conf a13_mmc_conf = { 94 .dma_xferlen = 0x10000, 95 }; 96 97 static const struct aw_mmc_conf a64_mmc_conf = { 98 .dma_xferlen = 0x10000, 99 .mask_data0 = true, 100 .can_calibrate = true, 101 .new_timing = true, 102 }; 103 104 static const struct aw_mmc_conf a64_emmc_conf = { 105 .dma_xferlen = 0x2000, 106 .can_calibrate = true, 107 }; 108 109 static struct ofw_compat_data compat_data[] = { 110 {"allwinner,sun4i-a10-mmc", (uintptr_t)&a10_mmc_conf}, 111 {"allwinner,sun5i-a13-mmc", (uintptr_t)&a13_mmc_conf}, 112 {"allwinner,sun7i-a20-mmc", (uintptr_t)&a13_mmc_conf}, 113 {"allwinner,sun50i-a64-mmc", (uintptr_t)&a64_mmc_conf}, 114 {"allwinner,sun50i-a64-emmc", (uintptr_t)&a64_emmc_conf}, 115 {NULL, 0} 116 }; 117 118 struct aw_mmc_softc { 119 device_t aw_dev; 120 clk_t aw_clk_ahb; 121 clk_t aw_clk_mmc; 122 hwreset_t aw_rst_ahb; 123 int aw_bus_busy; 124 int aw_resid; 125 int aw_timeout; 126 struct callout aw_timeoutc; 127 struct mmc_host aw_host; 128 struct mmc_fdt_helper mmc_helper; 129 #ifdef MMCCAM 130 union ccb * ccb; 131 struct cam_devq * devq; 132 struct cam_sim * sim; 133 struct mtx sim_mtx; 134 #else 135 struct mmc_request * aw_req; 136 #endif 137 struct mtx aw_mtx; 138 struct resource * aw_res[AW_MMC_RESSZ]; 139 struct aw_mmc_conf * aw_mmc_conf; 140 uint32_t aw_intr; 141 uint32_t aw_intr_wait; 142 void * aw_intrhand; 143 unsigned int aw_clock; 144 device_t child; 145 146 /* Fields required for DMA access. */ 147 bus_addr_t aw_dma_desc_phys; 148 bus_dmamap_t aw_dma_map; 149 bus_dma_tag_t aw_dma_tag; 150 void * aw_dma_desc; 151 bus_dmamap_t aw_dma_buf_map; 152 bus_dma_tag_t aw_dma_buf_tag; 153 int aw_dma_map_err; 154 }; 155 156 static struct resource_spec aw_mmc_res_spec[] = { 157 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 158 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 159 { -1, 0, 0 } 160 }; 161 162 static int aw_mmc_probe(device_t); 163 static int aw_mmc_attach(device_t); 164 static int aw_mmc_detach(device_t); 165 static int aw_mmc_setup_dma(struct aw_mmc_softc *); 166 static int aw_mmc_reset(struct aw_mmc_softc *); 167 static int aw_mmc_init(struct aw_mmc_softc *); 168 static void aw_mmc_intr(void *); 169 static int aw_mmc_update_clock(struct aw_mmc_softc *, uint32_t); 170 static void aw_mmc_helper_cd_handler(device_t, bool); 171 172 static void aw_mmc_print_error(uint32_t); 173 static int aw_mmc_update_ios(device_t, device_t); 174 static int aw_mmc_request(device_t, device_t, struct mmc_request *); 175 static int aw_mmc_get_ro(device_t, device_t); 176 static int aw_mmc_acquire_host(device_t, device_t); 177 static int aw_mmc_release_host(device_t, device_t); 178 #ifdef MMCCAM 179 static void aw_mmc_cam_action(struct cam_sim *, union ccb *); 180 static void aw_mmc_cam_poll(struct cam_sim *); 181 static int aw_mmc_cam_settran_settings(struct aw_mmc_softc *, union ccb *); 182 static int aw_mmc_cam_request(struct aw_mmc_softc *, union ccb *); 183 static void aw_mmc_cam_handle_mmcio(struct cam_sim *, union ccb *); 184 #endif 185 186 #define AW_MMC_LOCK(_sc) mtx_lock(&(_sc)->aw_mtx) 187 #define AW_MMC_UNLOCK(_sc) mtx_unlock(&(_sc)->aw_mtx) 188 #define AW_MMC_READ_4(_sc, _reg) \ 189 bus_read_4((_sc)->aw_res[AW_MMC_MEMRES], _reg) 190 #define AW_MMC_WRITE_4(_sc, _reg, _value) \ 191 bus_write_4((_sc)->aw_res[AW_MMC_MEMRES], _reg, _value) 192 193 #ifdef MMCCAM 194 static void 195 aw_mmc_cam_handle_mmcio(struct cam_sim *sim, union ccb *ccb) 196 { 197 struct aw_mmc_softc *sc; 198 199 sc = cam_sim_softc(sim); 200 201 aw_mmc_cam_request(sc, ccb); 202 } 203 204 static void 205 aw_mmc_cam_action(struct cam_sim *sim, union ccb *ccb) 206 { 207 struct aw_mmc_softc *sc; 208 209 sc = cam_sim_softc(sim); 210 if (sc == NULL) { 211 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 212 xpt_done(ccb); 213 return; 214 } 215 216 mtx_assert(&sc->sim_mtx, MA_OWNED); 217 218 switch (ccb->ccb_h.func_code) { 219 case XPT_PATH_INQ: 220 mmc_path_inq(&ccb->cpi, "Deglitch Networks", sim, 221 (sc->aw_mmc_conf->dma_xferlen * AW_MMC_DMA_SEGS) / 222 MMC_SECTOR_SIZE); 223 break; 224 225 case XPT_GET_TRAN_SETTINGS: 226 { 227 struct ccb_trans_settings *cts = &ccb->cts; 228 229 if (bootverbose) 230 device_printf(sc->aw_dev, "Got XPT_GET_TRAN_SETTINGS\n"); 231 232 cts->protocol = PROTO_MMCSD; 233 cts->protocol_version = 1; 234 cts->transport = XPORT_MMCSD; 235 cts->transport_version = 1; 236 cts->xport_specific.valid = 0; 237 cts->proto_specific.mmc.host_ocr = sc->aw_host.host_ocr; 238 cts->proto_specific.mmc.host_f_min = sc->aw_host.f_min; 239 cts->proto_specific.mmc.host_f_max = sc->aw_host.f_max; 240 cts->proto_specific.mmc.host_caps = sc->aw_host.caps; 241 cts->proto_specific.mmc.host_max_data = (sc->aw_mmc_conf->dma_xferlen * 242 AW_MMC_DMA_SEGS) / MMC_SECTOR_SIZE; 243 memcpy(&cts->proto_specific.mmc.ios, &sc->aw_host.ios, sizeof(struct mmc_ios)); 244 ccb->ccb_h.status = CAM_REQ_CMP; 245 break; 246 } 247 case XPT_SET_TRAN_SETTINGS: 248 { 249 if (bootverbose) 250 device_printf(sc->aw_dev, "Got XPT_SET_TRAN_SETTINGS\n"); 251 aw_mmc_cam_settran_settings(sc, ccb); 252 ccb->ccb_h.status = CAM_REQ_CMP; 253 break; 254 } 255 case XPT_RESET_BUS: 256 if (bootverbose) 257 device_printf(sc->aw_dev, "Got XPT_RESET_BUS, ACK it...\n"); 258 ccb->ccb_h.status = CAM_REQ_CMP; 259 break; 260 case XPT_MMC_IO: 261 /* 262 * Here is the HW-dependent part of 263 * sending the command to the underlying h/w 264 * At some point in the future an interrupt comes. 265 * Then the request will be marked as completed. 266 */ 267 ccb->ccb_h.status = CAM_REQ_INPROG; 268 269 aw_mmc_cam_handle_mmcio(sim, ccb); 270 return; 271 /* NOTREACHED */ 272 break; 273 default: 274 ccb->ccb_h.status = CAM_REQ_INVALID; 275 break; 276 } 277 xpt_done(ccb); 278 return; 279 } 280 281 static void 282 aw_mmc_cam_poll(struct cam_sim *sim) 283 { 284 return; 285 } 286 287 static int 288 aw_mmc_cam_settran_settings(struct aw_mmc_softc *sc, union ccb *ccb) 289 { 290 struct mmc_ios *ios; 291 struct mmc_ios *new_ios; 292 struct ccb_trans_settings_mmc *cts; 293 294 ios = &sc->aw_host.ios; 295 296 cts = &ccb->cts.proto_specific.mmc; 297 new_ios = &cts->ios; 298 299 /* Update only requested fields */ 300 if (cts->ios_valid & MMC_CLK) { 301 ios->clock = new_ios->clock; 302 device_printf(sc->aw_dev, "Clock => %d\n", ios->clock); 303 } 304 if (cts->ios_valid & MMC_VDD) { 305 ios->vdd = new_ios->vdd; 306 device_printf(sc->aw_dev, "VDD => %d\n", ios->vdd); 307 } 308 if (cts->ios_valid & MMC_CS) { 309 ios->chip_select = new_ios->chip_select; 310 device_printf(sc->aw_dev, "CS => %d\n", ios->chip_select); 311 } 312 if (cts->ios_valid & MMC_BW) { 313 ios->bus_width = new_ios->bus_width; 314 device_printf(sc->aw_dev, "Bus width => %d\n", ios->bus_width); 315 } 316 if (cts->ios_valid & MMC_PM) { 317 ios->power_mode = new_ios->power_mode; 318 device_printf(sc->aw_dev, "Power mode => %d\n", ios->power_mode); 319 } 320 if (cts->ios_valid & MMC_BT) { 321 ios->timing = new_ios->timing; 322 device_printf(sc->aw_dev, "Timing => %d\n", ios->timing); 323 } 324 if (cts->ios_valid & MMC_BM) { 325 ios->bus_mode = new_ios->bus_mode; 326 device_printf(sc->aw_dev, "Bus mode => %d\n", ios->bus_mode); 327 } 328 329 return (aw_mmc_update_ios(sc->aw_dev, NULL)); 330 } 331 332 static int 333 aw_mmc_cam_request(struct aw_mmc_softc *sc, union ccb *ccb) 334 { 335 struct ccb_mmcio *mmcio; 336 337 mmcio = &ccb->mmcio; 338 339 AW_MMC_LOCK(sc); 340 341 #ifdef DEBUG 342 if (__predict_false(bootverbose)) { 343 device_printf(sc->aw_dev, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 344 mmcio->cmd.opcode, mmcio->cmd.arg, mmcio->cmd.flags, 345 mmcio->cmd.data != NULL ? (unsigned int) mmcio->cmd.data->len : 0, 346 mmcio->cmd.data != NULL ? mmcio->cmd.data->flags: 0); 347 } 348 #endif 349 if (mmcio->cmd.data != NULL) { 350 if (mmcio->cmd.data->len == 0 || mmcio->cmd.data->flags == 0) 351 panic("data->len = %d, data->flags = %d -- something is b0rked", 352 (int)mmcio->cmd.data->len, mmcio->cmd.data->flags); 353 } 354 if (sc->ccb != NULL) { 355 device_printf(sc->aw_dev, "Controller still has an active command\n"); 356 return (EBUSY); 357 } 358 sc->ccb = ccb; 359 /* aw_mmc_request locks again */ 360 AW_MMC_UNLOCK(sc); 361 aw_mmc_request(sc->aw_dev, NULL, NULL); 362 363 return (0); 364 } 365 #endif /* MMCCAM */ 366 367 static void 368 aw_mmc_helper_cd_handler(device_t dev, bool present) 369 { 370 struct aw_mmc_softc *sc; 371 372 sc = device_get_softc(dev); 373 AW_MMC_LOCK(sc); 374 if (present) { 375 if (sc->child == NULL) { 376 if (bootverbose) 377 device_printf(sc->aw_dev, "Card inserted\n"); 378 379 sc->child = device_add_child(sc->aw_dev, "mmc", -1); 380 AW_MMC_UNLOCK(sc); 381 if (sc->child) { 382 device_set_ivars(sc->child, sc); 383 (void)device_probe_and_attach(sc->child); 384 } 385 } else 386 AW_MMC_UNLOCK(sc); 387 } else { 388 /* Card isn't present, detach if necessary */ 389 if (sc->child != NULL) { 390 if (bootverbose) 391 device_printf(sc->aw_dev, "Card removed\n"); 392 393 AW_MMC_UNLOCK(sc); 394 device_delete_child(sc->aw_dev, sc->child); 395 sc->child = NULL; 396 } else 397 AW_MMC_UNLOCK(sc); 398 } 399 } 400 401 static int 402 aw_mmc_probe(device_t dev) 403 { 404 405 if (!ofw_bus_status_okay(dev)) 406 return (ENXIO); 407 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 408 return (ENXIO); 409 410 device_set_desc(dev, "Allwinner Integrated MMC/SD controller"); 411 412 return (BUS_PROBE_DEFAULT); 413 } 414 415 static int 416 aw_mmc_attach(device_t dev) 417 { 418 struct aw_mmc_softc *sc; 419 struct sysctl_ctx_list *ctx; 420 struct sysctl_oid_list *tree; 421 int error; 422 423 sc = device_get_softc(dev); 424 sc->aw_dev = dev; 425 426 sc->aw_mmc_conf = (struct aw_mmc_conf *)ofw_bus_search_compatible(dev, compat_data)->ocd_data; 427 428 #ifndef MMCCAM 429 sc->aw_req = NULL; 430 #endif 431 if (bus_alloc_resources(dev, aw_mmc_res_spec, sc->aw_res) != 0) { 432 device_printf(dev, "cannot allocate device resources\n"); 433 return (ENXIO); 434 } 435 if (bus_setup_intr(dev, sc->aw_res[AW_MMC_IRQRES], 436 INTR_TYPE_NET | INTR_MPSAFE, NULL, aw_mmc_intr, sc, 437 &sc->aw_intrhand)) { 438 bus_release_resources(dev, aw_mmc_res_spec, sc->aw_res); 439 device_printf(dev, "cannot setup interrupt handler\n"); 440 return (ENXIO); 441 } 442 mtx_init(&sc->aw_mtx, device_get_nameunit(sc->aw_dev), "aw_mmc", 443 MTX_DEF); 444 callout_init_mtx(&sc->aw_timeoutc, &sc->aw_mtx, 0); 445 446 /* De-assert reset */ 447 if (hwreset_get_by_ofw_name(dev, 0, "ahb", &sc->aw_rst_ahb) == 0) { 448 error = hwreset_deassert(sc->aw_rst_ahb); 449 if (error != 0) { 450 device_printf(dev, "cannot de-assert reset\n"); 451 goto fail; 452 } 453 } 454 455 /* Activate the module clock. */ 456 error = clk_get_by_ofw_name(dev, 0, "ahb", &sc->aw_clk_ahb); 457 if (error != 0) { 458 device_printf(dev, "cannot get ahb clock\n"); 459 goto fail; 460 } 461 error = clk_enable(sc->aw_clk_ahb); 462 if (error != 0) { 463 device_printf(dev, "cannot enable ahb clock\n"); 464 goto fail; 465 } 466 error = clk_get_by_ofw_name(dev, 0, "mmc", &sc->aw_clk_mmc); 467 if (error != 0) { 468 device_printf(dev, "cannot get mmc clock\n"); 469 goto fail; 470 } 471 error = clk_set_freq(sc->aw_clk_mmc, CARD_ID_FREQUENCY, 472 CLK_SET_ROUND_DOWN); 473 if (error != 0) { 474 device_printf(dev, "cannot init mmc clock\n"); 475 goto fail; 476 } 477 error = clk_enable(sc->aw_clk_mmc); 478 if (error != 0) { 479 device_printf(dev, "cannot enable mmc clock\n"); 480 goto fail; 481 } 482 483 sc->aw_timeout = 10; 484 ctx = device_get_sysctl_ctx(dev); 485 tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 486 SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "req_timeout", CTLFLAG_RW, 487 &sc->aw_timeout, 0, "Request timeout in seconds"); 488 489 /* Soft Reset controller. */ 490 if (aw_mmc_reset(sc) != 0) { 491 device_printf(dev, "cannot reset the controller\n"); 492 goto fail; 493 } 494 495 if (aw_mmc_setup_dma(sc) != 0) { 496 device_printf(sc->aw_dev, "Couldn't setup DMA!\n"); 497 goto fail; 498 } 499 500 /* Set some defaults for freq and supported mode */ 501 sc->aw_host.f_min = 400000; 502 sc->aw_host.f_max = 52000000; 503 sc->aw_host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340; 504 sc->aw_host.caps |= MMC_CAP_HSPEED | MMC_CAP_SIGNALING_330; 505 mmc_fdt_parse(dev, 0, &sc->mmc_helper, &sc->aw_host); 506 mmc_fdt_gpio_setup(dev, 0, &sc->mmc_helper, aw_mmc_helper_cd_handler); 507 508 #ifdef MMCCAM 509 sc->ccb = NULL; 510 if ((sc->devq = cam_simq_alloc(1)) == NULL) { 511 goto fail; 512 } 513 514 mtx_init(&sc->sim_mtx, "awmmcsim", NULL, MTX_DEF); 515 sc->sim = cam_sim_alloc_dev(aw_mmc_cam_action, aw_mmc_cam_poll, 516 "aw_mmc_sim", sc, dev, 517 &sc->sim_mtx, 1, 1, sc->devq); 518 519 if (sc->sim == NULL) { 520 cam_simq_free(sc->devq); 521 device_printf(dev, "cannot allocate CAM SIM\n"); 522 goto fail; 523 } 524 525 mtx_lock(&sc->sim_mtx); 526 if (xpt_bus_register(sc->sim, sc->aw_dev, 0) != 0) { 527 device_printf(dev, "cannot register SCSI pass-through bus\n"); 528 cam_sim_free(sc->sim, FALSE); 529 cam_simq_free(sc->devq); 530 mtx_unlock(&sc->sim_mtx); 531 goto fail; 532 } 533 534 mtx_unlock(&sc->sim_mtx); 535 #endif /* MMCCAM */ 536 537 return (0); 538 539 fail: 540 callout_drain(&sc->aw_timeoutc); 541 mtx_destroy(&sc->aw_mtx); 542 bus_teardown_intr(dev, sc->aw_res[AW_MMC_IRQRES], sc->aw_intrhand); 543 bus_release_resources(dev, aw_mmc_res_spec, sc->aw_res); 544 545 #ifdef MMCCAM 546 if (sc->sim != NULL) { 547 mtx_lock(&sc->sim_mtx); 548 xpt_bus_deregister(cam_sim_path(sc->sim)); 549 cam_sim_free(sc->sim, FALSE); 550 mtx_unlock(&sc->sim_mtx); 551 } 552 553 if (sc->devq != NULL) 554 cam_simq_free(sc->devq); 555 #endif 556 return (ENXIO); 557 } 558 559 static int 560 aw_mmc_detach(device_t dev) 561 { 562 563 return (EBUSY); 564 } 565 566 static void 567 aw_dma_desc_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err) 568 { 569 struct aw_mmc_softc *sc; 570 571 sc = (struct aw_mmc_softc *)arg; 572 if (err) { 573 sc->aw_dma_map_err = err; 574 return; 575 } 576 sc->aw_dma_desc_phys = segs[0].ds_addr; 577 } 578 579 static int 580 aw_mmc_setup_dma(struct aw_mmc_softc *sc) 581 { 582 int error; 583 584 /* Allocate the DMA descriptor memory. */ 585 error = bus_dma_tag_create( 586 bus_get_dma_tag(sc->aw_dev), /* parent */ 587 AW_MMC_DMA_ALIGN, 0, /* align, boundary */ 588 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 589 BUS_SPACE_MAXADDR, /* highaddr */ 590 NULL, NULL, /* filter, filterarg*/ 591 AW_MMC_DMA_DESC_SIZE, 1, /* maxsize, nsegment */ 592 AW_MMC_DMA_DESC_SIZE, /* maxsegsize */ 593 0, /* flags */ 594 NULL, NULL, /* lock, lockarg*/ 595 &sc->aw_dma_tag); 596 if (error) 597 return (error); 598 599 error = bus_dmamem_alloc(sc->aw_dma_tag, &sc->aw_dma_desc, 600 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, 601 &sc->aw_dma_map); 602 if (error) 603 return (error); 604 605 error = bus_dmamap_load(sc->aw_dma_tag, 606 sc->aw_dma_map, 607 sc->aw_dma_desc, AW_MMC_DMA_DESC_SIZE, 608 aw_dma_desc_cb, sc, 0); 609 if (error) 610 return (error); 611 if (sc->aw_dma_map_err) 612 return (sc->aw_dma_map_err); 613 614 /* Create the DMA map for data transfers. */ 615 error = bus_dma_tag_create( 616 bus_get_dma_tag(sc->aw_dev), /* parent */ 617 AW_MMC_DMA_ALIGN, 0, /* align, boundary */ 618 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 619 BUS_SPACE_MAXADDR, /* highaddr */ 620 NULL, NULL, /* filter, filterarg*/ 621 sc->aw_mmc_conf->dma_xferlen * 622 AW_MMC_DMA_SEGS, AW_MMC_DMA_SEGS, /* maxsize, nsegments */ 623 sc->aw_mmc_conf->dma_xferlen, /* maxsegsize */ 624 BUS_DMA_ALLOCNOW, /* flags */ 625 NULL, NULL, /* lock, lockarg*/ 626 &sc->aw_dma_buf_tag); 627 if (error) 628 return (error); 629 error = bus_dmamap_create(sc->aw_dma_buf_tag, 0, 630 &sc->aw_dma_buf_map); 631 if (error) 632 return (error); 633 634 return (0); 635 } 636 637 static void 638 aw_dma_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err) 639 { 640 int i; 641 struct aw_mmc_dma_desc *dma_desc; 642 struct aw_mmc_softc *sc; 643 644 sc = (struct aw_mmc_softc *)arg; 645 sc->aw_dma_map_err = err; 646 647 if (err) 648 return; 649 650 dma_desc = sc->aw_dma_desc; 651 for (i = 0; i < nsegs; i++) { 652 if (segs[i].ds_len == sc->aw_mmc_conf->dma_xferlen) 653 dma_desc[i].buf_size = 0; /* Size of 0 indicate max len */ 654 else 655 dma_desc[i].buf_size = segs[i].ds_len; 656 dma_desc[i].buf_addr = segs[i].ds_addr; 657 dma_desc[i].config = AW_MMC_DMA_CONFIG_CH | 658 AW_MMC_DMA_CONFIG_OWN | AW_MMC_DMA_CONFIG_DIC; 659 660 dma_desc[i].next = sc->aw_dma_desc_phys + 661 ((i + 1) * sizeof(struct aw_mmc_dma_desc)); 662 } 663 664 dma_desc[0].config |= AW_MMC_DMA_CONFIG_FD; 665 dma_desc[nsegs - 1].config |= AW_MMC_DMA_CONFIG_LD | 666 AW_MMC_DMA_CONFIG_ER; 667 dma_desc[nsegs - 1].config &= ~AW_MMC_DMA_CONFIG_DIC; 668 dma_desc[nsegs - 1].next = 0; 669 } 670 671 static int 672 aw_mmc_prepare_dma(struct aw_mmc_softc *sc) 673 { 674 bus_dmasync_op_t sync_op; 675 int error; 676 struct mmc_command *cmd; 677 uint32_t val; 678 679 #ifdef MMCCAM 680 cmd = &sc->ccb->mmcio.cmd; 681 #else 682 cmd = sc->aw_req->cmd; 683 #endif 684 if (cmd->data->len > (sc->aw_mmc_conf->dma_xferlen * AW_MMC_DMA_SEGS)) 685 return (EFBIG); 686 error = bus_dmamap_load(sc->aw_dma_buf_tag, sc->aw_dma_buf_map, 687 cmd->data->data, cmd->data->len, aw_dma_cb, sc, 0); 688 if (error) 689 return (error); 690 if (sc->aw_dma_map_err) 691 return (sc->aw_dma_map_err); 692 693 if (cmd->data->flags & MMC_DATA_WRITE) 694 sync_op = BUS_DMASYNC_PREWRITE; 695 else 696 sync_op = BUS_DMASYNC_PREREAD; 697 bus_dmamap_sync(sc->aw_dma_buf_tag, sc->aw_dma_buf_map, sync_op); 698 bus_dmamap_sync(sc->aw_dma_tag, sc->aw_dma_map, BUS_DMASYNC_PREWRITE); 699 700 /* Enable DMA */ 701 val = AW_MMC_READ_4(sc, AW_MMC_GCTL); 702 val &= ~AW_MMC_GCTL_FIFO_AC_MOD; 703 val |= AW_MMC_GCTL_DMA_ENB; 704 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val); 705 706 /* Reset DMA */ 707 val |= AW_MMC_GCTL_DMA_RST; 708 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val); 709 710 AW_MMC_WRITE_4(sc, AW_MMC_DMAC, AW_MMC_DMAC_IDMAC_SOFT_RST); 711 AW_MMC_WRITE_4(sc, AW_MMC_DMAC, 712 AW_MMC_DMAC_IDMAC_IDMA_ON | AW_MMC_DMAC_IDMAC_FIX_BURST); 713 714 /* Enable RX or TX DMA interrupt */ 715 val = AW_MMC_READ_4(sc, AW_MMC_IDIE); 716 if (cmd->data->flags & MMC_DATA_WRITE) 717 val |= AW_MMC_IDST_TX_INT; 718 else 719 val |= AW_MMC_IDST_RX_INT; 720 AW_MMC_WRITE_4(sc, AW_MMC_IDIE, val); 721 722 /* Set DMA descritptor list address */ 723 AW_MMC_WRITE_4(sc, AW_MMC_DLBA, sc->aw_dma_desc_phys); 724 725 /* FIFO trigger level */ 726 AW_MMC_WRITE_4(sc, AW_MMC_FWLR, AW_MMC_DMA_FTRGLEVEL); 727 728 return (0); 729 } 730 731 static int 732 aw_mmc_reset(struct aw_mmc_softc *sc) 733 { 734 uint32_t reg; 735 int timeout; 736 737 reg = AW_MMC_READ_4(sc, AW_MMC_GCTL); 738 reg |= AW_MMC_GCTL_RESET; 739 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg); 740 timeout = AW_MMC_RESET_RETRY; 741 while (--timeout > 0) { 742 if ((AW_MMC_READ_4(sc, AW_MMC_GCTL) & AW_MMC_GCTL_RESET) == 0) 743 break; 744 DELAY(100); 745 } 746 if (timeout == 0) 747 return (ETIMEDOUT); 748 749 return (0); 750 } 751 752 static int 753 aw_mmc_init(struct aw_mmc_softc *sc) 754 { 755 uint32_t reg; 756 int ret; 757 758 ret = aw_mmc_reset(sc); 759 if (ret != 0) 760 return (ret); 761 762 /* Set the timeout. */ 763 AW_MMC_WRITE_4(sc, AW_MMC_TMOR, 764 AW_MMC_TMOR_DTO_LMT_SHIFT(AW_MMC_TMOR_DTO_LMT_MASK) | 765 AW_MMC_TMOR_RTO_LMT_SHIFT(AW_MMC_TMOR_RTO_LMT_MASK)); 766 767 /* Unmask interrupts. */ 768 AW_MMC_WRITE_4(sc, AW_MMC_IMKR, 0); 769 770 /* Clear pending interrupts. */ 771 AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff); 772 773 /* Debug register, undocumented */ 774 AW_MMC_WRITE_4(sc, AW_MMC_DBGC, 0xdeb); 775 776 /* Function select register */ 777 AW_MMC_WRITE_4(sc, AW_MMC_FUNS, 0xceaa0000); 778 779 AW_MMC_WRITE_4(sc, AW_MMC_IDST, 0xffffffff); 780 781 /* Enable interrupts and disable AHB access. */ 782 reg = AW_MMC_READ_4(sc, AW_MMC_GCTL); 783 reg |= AW_MMC_GCTL_INT_ENB; 784 reg &= ~AW_MMC_GCTL_FIFO_AC_MOD; 785 reg &= ~AW_MMC_GCTL_WAIT_MEM_ACCESS; 786 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg); 787 788 return (0); 789 } 790 791 static void 792 aw_mmc_req_done(struct aw_mmc_softc *sc) 793 { 794 struct mmc_command *cmd; 795 #ifdef MMCCAM 796 union ccb *ccb; 797 #else 798 struct mmc_request *req; 799 #endif 800 uint32_t val, mask; 801 int retry; 802 803 #ifdef MMCCAM 804 ccb = sc->ccb; 805 cmd = &ccb->mmcio.cmd; 806 #else 807 cmd = sc->aw_req->cmd; 808 #endif 809 #ifdef DEBUG 810 if (bootverbose) { 811 device_printf(sc->aw_dev, "%s: cmd %d err %d\n", __func__, cmd->opcode, cmd->error); 812 } 813 #endif 814 if (cmd->error != MMC_ERR_NONE) { 815 /* Reset the FIFO and DMA engines. */ 816 mask = AW_MMC_GCTL_FIFO_RST | AW_MMC_GCTL_DMA_RST; 817 val = AW_MMC_READ_4(sc, AW_MMC_GCTL); 818 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val | mask); 819 820 retry = AW_MMC_RESET_RETRY; 821 while (--retry > 0) { 822 if ((AW_MMC_READ_4(sc, AW_MMC_GCTL) & 823 AW_MMC_GCTL_RESET) == 0) 824 break; 825 DELAY(100); 826 } 827 if (retry == 0) 828 device_printf(sc->aw_dev, 829 "timeout resetting DMA/FIFO\n"); 830 aw_mmc_update_clock(sc, 1); 831 } 832 833 callout_stop(&sc->aw_timeoutc); 834 sc->aw_intr = 0; 835 sc->aw_resid = 0; 836 sc->aw_dma_map_err = 0; 837 sc->aw_intr_wait = 0; 838 #ifdef MMCCAM 839 sc->ccb = NULL; 840 ccb->ccb_h.status = 841 (ccb->mmcio.cmd.error == 0 ? CAM_REQ_CMP : CAM_REQ_CMP_ERR); 842 xpt_done(ccb); 843 #else 844 req = sc->aw_req; 845 sc->aw_req = NULL; 846 req->done(req); 847 #endif 848 } 849 850 static void 851 aw_mmc_req_ok(struct aw_mmc_softc *sc) 852 { 853 int timeout; 854 struct mmc_command *cmd; 855 uint32_t status; 856 857 timeout = 1000; 858 while (--timeout > 0) { 859 status = AW_MMC_READ_4(sc, AW_MMC_STAR); 860 if ((status & AW_MMC_STAR_CARD_BUSY) == 0) 861 break; 862 DELAY(1000); 863 } 864 #ifdef MMCCAM 865 cmd = &sc->ccb->mmcio.cmd; 866 #else 867 cmd = sc->aw_req->cmd; 868 #endif 869 if (timeout == 0) { 870 cmd->error = MMC_ERR_FAILED; 871 aw_mmc_req_done(sc); 872 return; 873 } 874 if (cmd->flags & MMC_RSP_PRESENT) { 875 if (cmd->flags & MMC_RSP_136) { 876 cmd->resp[0] = AW_MMC_READ_4(sc, AW_MMC_RESP3); 877 cmd->resp[1] = AW_MMC_READ_4(sc, AW_MMC_RESP2); 878 cmd->resp[2] = AW_MMC_READ_4(sc, AW_MMC_RESP1); 879 cmd->resp[3] = AW_MMC_READ_4(sc, AW_MMC_RESP0); 880 } else 881 cmd->resp[0] = AW_MMC_READ_4(sc, AW_MMC_RESP0); 882 } 883 /* All data has been transferred ? */ 884 if (cmd->data != NULL && (sc->aw_resid << 2) < cmd->data->len) 885 cmd->error = MMC_ERR_FAILED; 886 aw_mmc_req_done(sc); 887 } 888 889 890 static inline void 891 set_mmc_error(struct aw_mmc_softc *sc, int error_code) 892 { 893 #ifdef MMCCAM 894 sc->ccb->mmcio.cmd.error = error_code; 895 #else 896 sc->aw_req->cmd->error = error_code; 897 #endif 898 } 899 900 static void 901 aw_mmc_timeout(void *arg) 902 { 903 struct aw_mmc_softc *sc; 904 905 sc = (struct aw_mmc_softc *)arg; 906 #ifdef MMCCAM 907 if (sc->ccb != NULL) { 908 #else 909 if (sc->aw_req != NULL) { 910 #endif 911 device_printf(sc->aw_dev, "controller timeout\n"); 912 set_mmc_error(sc, MMC_ERR_TIMEOUT); 913 aw_mmc_req_done(sc); 914 } else 915 device_printf(sc->aw_dev, 916 "Spurious timeout - no active request\n"); 917 } 918 919 static void 920 aw_mmc_print_error(uint32_t err) 921 { 922 if(err & AW_MMC_INT_RESP_ERR) 923 printf("AW_MMC_INT_RESP_ERR "); 924 if (err & AW_MMC_INT_RESP_CRC_ERR) 925 printf("AW_MMC_INT_RESP_CRC_ERR "); 926 if (err & AW_MMC_INT_DATA_CRC_ERR) 927 printf("AW_MMC_INT_DATA_CRC_ERR "); 928 if (err & AW_MMC_INT_RESP_TIMEOUT) 929 printf("AW_MMC_INT_RESP_TIMEOUT "); 930 if (err & AW_MMC_INT_FIFO_RUN_ERR) 931 printf("AW_MMC_INT_FIFO_RUN_ERR "); 932 if (err & AW_MMC_INT_CMD_BUSY) 933 printf("AW_MMC_INT_CMD_BUSY "); 934 if (err & AW_MMC_INT_DATA_START_ERR) 935 printf("AW_MMC_INT_DATA_START_ERR "); 936 if (err & AW_MMC_INT_DATA_END_BIT_ERR) 937 printf("AW_MMC_INT_DATA_END_BIT_ERR"); 938 printf("\n"); 939 } 940 941 static void 942 aw_mmc_intr(void *arg) 943 { 944 bus_dmasync_op_t sync_op; 945 struct aw_mmc_softc *sc; 946 struct mmc_data *data; 947 uint32_t idst, imask, rint; 948 949 sc = (struct aw_mmc_softc *)arg; 950 AW_MMC_LOCK(sc); 951 rint = AW_MMC_READ_4(sc, AW_MMC_RISR); 952 idst = AW_MMC_READ_4(sc, AW_MMC_IDST); 953 imask = AW_MMC_READ_4(sc, AW_MMC_IMKR); 954 if (idst == 0 && imask == 0 && rint == 0) { 955 AW_MMC_UNLOCK(sc); 956 return; 957 } 958 #ifdef DEBUG 959 device_printf(sc->aw_dev, "idst: %#x, imask: %#x, rint: %#x\n", 960 idst, imask, rint); 961 #endif 962 #ifdef MMCCAM 963 if (sc->ccb == NULL) { 964 #else 965 if (sc->aw_req == NULL) { 966 #endif 967 device_printf(sc->aw_dev, 968 "Spurious interrupt - no active request, rint: 0x%08X\n", 969 rint); 970 aw_mmc_print_error(rint); 971 goto end; 972 } 973 if (rint & AW_MMC_INT_ERR_BIT) { 974 if (bootverbose) 975 device_printf(sc->aw_dev, "error rint: 0x%08X\n", rint); 976 aw_mmc_print_error(rint); 977 if (rint & AW_MMC_INT_RESP_TIMEOUT) 978 set_mmc_error(sc, MMC_ERR_TIMEOUT); 979 else 980 set_mmc_error(sc, MMC_ERR_FAILED); 981 aw_mmc_req_done(sc); 982 goto end; 983 } 984 if (idst & AW_MMC_IDST_ERROR) { 985 device_printf(sc->aw_dev, "error idst: 0x%08x\n", idst); 986 set_mmc_error(sc, MMC_ERR_FAILED); 987 aw_mmc_req_done(sc); 988 goto end; 989 } 990 991 sc->aw_intr |= rint; 992 #ifdef MMCCAM 993 data = sc->ccb->mmcio.cmd.data; 994 #else 995 data = sc->aw_req->cmd->data; 996 #endif 997 if (data != NULL && (idst & AW_MMC_IDST_COMPLETE) != 0) { 998 if (data->flags & MMC_DATA_WRITE) 999 sync_op = BUS_DMASYNC_POSTWRITE; 1000 else 1001 sync_op = BUS_DMASYNC_POSTREAD; 1002 bus_dmamap_sync(sc->aw_dma_buf_tag, sc->aw_dma_buf_map, 1003 sync_op); 1004 bus_dmamap_sync(sc->aw_dma_tag, sc->aw_dma_map, 1005 BUS_DMASYNC_POSTWRITE); 1006 bus_dmamap_unload(sc->aw_dma_buf_tag, sc->aw_dma_buf_map); 1007 sc->aw_resid = data->len >> 2; 1008 } 1009 if ((sc->aw_intr & sc->aw_intr_wait) == sc->aw_intr_wait) 1010 aw_mmc_req_ok(sc); 1011 1012 end: 1013 AW_MMC_WRITE_4(sc, AW_MMC_IDST, idst); 1014 AW_MMC_WRITE_4(sc, AW_MMC_RISR, rint); 1015 AW_MMC_UNLOCK(sc); 1016 } 1017 1018 static int 1019 aw_mmc_request(device_t bus, device_t child, struct mmc_request *req) 1020 { 1021 int blksz; 1022 struct aw_mmc_softc *sc; 1023 struct mmc_command *cmd; 1024 uint32_t cmdreg, imask; 1025 int err; 1026 1027 sc = device_get_softc(bus); 1028 1029 AW_MMC_LOCK(sc); 1030 #ifdef MMCCAM 1031 KASSERT(req == NULL, ("req should be NULL in MMCCAM case!")); 1032 /* 1033 * For MMCCAM, sc->ccb has been NULL-checked and populated 1034 * by aw_mmc_cam_request() already. 1035 */ 1036 cmd = &sc->ccb->mmcio.cmd; 1037 #else 1038 if (sc->aw_req) { 1039 AW_MMC_UNLOCK(sc); 1040 return (EBUSY); 1041 } 1042 sc->aw_req = req; 1043 cmd = req->cmd; 1044 1045 #ifdef DEBUG 1046 if (bootverbose) 1047 device_printf(sc->aw_dev, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 1048 cmd->opcode, cmd->arg, cmd->flags, 1049 cmd->data != NULL ? (unsigned int)cmd->data->len : 0, 1050 cmd->data != NULL ? cmd->data->flags: 0); 1051 #endif 1052 #endif 1053 cmdreg = AW_MMC_CMDR_LOAD; 1054 imask = AW_MMC_INT_ERR_BIT; 1055 sc->aw_intr_wait = 0; 1056 sc->aw_intr = 0; 1057 sc->aw_resid = 0; 1058 cmd->error = MMC_ERR_NONE; 1059 1060 if (cmd->opcode == MMC_GO_IDLE_STATE) 1061 cmdreg |= AW_MMC_CMDR_SEND_INIT_SEQ; 1062 1063 if (cmd->flags & MMC_RSP_PRESENT) 1064 cmdreg |= AW_MMC_CMDR_RESP_RCV; 1065 if (cmd->flags & MMC_RSP_136) 1066 cmdreg |= AW_MMC_CMDR_LONG_RESP; 1067 if (cmd->flags & MMC_RSP_CRC) 1068 cmdreg |= AW_MMC_CMDR_CHK_RESP_CRC; 1069 1070 if (cmd->data) { 1071 cmdreg |= AW_MMC_CMDR_DATA_TRANS | AW_MMC_CMDR_WAIT_PRE_OVER; 1072 1073 if (cmd->data->flags & MMC_DATA_MULTI) { 1074 cmdreg |= AW_MMC_CMDR_STOP_CMD_FLAG; 1075 imask |= AW_MMC_INT_AUTO_STOP_DONE; 1076 sc->aw_intr_wait |= AW_MMC_INT_AUTO_STOP_DONE; 1077 } else { 1078 sc->aw_intr_wait |= AW_MMC_INT_DATA_OVER; 1079 imask |= AW_MMC_INT_DATA_OVER; 1080 } 1081 if (cmd->data->flags & MMC_DATA_WRITE) 1082 cmdreg |= AW_MMC_CMDR_DIR_WRITE; 1083 #ifdef MMCCAM 1084 if (cmd->data->flags & MMC_DATA_BLOCK_SIZE) { 1085 AW_MMC_WRITE_4(sc, AW_MMC_BKSR, cmd->data->block_size); 1086 AW_MMC_WRITE_4(sc, AW_MMC_BYCR, cmd->data->len); 1087 } else 1088 #endif 1089 { 1090 blksz = min(cmd->data->len, MMC_SECTOR_SIZE); 1091 AW_MMC_WRITE_4(sc, AW_MMC_BKSR, blksz); 1092 AW_MMC_WRITE_4(sc, AW_MMC_BYCR, cmd->data->len); 1093 } 1094 } else { 1095 imask |= AW_MMC_INT_CMD_DONE; 1096 } 1097 1098 /* Enable the interrupts we are interested in */ 1099 AW_MMC_WRITE_4(sc, AW_MMC_IMKR, imask); 1100 AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff); 1101 1102 /* Enable auto stop if needed */ 1103 AW_MMC_WRITE_4(sc, AW_MMC_A12A, 1104 cmdreg & AW_MMC_CMDR_STOP_CMD_FLAG ? 0 : 0xffff); 1105 1106 /* Write the command argument */ 1107 AW_MMC_WRITE_4(sc, AW_MMC_CAGR, cmd->arg); 1108 1109 /* 1110 * If we don't have data start the request 1111 * if we do prepare the dma request and start the request 1112 */ 1113 if (cmd->data == NULL) { 1114 AW_MMC_WRITE_4(sc, AW_MMC_CMDR, cmdreg | cmd->opcode); 1115 } else { 1116 err = aw_mmc_prepare_dma(sc); 1117 if (err != 0) 1118 device_printf(sc->aw_dev, "prepare_dma failed: %d\n", err); 1119 1120 AW_MMC_WRITE_4(sc, AW_MMC_CMDR, cmdreg | cmd->opcode); 1121 } 1122 1123 callout_reset(&sc->aw_timeoutc, sc->aw_timeout * hz, 1124 aw_mmc_timeout, sc); 1125 AW_MMC_UNLOCK(sc); 1126 1127 return (0); 1128 } 1129 1130 static int 1131 aw_mmc_read_ivar(device_t bus, device_t child, int which, 1132 uintptr_t *result) 1133 { 1134 struct aw_mmc_softc *sc; 1135 1136 sc = device_get_softc(bus); 1137 switch (which) { 1138 default: 1139 return (EINVAL); 1140 case MMCBR_IVAR_BUS_MODE: 1141 *(int *)result = sc->aw_host.ios.bus_mode; 1142 break; 1143 case MMCBR_IVAR_BUS_WIDTH: 1144 *(int *)result = sc->aw_host.ios.bus_width; 1145 break; 1146 case MMCBR_IVAR_CHIP_SELECT: 1147 *(int *)result = sc->aw_host.ios.chip_select; 1148 break; 1149 case MMCBR_IVAR_CLOCK: 1150 *(int *)result = sc->aw_host.ios.clock; 1151 break; 1152 case MMCBR_IVAR_F_MIN: 1153 *(int *)result = sc->aw_host.f_min; 1154 break; 1155 case MMCBR_IVAR_F_MAX: 1156 *(int *)result = sc->aw_host.f_max; 1157 break; 1158 case MMCBR_IVAR_HOST_OCR: 1159 *(int *)result = sc->aw_host.host_ocr; 1160 break; 1161 case MMCBR_IVAR_MODE: 1162 *(int *)result = sc->aw_host.mode; 1163 break; 1164 case MMCBR_IVAR_OCR: 1165 *(int *)result = sc->aw_host.ocr; 1166 break; 1167 case MMCBR_IVAR_POWER_MODE: 1168 *(int *)result = sc->aw_host.ios.power_mode; 1169 break; 1170 case MMCBR_IVAR_VDD: 1171 *(int *)result = sc->aw_host.ios.vdd; 1172 break; 1173 case MMCBR_IVAR_VCCQ: 1174 *(int *)result = sc->aw_host.ios.vccq; 1175 break; 1176 case MMCBR_IVAR_CAPS: 1177 *(int *)result = sc->aw_host.caps; 1178 break; 1179 case MMCBR_IVAR_TIMING: 1180 *(int *)result = sc->aw_host.ios.timing; 1181 break; 1182 case MMCBR_IVAR_MAX_DATA: 1183 *(int *)result = (sc->aw_mmc_conf->dma_xferlen * 1184 AW_MMC_DMA_SEGS) / MMC_SECTOR_SIZE; 1185 break; 1186 case MMCBR_IVAR_RETUNE_REQ: 1187 *(int *)result = retune_req_none; 1188 break; 1189 } 1190 1191 return (0); 1192 } 1193 1194 static int 1195 aw_mmc_write_ivar(device_t bus, device_t child, int which, 1196 uintptr_t value) 1197 { 1198 struct aw_mmc_softc *sc; 1199 1200 sc = device_get_softc(bus); 1201 switch (which) { 1202 default: 1203 return (EINVAL); 1204 case MMCBR_IVAR_BUS_MODE: 1205 sc->aw_host.ios.bus_mode = value; 1206 break; 1207 case MMCBR_IVAR_BUS_WIDTH: 1208 sc->aw_host.ios.bus_width = value; 1209 break; 1210 case MMCBR_IVAR_CHIP_SELECT: 1211 sc->aw_host.ios.chip_select = value; 1212 break; 1213 case MMCBR_IVAR_CLOCK: 1214 sc->aw_host.ios.clock = value; 1215 break; 1216 case MMCBR_IVAR_MODE: 1217 sc->aw_host.mode = value; 1218 break; 1219 case MMCBR_IVAR_OCR: 1220 sc->aw_host.ocr = value; 1221 break; 1222 case MMCBR_IVAR_POWER_MODE: 1223 sc->aw_host.ios.power_mode = value; 1224 break; 1225 case MMCBR_IVAR_VDD: 1226 sc->aw_host.ios.vdd = value; 1227 break; 1228 case MMCBR_IVAR_VCCQ: 1229 sc->aw_host.ios.vccq = value; 1230 break; 1231 case MMCBR_IVAR_TIMING: 1232 sc->aw_host.ios.timing = value; 1233 break; 1234 /* These are read-only */ 1235 case MMCBR_IVAR_CAPS: 1236 case MMCBR_IVAR_HOST_OCR: 1237 case MMCBR_IVAR_F_MIN: 1238 case MMCBR_IVAR_F_MAX: 1239 case MMCBR_IVAR_MAX_DATA: 1240 return (EINVAL); 1241 } 1242 1243 return (0); 1244 } 1245 1246 static int 1247 aw_mmc_update_clock(struct aw_mmc_softc *sc, uint32_t clkon) 1248 { 1249 uint32_t reg; 1250 int retry; 1251 1252 reg = AW_MMC_READ_4(sc, AW_MMC_CKCR); 1253 reg &= ~(AW_MMC_CKCR_ENB | AW_MMC_CKCR_LOW_POWER | 1254 AW_MMC_CKCR_MASK_DATA0); 1255 1256 if (clkon) 1257 reg |= AW_MMC_CKCR_ENB; 1258 if (sc->aw_mmc_conf->mask_data0) 1259 reg |= AW_MMC_CKCR_MASK_DATA0; 1260 1261 AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg); 1262 1263 reg = AW_MMC_CMDR_LOAD | AW_MMC_CMDR_PRG_CLK | 1264 AW_MMC_CMDR_WAIT_PRE_OVER; 1265 AW_MMC_WRITE_4(sc, AW_MMC_CMDR, reg); 1266 retry = 0xfffff; 1267 1268 while (reg & AW_MMC_CMDR_LOAD && --retry > 0) { 1269 reg = AW_MMC_READ_4(sc, AW_MMC_CMDR); 1270 DELAY(10); 1271 } 1272 AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff); 1273 1274 if (reg & AW_MMC_CMDR_LOAD) { 1275 device_printf(sc->aw_dev, "timeout updating clock\n"); 1276 return (ETIMEDOUT); 1277 } 1278 1279 if (sc->aw_mmc_conf->mask_data0) { 1280 reg = AW_MMC_READ_4(sc, AW_MMC_CKCR); 1281 reg &= ~AW_MMC_CKCR_MASK_DATA0; 1282 AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg); 1283 } 1284 1285 return (0); 1286 } 1287 1288 static int 1289 aw_mmc_switch_vccq(device_t bus, device_t child) 1290 { 1291 struct aw_mmc_softc *sc; 1292 int uvolt, err; 1293 1294 sc = device_get_softc(bus); 1295 1296 if (sc->mmc_helper.vqmmc_supply == NULL) 1297 return EOPNOTSUPP; 1298 1299 switch (sc->aw_host.ios.vccq) { 1300 case vccq_180: 1301 uvolt = 1800000; 1302 break; 1303 case vccq_330: 1304 uvolt = 3300000; 1305 break; 1306 default: 1307 return EINVAL; 1308 } 1309 1310 err = regulator_set_voltage(sc->mmc_helper.vqmmc_supply, uvolt, uvolt); 1311 if (err != 0) { 1312 device_printf(sc->aw_dev, 1313 "Cannot set vqmmc to %d<->%d\n", 1314 uvolt, 1315 uvolt); 1316 return (err); 1317 } 1318 1319 return (0); 1320 } 1321 1322 static int 1323 aw_mmc_update_ios(device_t bus, device_t child) 1324 { 1325 int error; 1326 struct aw_mmc_softc *sc; 1327 struct mmc_ios *ios; 1328 unsigned int clock; 1329 uint32_t reg, div = 1; 1330 1331 sc = device_get_softc(bus); 1332 1333 ios = &sc->aw_host.ios; 1334 1335 /* Set the bus width. */ 1336 switch (ios->bus_width) { 1337 case bus_width_1: 1338 AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR1); 1339 break; 1340 case bus_width_4: 1341 AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR4); 1342 break; 1343 case bus_width_8: 1344 AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR8); 1345 break; 1346 } 1347 1348 switch (ios->power_mode) { 1349 case power_on: 1350 break; 1351 case power_off: 1352 if (bootverbose) 1353 device_printf(sc->aw_dev, "Powering down sd/mmc\n"); 1354 1355 if (sc->mmc_helper.vmmc_supply) 1356 regulator_disable(sc->mmc_helper.vmmc_supply); 1357 if (sc->mmc_helper.vqmmc_supply) 1358 regulator_disable(sc->mmc_helper.vqmmc_supply); 1359 1360 aw_mmc_reset(sc); 1361 break; 1362 case power_up: 1363 if (bootverbose) 1364 device_printf(sc->aw_dev, "Powering up sd/mmc\n"); 1365 1366 if (sc->mmc_helper.vmmc_supply) 1367 regulator_enable(sc->mmc_helper.vmmc_supply); 1368 if (sc->mmc_helper.vqmmc_supply) 1369 regulator_enable(sc->mmc_helper.vqmmc_supply); 1370 aw_mmc_init(sc); 1371 break; 1372 }; 1373 1374 /* Enable ddr mode if needed */ 1375 reg = AW_MMC_READ_4(sc, AW_MMC_GCTL); 1376 if (ios->timing == bus_timing_uhs_ddr50 || 1377 ios->timing == bus_timing_mmc_ddr52) 1378 reg |= AW_MMC_GCTL_DDR_MOD_SEL; 1379 else 1380 reg &= ~AW_MMC_GCTL_DDR_MOD_SEL; 1381 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg); 1382 1383 if (ios->clock && ios->clock != sc->aw_clock) { 1384 sc->aw_clock = clock = ios->clock; 1385 1386 /* Disable clock */ 1387 error = aw_mmc_update_clock(sc, 0); 1388 if (error != 0) 1389 return (error); 1390 1391 if (ios->timing == bus_timing_mmc_ddr52 && 1392 (sc->aw_mmc_conf->new_timing || 1393 ios->bus_width == bus_width_8)) { 1394 div = 2; 1395 clock <<= 1; 1396 } 1397 1398 /* Reset the divider. */ 1399 reg = AW_MMC_READ_4(sc, AW_MMC_CKCR); 1400 reg &= ~AW_MMC_CKCR_DIV; 1401 reg |= div - 1; 1402 AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg); 1403 1404 /* New timing mode if needed */ 1405 if (sc->aw_mmc_conf->new_timing) { 1406 reg = AW_MMC_READ_4(sc, AW_MMC_NTSR); 1407 reg |= AW_MMC_NTSR_MODE_SELECT; 1408 AW_MMC_WRITE_4(sc, AW_MMC_NTSR, reg); 1409 } 1410 1411 /* Set the MMC clock. */ 1412 error = clk_disable(sc->aw_clk_mmc); 1413 if (error != 0 && bootverbose) 1414 device_printf(sc->aw_dev, 1415 "failed to disable mmc clock: %d\n", error); 1416 error = clk_set_freq(sc->aw_clk_mmc, clock, 1417 CLK_SET_ROUND_DOWN); 1418 if (error != 0) { 1419 device_printf(sc->aw_dev, 1420 "failed to set frequency to %u Hz: %d\n", 1421 clock, error); 1422 return (error); 1423 } 1424 error = clk_enable(sc->aw_clk_mmc); 1425 if (error != 0 && bootverbose) 1426 device_printf(sc->aw_dev, 1427 "failed to re-enable mmc clock: %d\n", error); 1428 1429 if (sc->aw_mmc_conf->can_calibrate) 1430 AW_MMC_WRITE_4(sc, AW_MMC_SAMP_DL, AW_MMC_SAMP_DL_SW_EN); 1431 1432 /* Enable clock. */ 1433 error = aw_mmc_update_clock(sc, 1); 1434 if (error != 0) 1435 return (error); 1436 } 1437 1438 1439 return (0); 1440 } 1441 1442 static int 1443 aw_mmc_get_ro(device_t bus, device_t child) 1444 { 1445 struct aw_mmc_softc *sc; 1446 1447 sc = device_get_softc(bus); 1448 1449 return (mmc_fdt_gpio_get_readonly(&sc->mmc_helper)); 1450 } 1451 1452 static int 1453 aw_mmc_acquire_host(device_t bus, device_t child) 1454 { 1455 struct aw_mmc_softc *sc; 1456 int error; 1457 1458 sc = device_get_softc(bus); 1459 AW_MMC_LOCK(sc); 1460 while (sc->aw_bus_busy) { 1461 error = msleep(sc, &sc->aw_mtx, PCATCH, "mmchw", 0); 1462 if (error != 0) { 1463 AW_MMC_UNLOCK(sc); 1464 return (error); 1465 } 1466 } 1467 sc->aw_bus_busy++; 1468 AW_MMC_UNLOCK(sc); 1469 1470 return (0); 1471 } 1472 1473 static int 1474 aw_mmc_release_host(device_t bus, device_t child) 1475 { 1476 struct aw_mmc_softc *sc; 1477 1478 sc = device_get_softc(bus); 1479 AW_MMC_LOCK(sc); 1480 sc->aw_bus_busy--; 1481 wakeup(sc); 1482 AW_MMC_UNLOCK(sc); 1483 1484 return (0); 1485 } 1486 1487 static device_method_t aw_mmc_methods[] = { 1488 /* Device interface */ 1489 DEVMETHOD(device_probe, aw_mmc_probe), 1490 DEVMETHOD(device_attach, aw_mmc_attach), 1491 DEVMETHOD(device_detach, aw_mmc_detach), 1492 1493 /* Bus interface */ 1494 DEVMETHOD(bus_read_ivar, aw_mmc_read_ivar), 1495 DEVMETHOD(bus_write_ivar, aw_mmc_write_ivar), 1496 DEVMETHOD(bus_add_child, bus_generic_add_child), 1497 1498 /* MMC bridge interface */ 1499 DEVMETHOD(mmcbr_update_ios, aw_mmc_update_ios), 1500 DEVMETHOD(mmcbr_request, aw_mmc_request), 1501 DEVMETHOD(mmcbr_get_ro, aw_mmc_get_ro), 1502 DEVMETHOD(mmcbr_switch_vccq, aw_mmc_switch_vccq), 1503 DEVMETHOD(mmcbr_acquire_host, aw_mmc_acquire_host), 1504 DEVMETHOD(mmcbr_release_host, aw_mmc_release_host), 1505 1506 DEVMETHOD_END 1507 }; 1508 1509 static devclass_t aw_mmc_devclass; 1510 1511 static driver_t aw_mmc_driver = { 1512 "aw_mmc", 1513 aw_mmc_methods, 1514 sizeof(struct aw_mmc_softc), 1515 }; 1516 1517 DRIVER_MODULE(aw_mmc, simplebus, aw_mmc_driver, aw_mmc_devclass, NULL, 1518 NULL); 1519 #ifndef MMCCAM 1520 MMC_DECLARE_BRIDGE(aw_mmc); 1521 #endif 1522