1b5be541fSEmmanuel Vadot /*- 2b091392eSEmmanuel Vadot * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3b091392eSEmmanuel Vadot * 4b091392eSEmmanuel Vadot * Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org> 5b5be541fSEmmanuel Vadot * Copyright (c) 2013 Alexander Fedorov 6b5be541fSEmmanuel Vadot * All rights reserved. 7b5be541fSEmmanuel Vadot * 8b5be541fSEmmanuel Vadot * Redistribution and use in source and binary forms, with or without 9b5be541fSEmmanuel Vadot * modification, are permitted provided that the following conditions 10b5be541fSEmmanuel Vadot * are met: 11b5be541fSEmmanuel Vadot * 1. Redistributions of source code must retain the above copyright 12b5be541fSEmmanuel Vadot * notice, this list of conditions and the following disclaimer. 13b5be541fSEmmanuel Vadot * 2. Redistributions in binary form must reproduce the above copyright 14b5be541fSEmmanuel Vadot * notice, this list of conditions and the following disclaimer in the 15b5be541fSEmmanuel Vadot * documentation and/or other materials provided with the distribution. 16b5be541fSEmmanuel Vadot * 17b5be541fSEmmanuel Vadot * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18b5be541fSEmmanuel Vadot * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19b5be541fSEmmanuel Vadot * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20b5be541fSEmmanuel Vadot * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21b5be541fSEmmanuel Vadot * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22b5be541fSEmmanuel Vadot * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23b5be541fSEmmanuel Vadot * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24b5be541fSEmmanuel Vadot * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25b5be541fSEmmanuel Vadot * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26b5be541fSEmmanuel Vadot * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27b5be541fSEmmanuel Vadot * SUCH DAMAGE. 28b5be541fSEmmanuel Vadot */ 29b5be541fSEmmanuel Vadot 30b5be541fSEmmanuel Vadot #include <sys/cdefs.h> 31b5be541fSEmmanuel Vadot __FBSDID("$FreeBSD$"); 32b5be541fSEmmanuel Vadot 33b5be541fSEmmanuel Vadot #include <sys/param.h> 34b5be541fSEmmanuel Vadot #include <sys/systm.h> 35b5be541fSEmmanuel Vadot #include <sys/bus.h> 36b5be541fSEmmanuel Vadot #include <sys/kernel.h> 37b5be541fSEmmanuel Vadot #include <sys/lock.h> 38b5be541fSEmmanuel Vadot #include <sys/malloc.h> 39b5be541fSEmmanuel Vadot #include <sys/module.h> 40b5be541fSEmmanuel Vadot #include <sys/mutex.h> 41b5be541fSEmmanuel Vadot #include <sys/resource.h> 42b5be541fSEmmanuel Vadot #include <sys/rman.h> 43b5be541fSEmmanuel Vadot #include <sys/sysctl.h> 44b5be541fSEmmanuel Vadot 45b5be541fSEmmanuel Vadot #include <machine/bus.h> 46b5be541fSEmmanuel Vadot 47b5be541fSEmmanuel Vadot #include <dev/ofw/ofw_bus.h> 48b5be541fSEmmanuel Vadot #include <dev/ofw/ofw_bus_subr.h> 49b5be541fSEmmanuel Vadot 50b5be541fSEmmanuel Vadot #include <dev/mmc/bridge.h> 51b5be541fSEmmanuel Vadot #include <dev/mmc/mmcbrvar.h> 52b5be541fSEmmanuel Vadot 53b5be541fSEmmanuel Vadot #include <arm/allwinner/aw_mmc.h> 54b5be541fSEmmanuel Vadot #include <dev/extres/clk/clk.h> 55b5be541fSEmmanuel Vadot #include <dev/extres/hwreset/hwreset.h> 56ce0618beSEmmanuel Vadot #include <dev/extres/regulator/regulator.h> 57b5be541fSEmmanuel Vadot 585e03278fSIlya Bakulin #include "opt_mmccam.h" 595e03278fSIlya Bakulin 605e03278fSIlya Bakulin #ifdef MMCCAM 615e03278fSIlya Bakulin #include <cam/cam.h> 625e03278fSIlya Bakulin #include <cam/cam_ccb.h> 635e03278fSIlya Bakulin #include <cam/cam_debug.h> 645e03278fSIlya Bakulin #include <cam/cam_sim.h> 655e03278fSIlya Bakulin #include <cam/cam_xpt_sim.h> 665e03278fSIlya Bakulin #endif 675e03278fSIlya Bakulin 68b5be541fSEmmanuel Vadot #define AW_MMC_MEMRES 0 69b5be541fSEmmanuel Vadot #define AW_MMC_IRQRES 1 70b5be541fSEmmanuel Vadot #define AW_MMC_RESSZ 2 71c39ea909SEmmanuel Vadot #define AW_MMC_DMA_SEGS (PAGE_SIZE / sizeof(struct aw_mmc_dma_desc)) 72c39ea909SEmmanuel Vadot #define AW_MMC_DMA_DESC_SIZE (sizeof(struct aw_mmc_dma_desc) * AW_MMC_DMA_SEGS) 73b5be541fSEmmanuel Vadot #define AW_MMC_DMA_FTRGLEVEL 0x20070008 74c39ea909SEmmanuel Vadot 75b5be541fSEmmanuel Vadot #define AW_MMC_RESET_RETRY 1000 76b5be541fSEmmanuel Vadot 77b5be541fSEmmanuel Vadot #define CARD_ID_FREQUENCY 400000 78b5be541fSEmmanuel Vadot 79ce0618beSEmmanuel Vadot struct aw_mmc_conf { 80ce0618beSEmmanuel Vadot uint32_t dma_xferlen; 81ce0618beSEmmanuel Vadot bool mask_data0; 82ce0618beSEmmanuel Vadot bool can_calibrate; 83ce0618beSEmmanuel Vadot bool new_timing; 84ce0618beSEmmanuel Vadot }; 85ce0618beSEmmanuel Vadot 86ce0618beSEmmanuel Vadot static const struct aw_mmc_conf a10_mmc_conf = { 87ce0618beSEmmanuel Vadot .dma_xferlen = 0x2000, 88ce0618beSEmmanuel Vadot }; 89ce0618beSEmmanuel Vadot 90ce0618beSEmmanuel Vadot static const struct aw_mmc_conf a13_mmc_conf = { 91ce0618beSEmmanuel Vadot .dma_xferlen = 0x10000, 92ce0618beSEmmanuel Vadot }; 93ce0618beSEmmanuel Vadot 94ce0618beSEmmanuel Vadot static const struct aw_mmc_conf a64_mmc_conf = { 95ce0618beSEmmanuel Vadot .dma_xferlen = 0x10000, 96ce0618beSEmmanuel Vadot .mask_data0 = true, 97ce0618beSEmmanuel Vadot .can_calibrate = true, 98ce0618beSEmmanuel Vadot .new_timing = true, 99ce0618beSEmmanuel Vadot }; 100ce0618beSEmmanuel Vadot 101ce0618beSEmmanuel Vadot static const struct aw_mmc_conf a64_emmc_conf = { 102ce0618beSEmmanuel Vadot .dma_xferlen = 0x2000, 103ce0618beSEmmanuel Vadot .can_calibrate = true, 104ce0618beSEmmanuel Vadot }; 105ce0618beSEmmanuel Vadot 106b5be541fSEmmanuel Vadot static struct ofw_compat_data compat_data[] = { 107ce0618beSEmmanuel Vadot {"allwinner,sun4i-a10-mmc", (uintptr_t)&a10_mmc_conf}, 108ce0618beSEmmanuel Vadot {"allwinner,sun5i-a13-mmc", (uintptr_t)&a13_mmc_conf}, 109ce0618beSEmmanuel Vadot {"allwinner,sun7i-a20-mmc", (uintptr_t)&a13_mmc_conf}, 110ce0618beSEmmanuel Vadot {"allwinner,sun50i-a64-mmc", (uintptr_t)&a64_mmc_conf}, 111ce0618beSEmmanuel Vadot {"allwinner,sun50i-a64-emmc", (uintptr_t)&a64_emmc_conf}, 112b5be541fSEmmanuel Vadot {NULL, 0} 113b5be541fSEmmanuel Vadot }; 114b5be541fSEmmanuel Vadot 115b5be541fSEmmanuel Vadot struct aw_mmc_softc { 116b5be541fSEmmanuel Vadot device_t aw_dev; 117b5be541fSEmmanuel Vadot clk_t aw_clk_ahb; 118b5be541fSEmmanuel Vadot clk_t aw_clk_mmc; 119b5be541fSEmmanuel Vadot hwreset_t aw_rst_ahb; 120b5be541fSEmmanuel Vadot int aw_bus_busy; 121b5be541fSEmmanuel Vadot int aw_resid; 122b5be541fSEmmanuel Vadot int aw_timeout; 123b5be541fSEmmanuel Vadot struct callout aw_timeoutc; 124b5be541fSEmmanuel Vadot struct mmc_host aw_host; 1255e03278fSIlya Bakulin #ifdef MMCCAM 1265e03278fSIlya Bakulin union ccb * ccb; 1275e03278fSIlya Bakulin struct cam_devq * devq; 1285e03278fSIlya Bakulin struct cam_sim * sim; 1295e03278fSIlya Bakulin struct mtx sim_mtx; 1305e03278fSIlya Bakulin #else 131b5be541fSEmmanuel Vadot struct mmc_request * aw_req; 1325e03278fSIlya Bakulin #endif 133b5be541fSEmmanuel Vadot struct mtx aw_mtx; 134b5be541fSEmmanuel Vadot struct resource * aw_res[AW_MMC_RESSZ]; 135ce0618beSEmmanuel Vadot struct aw_mmc_conf * aw_mmc_conf; 136b5be541fSEmmanuel Vadot uint32_t aw_intr; 137b5be541fSEmmanuel Vadot uint32_t aw_intr_wait; 138b5be541fSEmmanuel Vadot void * aw_intrhand; 139ce0618beSEmmanuel Vadot regulator_t aw_reg_vmmc; 140ce0618beSEmmanuel Vadot regulator_t aw_reg_vqmmc; 1410f7a6420SEmmanuel Vadot unsigned int aw_clock; 142b5be541fSEmmanuel Vadot 143b5be541fSEmmanuel Vadot /* Fields required for DMA access. */ 144b5be541fSEmmanuel Vadot bus_addr_t aw_dma_desc_phys; 145b5be541fSEmmanuel Vadot bus_dmamap_t aw_dma_map; 146b5be541fSEmmanuel Vadot bus_dma_tag_t aw_dma_tag; 147b5be541fSEmmanuel Vadot void * aw_dma_desc; 148b5be541fSEmmanuel Vadot bus_dmamap_t aw_dma_buf_map; 149b5be541fSEmmanuel Vadot bus_dma_tag_t aw_dma_buf_tag; 150b5be541fSEmmanuel Vadot int aw_dma_map_err; 151b5be541fSEmmanuel Vadot }; 152b5be541fSEmmanuel Vadot 153b5be541fSEmmanuel Vadot static struct resource_spec aw_mmc_res_spec[] = { 154b5be541fSEmmanuel Vadot { SYS_RES_MEMORY, 0, RF_ACTIVE }, 155b5be541fSEmmanuel Vadot { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 156b5be541fSEmmanuel Vadot { -1, 0, 0 } 157b5be541fSEmmanuel Vadot }; 158b5be541fSEmmanuel Vadot 159b5be541fSEmmanuel Vadot static int aw_mmc_probe(device_t); 160b5be541fSEmmanuel Vadot static int aw_mmc_attach(device_t); 161b5be541fSEmmanuel Vadot static int aw_mmc_detach(device_t); 162b5be541fSEmmanuel Vadot static int aw_mmc_setup_dma(struct aw_mmc_softc *); 163b5be541fSEmmanuel Vadot static int aw_mmc_reset(struct aw_mmc_softc *); 16435a18619SEmmanuel Vadot static int aw_mmc_init(struct aw_mmc_softc *); 165b5be541fSEmmanuel Vadot static void aw_mmc_intr(void *); 166b5be541fSEmmanuel Vadot static int aw_mmc_update_clock(struct aw_mmc_softc *, uint32_t); 167b5be541fSEmmanuel Vadot 1685e03278fSIlya Bakulin static void aw_mmc_print_error(uint32_t); 169b5be541fSEmmanuel Vadot static int aw_mmc_update_ios(device_t, device_t); 170b5be541fSEmmanuel Vadot static int aw_mmc_request(device_t, device_t, struct mmc_request *); 171b5be541fSEmmanuel Vadot static int aw_mmc_get_ro(device_t, device_t); 172b5be541fSEmmanuel Vadot static int aw_mmc_acquire_host(device_t, device_t); 173b5be541fSEmmanuel Vadot static int aw_mmc_release_host(device_t, device_t); 1745e03278fSIlya Bakulin #ifdef MMCCAM 1755e03278fSIlya Bakulin static void aw_mmc_cam_action(struct cam_sim *, union ccb *); 1765e03278fSIlya Bakulin static void aw_mmc_cam_poll(struct cam_sim *); 1775e03278fSIlya Bakulin static int aw_mmc_cam_settran_settings(struct aw_mmc_softc *, union ccb *); 1785e03278fSIlya Bakulin static int aw_mmc_cam_request(struct aw_mmc_softc *, union ccb *); 1795e03278fSIlya Bakulin static void aw_mmc_cam_handle_mmcio(struct cam_sim *, union ccb *); 1805e03278fSIlya Bakulin #endif 181b5be541fSEmmanuel Vadot 182b5be541fSEmmanuel Vadot #define AW_MMC_LOCK(_sc) mtx_lock(&(_sc)->aw_mtx) 183b5be541fSEmmanuel Vadot #define AW_MMC_UNLOCK(_sc) mtx_unlock(&(_sc)->aw_mtx) 184b5be541fSEmmanuel Vadot #define AW_MMC_READ_4(_sc, _reg) \ 185b5be541fSEmmanuel Vadot bus_read_4((_sc)->aw_res[AW_MMC_MEMRES], _reg) 186b5be541fSEmmanuel Vadot #define AW_MMC_WRITE_4(_sc, _reg, _value) \ 187b5be541fSEmmanuel Vadot bus_write_4((_sc)->aw_res[AW_MMC_MEMRES], _reg, _value) 188b5be541fSEmmanuel Vadot 1895e03278fSIlya Bakulin #ifdef MMCCAM 1905e03278fSIlya Bakulin static void 1915e03278fSIlya Bakulin aw_mmc_cam_handle_mmcio(struct cam_sim *sim, union ccb *ccb) 1925e03278fSIlya Bakulin { 1935e03278fSIlya Bakulin struct aw_mmc_softc *sc; 1945e03278fSIlya Bakulin 1955e03278fSIlya Bakulin sc = cam_sim_softc(sim); 1965e03278fSIlya Bakulin 1975e03278fSIlya Bakulin aw_mmc_cam_request(sc, ccb); 1985e03278fSIlya Bakulin } 1995e03278fSIlya Bakulin 2005e03278fSIlya Bakulin static void 2015e03278fSIlya Bakulin aw_mmc_cam_action(struct cam_sim *sim, union ccb *ccb) 2025e03278fSIlya Bakulin { 2035e03278fSIlya Bakulin struct aw_mmc_softc *sc; 2045e03278fSIlya Bakulin 2055e03278fSIlya Bakulin sc = cam_sim_softc(sim); 2065e03278fSIlya Bakulin if (sc == NULL) { 2075e03278fSIlya Bakulin ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2085e03278fSIlya Bakulin xpt_done(ccb); 2095e03278fSIlya Bakulin return; 2105e03278fSIlya Bakulin } 2115e03278fSIlya Bakulin 2125e03278fSIlya Bakulin mtx_assert(&sc->sim_mtx, MA_OWNED); 2135e03278fSIlya Bakulin 2145e03278fSIlya Bakulin switch (ccb->ccb_h.func_code) { 2155e03278fSIlya Bakulin case XPT_PATH_INQ: 2165e03278fSIlya Bakulin { 2175e03278fSIlya Bakulin struct ccb_pathinq *cpi; 2185e03278fSIlya Bakulin 2195e03278fSIlya Bakulin cpi = &ccb->cpi; 2205e03278fSIlya Bakulin cpi->version_num = 1; 2215e03278fSIlya Bakulin cpi->hba_inquiry = 0; 2225e03278fSIlya Bakulin cpi->target_sprt = 0; 2235e03278fSIlya Bakulin cpi->hba_misc = PIM_NOBUSRESET | PIM_SEQSCAN; 2245e03278fSIlya Bakulin cpi->hba_eng_cnt = 0; 2255e03278fSIlya Bakulin cpi->max_target = 0; 2265e03278fSIlya Bakulin cpi->max_lun = 0; 2275e03278fSIlya Bakulin cpi->initiator_id = 1; 2285e03278fSIlya Bakulin cpi->maxio = (sc->aw_mmc_conf->dma_xferlen * 2295e03278fSIlya Bakulin AW_MMC_DMA_SEGS) / MMC_SECTOR_SIZE; 2305e03278fSIlya Bakulin strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2315e03278fSIlya Bakulin strncpy(cpi->hba_vid, "Deglitch Networks", HBA_IDLEN); 2325e03278fSIlya Bakulin strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2335e03278fSIlya Bakulin cpi->unit_number = cam_sim_unit(sim); 2345e03278fSIlya Bakulin cpi->bus_id = cam_sim_bus(sim); 2355e03278fSIlya Bakulin cpi->protocol = PROTO_MMCSD; 2365e03278fSIlya Bakulin cpi->protocol_version = SCSI_REV_0; 2375e03278fSIlya Bakulin cpi->transport = XPORT_MMCSD; 2385e03278fSIlya Bakulin cpi->transport_version = 1; 2395e03278fSIlya Bakulin 2405e03278fSIlya Bakulin cpi->ccb_h.status = CAM_REQ_CMP; 2415e03278fSIlya Bakulin break; 2425e03278fSIlya Bakulin } 2435e03278fSIlya Bakulin case XPT_GET_TRAN_SETTINGS: 2445e03278fSIlya Bakulin { 2455e03278fSIlya Bakulin struct ccb_trans_settings *cts = &ccb->cts; 2465e03278fSIlya Bakulin 2475e03278fSIlya Bakulin if (bootverbose) 2485e03278fSIlya Bakulin device_printf(sc->aw_dev, "Got XPT_GET_TRAN_SETTINGS\n"); 2495e03278fSIlya Bakulin 2505e03278fSIlya Bakulin cts->protocol = PROTO_MMCSD; 2515e03278fSIlya Bakulin cts->protocol_version = 1; 2525e03278fSIlya Bakulin cts->transport = XPORT_MMCSD; 2535e03278fSIlya Bakulin cts->transport_version = 1; 2545e03278fSIlya Bakulin cts->xport_specific.valid = 0; 2555e03278fSIlya Bakulin cts->proto_specific.mmc.host_ocr = sc->aw_host.host_ocr; 2565e03278fSIlya Bakulin cts->proto_specific.mmc.host_f_min = sc->aw_host.f_min; 2575e03278fSIlya Bakulin cts->proto_specific.mmc.host_f_max = sc->aw_host.f_max; 2585e03278fSIlya Bakulin cts->proto_specific.mmc.host_caps = sc->aw_host.caps; 2595e03278fSIlya Bakulin memcpy(&cts->proto_specific.mmc.ios, &sc->aw_host.ios, sizeof(struct mmc_ios)); 2605e03278fSIlya Bakulin ccb->ccb_h.status = CAM_REQ_CMP; 2615e03278fSIlya Bakulin break; 2625e03278fSIlya Bakulin } 2635e03278fSIlya Bakulin case XPT_SET_TRAN_SETTINGS: 2645e03278fSIlya Bakulin { 2655e03278fSIlya Bakulin if (bootverbose) 2665e03278fSIlya Bakulin device_printf(sc->aw_dev, "Got XPT_SET_TRAN_SETTINGS\n"); 2675e03278fSIlya Bakulin aw_mmc_cam_settran_settings(sc, ccb); 2685e03278fSIlya Bakulin ccb->ccb_h.status = CAM_REQ_CMP; 2695e03278fSIlya Bakulin break; 2705e03278fSIlya Bakulin } 2715e03278fSIlya Bakulin case XPT_RESET_BUS: 2725e03278fSIlya Bakulin if (bootverbose) 2735e03278fSIlya Bakulin device_printf(sc->aw_dev, "Got XPT_RESET_BUS, ACK it...\n"); 2745e03278fSIlya Bakulin ccb->ccb_h.status = CAM_REQ_CMP; 2755e03278fSIlya Bakulin break; 2765e03278fSIlya Bakulin case XPT_MMC_IO: 2775e03278fSIlya Bakulin /* 2785e03278fSIlya Bakulin * Here is the HW-dependent part of 2795e03278fSIlya Bakulin * sending the command to the underlying h/w 2805e03278fSIlya Bakulin * At some point in the future an interrupt comes. 2815e03278fSIlya Bakulin * Then the request will be marked as completed. 2825e03278fSIlya Bakulin */ 2835e03278fSIlya Bakulin ccb->ccb_h.status = CAM_REQ_INPROG; 2845e03278fSIlya Bakulin 2855e03278fSIlya Bakulin aw_mmc_cam_handle_mmcio(sim, ccb); 2865e03278fSIlya Bakulin return; 2875e03278fSIlya Bakulin /* NOTREACHED */ 2885e03278fSIlya Bakulin break; 2895e03278fSIlya Bakulin default: 2905e03278fSIlya Bakulin ccb->ccb_h.status = CAM_REQ_INVALID; 2915e03278fSIlya Bakulin break; 2925e03278fSIlya Bakulin } 2935e03278fSIlya Bakulin xpt_done(ccb); 2945e03278fSIlya Bakulin return; 2955e03278fSIlya Bakulin } 2965e03278fSIlya Bakulin 2975e03278fSIlya Bakulin static void 2985e03278fSIlya Bakulin aw_mmc_cam_poll(struct cam_sim *sim) 2995e03278fSIlya Bakulin { 3005e03278fSIlya Bakulin return; 3015e03278fSIlya Bakulin } 3025e03278fSIlya Bakulin 3035e03278fSIlya Bakulin static int 3045e03278fSIlya Bakulin aw_mmc_cam_settran_settings(struct aw_mmc_softc *sc, union ccb *ccb) 3055e03278fSIlya Bakulin { 3065e03278fSIlya Bakulin struct mmc_ios *ios; 3075e03278fSIlya Bakulin struct mmc_ios *new_ios; 3085e03278fSIlya Bakulin struct ccb_trans_settings_mmc *cts; 3095e03278fSIlya Bakulin 3105e03278fSIlya Bakulin ios = &sc->aw_host.ios; 3115e03278fSIlya Bakulin 3125e03278fSIlya Bakulin cts = &ccb->cts.proto_specific.mmc; 3135e03278fSIlya Bakulin new_ios = &cts->ios; 3145e03278fSIlya Bakulin 3155e03278fSIlya Bakulin /* Update only requested fields */ 3165e03278fSIlya Bakulin if (cts->ios_valid & MMC_CLK) { 3175e03278fSIlya Bakulin ios->clock = new_ios->clock; 3185e03278fSIlya Bakulin device_printf(sc->aw_dev, "Clock => %d\n", ios->clock); 3195e03278fSIlya Bakulin } 3205e03278fSIlya Bakulin if (cts->ios_valid & MMC_VDD) { 3215e03278fSIlya Bakulin ios->vdd = new_ios->vdd; 3225e03278fSIlya Bakulin device_printf(sc->aw_dev, "VDD => %d\n", ios->vdd); 3235e03278fSIlya Bakulin } 3245e03278fSIlya Bakulin if (cts->ios_valid & MMC_CS) { 3255e03278fSIlya Bakulin ios->chip_select = new_ios->chip_select; 3265e03278fSIlya Bakulin device_printf(sc->aw_dev, "CS => %d\n", ios->chip_select); 3275e03278fSIlya Bakulin } 3285e03278fSIlya Bakulin if (cts->ios_valid & MMC_BW) { 3295e03278fSIlya Bakulin ios->bus_width = new_ios->bus_width; 3305e03278fSIlya Bakulin device_printf(sc->aw_dev, "Bus width => %d\n", ios->bus_width); 3315e03278fSIlya Bakulin } 3325e03278fSIlya Bakulin if (cts->ios_valid & MMC_PM) { 3335e03278fSIlya Bakulin ios->power_mode = new_ios->power_mode; 3345e03278fSIlya Bakulin device_printf(sc->aw_dev, "Power mode => %d\n", ios->power_mode); 3355e03278fSIlya Bakulin } 3365e03278fSIlya Bakulin if (cts->ios_valid & MMC_BT) { 3375e03278fSIlya Bakulin ios->timing = new_ios->timing; 3385e03278fSIlya Bakulin device_printf(sc->aw_dev, "Timing => %d\n", ios->timing); 3395e03278fSIlya Bakulin } 3405e03278fSIlya Bakulin if (cts->ios_valid & MMC_BM) { 3415e03278fSIlya Bakulin ios->bus_mode = new_ios->bus_mode; 3425e03278fSIlya Bakulin device_printf(sc->aw_dev, "Bus mode => %d\n", ios->bus_mode); 3435e03278fSIlya Bakulin } 3445e03278fSIlya Bakulin 3455e03278fSIlya Bakulin return (aw_mmc_update_ios(sc->aw_dev, NULL)); 3465e03278fSIlya Bakulin } 3475e03278fSIlya Bakulin 3485e03278fSIlya Bakulin static int 3495e03278fSIlya Bakulin aw_mmc_cam_request(struct aw_mmc_softc *sc, union ccb *ccb) 3505e03278fSIlya Bakulin { 3515e03278fSIlya Bakulin struct ccb_mmcio *mmcio; 3525e03278fSIlya Bakulin 3535e03278fSIlya Bakulin mmcio = &ccb->mmcio; 3545e03278fSIlya Bakulin 3555e03278fSIlya Bakulin AW_MMC_LOCK(sc); 3565e03278fSIlya Bakulin 3575e03278fSIlya Bakulin #ifdef DEBUG 3585e03278fSIlya Bakulin if (__predict_false(bootverbose)) { 3595e03278fSIlya Bakulin device_printf(sc->aw_dev, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 3605e03278fSIlya Bakulin mmcio->cmd.opcode, mmcio->cmd.arg, mmcio->cmd.flags, 3615e03278fSIlya Bakulin mmcio->cmd.data != NULL ? (unsigned int) mmcio->cmd.data->len : 0, 3625e03278fSIlya Bakulin mmcio->cmd.data != NULL ? mmcio->cmd.data->flags: 0); 3635e03278fSIlya Bakulin } 3645e03278fSIlya Bakulin #endif 3655e03278fSIlya Bakulin if (mmcio->cmd.data != NULL) { 3665e03278fSIlya Bakulin if (mmcio->cmd.data->len == 0 || mmcio->cmd.data->flags == 0) 3675e03278fSIlya Bakulin panic("data->len = %d, data->flags = %d -- something is b0rked", 3685e03278fSIlya Bakulin (int)mmcio->cmd.data->len, mmcio->cmd.data->flags); 3695e03278fSIlya Bakulin } 3705e03278fSIlya Bakulin if (sc->ccb != NULL) { 3715e03278fSIlya Bakulin device_printf(sc->aw_dev, "Controller still has an active command\n"); 3725e03278fSIlya Bakulin return (EBUSY); 3735e03278fSIlya Bakulin } 3745e03278fSIlya Bakulin sc->ccb = ccb; 3755e03278fSIlya Bakulin /* aw_mmc_request locks again */ 3765e03278fSIlya Bakulin AW_MMC_UNLOCK(sc); 3775e03278fSIlya Bakulin aw_mmc_request(sc->aw_dev, NULL, NULL); 3785e03278fSIlya Bakulin 3795e03278fSIlya Bakulin return (0); 3805e03278fSIlya Bakulin } 3815e03278fSIlya Bakulin #endif /* MMCCAM */ 3825e03278fSIlya Bakulin 383b5be541fSEmmanuel Vadot static int 384b5be541fSEmmanuel Vadot aw_mmc_probe(device_t dev) 385b5be541fSEmmanuel Vadot { 386b5be541fSEmmanuel Vadot 387b5be541fSEmmanuel Vadot if (!ofw_bus_status_okay(dev)) 388b5be541fSEmmanuel Vadot return (ENXIO); 389b5be541fSEmmanuel Vadot if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 390b5be541fSEmmanuel Vadot return (ENXIO); 391b5be541fSEmmanuel Vadot 392b5be541fSEmmanuel Vadot device_set_desc(dev, "Allwinner Integrated MMC/SD controller"); 393b5be541fSEmmanuel Vadot 394b5be541fSEmmanuel Vadot return (BUS_PROBE_DEFAULT); 395b5be541fSEmmanuel Vadot } 396b5be541fSEmmanuel Vadot 397b5be541fSEmmanuel Vadot static int 398b5be541fSEmmanuel Vadot aw_mmc_attach(device_t dev) 399b5be541fSEmmanuel Vadot { 400b5be541fSEmmanuel Vadot device_t child; 401b5be541fSEmmanuel Vadot struct aw_mmc_softc *sc; 402b5be541fSEmmanuel Vadot struct sysctl_ctx_list *ctx; 403b5be541fSEmmanuel Vadot struct sysctl_oid_list *tree; 404bbf8c8faSEmmanuel Vadot uint32_t bus_width, max_freq; 405b5be541fSEmmanuel Vadot phandle_t node; 406b5be541fSEmmanuel Vadot int error; 407b5be541fSEmmanuel Vadot 408b5be541fSEmmanuel Vadot node = ofw_bus_get_node(dev); 409b5be541fSEmmanuel Vadot sc = device_get_softc(dev); 410b5be541fSEmmanuel Vadot sc->aw_dev = dev; 411ce0618beSEmmanuel Vadot 412ce0618beSEmmanuel Vadot sc->aw_mmc_conf = (struct aw_mmc_conf *)ofw_bus_search_compatible(dev, compat_data)->ocd_data; 413ce0618beSEmmanuel Vadot 4145e03278fSIlya Bakulin #ifndef MMCCAM 415b5be541fSEmmanuel Vadot sc->aw_req = NULL; 4165e03278fSIlya Bakulin #endif 417b5be541fSEmmanuel Vadot if (bus_alloc_resources(dev, aw_mmc_res_spec, sc->aw_res) != 0) { 418b5be541fSEmmanuel Vadot device_printf(dev, "cannot allocate device resources\n"); 419b5be541fSEmmanuel Vadot return (ENXIO); 420b5be541fSEmmanuel Vadot } 421b5be541fSEmmanuel Vadot if (bus_setup_intr(dev, sc->aw_res[AW_MMC_IRQRES], 422b5be541fSEmmanuel Vadot INTR_TYPE_MISC | INTR_MPSAFE, NULL, aw_mmc_intr, sc, 423b5be541fSEmmanuel Vadot &sc->aw_intrhand)) { 424b5be541fSEmmanuel Vadot bus_release_resources(dev, aw_mmc_res_spec, sc->aw_res); 425b5be541fSEmmanuel Vadot device_printf(dev, "cannot setup interrupt handler\n"); 426b5be541fSEmmanuel Vadot return (ENXIO); 427b5be541fSEmmanuel Vadot } 428b5be541fSEmmanuel Vadot mtx_init(&sc->aw_mtx, device_get_nameunit(sc->aw_dev), "aw_mmc", 429b5be541fSEmmanuel Vadot MTX_DEF); 430b5be541fSEmmanuel Vadot callout_init_mtx(&sc->aw_timeoutc, &sc->aw_mtx, 0); 431b5be541fSEmmanuel Vadot 432b5be541fSEmmanuel Vadot /* De-assert reset */ 433b5be541fSEmmanuel Vadot if (hwreset_get_by_ofw_name(dev, 0, "ahb", &sc->aw_rst_ahb) == 0) { 434b5be541fSEmmanuel Vadot error = hwreset_deassert(sc->aw_rst_ahb); 435b5be541fSEmmanuel Vadot if (error != 0) { 436b5be541fSEmmanuel Vadot device_printf(dev, "cannot de-assert reset\n"); 437b5be541fSEmmanuel Vadot goto fail; 438b5be541fSEmmanuel Vadot } 439b5be541fSEmmanuel Vadot } 440b5be541fSEmmanuel Vadot 441b5be541fSEmmanuel Vadot /* Activate the module clock. */ 442b5be541fSEmmanuel Vadot error = clk_get_by_ofw_name(dev, 0, "ahb", &sc->aw_clk_ahb); 443b5be541fSEmmanuel Vadot if (error != 0) { 444b5be541fSEmmanuel Vadot device_printf(dev, "cannot get ahb clock\n"); 445b5be541fSEmmanuel Vadot goto fail; 446b5be541fSEmmanuel Vadot } 447b5be541fSEmmanuel Vadot error = clk_enable(sc->aw_clk_ahb); 448b5be541fSEmmanuel Vadot if (error != 0) { 449b5be541fSEmmanuel Vadot device_printf(dev, "cannot enable ahb clock\n"); 450b5be541fSEmmanuel Vadot goto fail; 451b5be541fSEmmanuel Vadot } 452b5be541fSEmmanuel Vadot error = clk_get_by_ofw_name(dev, 0, "mmc", &sc->aw_clk_mmc); 453b5be541fSEmmanuel Vadot if (error != 0) { 454b5be541fSEmmanuel Vadot device_printf(dev, "cannot get mmc clock\n"); 455b5be541fSEmmanuel Vadot goto fail; 456b5be541fSEmmanuel Vadot } 457b5be541fSEmmanuel Vadot error = clk_set_freq(sc->aw_clk_mmc, CARD_ID_FREQUENCY, 458b5be541fSEmmanuel Vadot CLK_SET_ROUND_DOWN); 459b5be541fSEmmanuel Vadot if (error != 0) { 460b5be541fSEmmanuel Vadot device_printf(dev, "cannot init mmc clock\n"); 461b5be541fSEmmanuel Vadot goto fail; 462b5be541fSEmmanuel Vadot } 463b5be541fSEmmanuel Vadot error = clk_enable(sc->aw_clk_mmc); 464b5be541fSEmmanuel Vadot if (error != 0) { 465b5be541fSEmmanuel Vadot device_printf(dev, "cannot enable mmc clock\n"); 466b5be541fSEmmanuel Vadot goto fail; 467b5be541fSEmmanuel Vadot } 468b5be541fSEmmanuel Vadot 469b5be541fSEmmanuel Vadot sc->aw_timeout = 10; 470b5be541fSEmmanuel Vadot ctx = device_get_sysctl_ctx(dev); 471b5be541fSEmmanuel Vadot tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 472b5be541fSEmmanuel Vadot SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "req_timeout", CTLFLAG_RW, 473b5be541fSEmmanuel Vadot &sc->aw_timeout, 0, "Request timeout in seconds"); 474b5be541fSEmmanuel Vadot 475b5be541fSEmmanuel Vadot /* Soft Reset controller. */ 476b5be541fSEmmanuel Vadot if (aw_mmc_reset(sc) != 0) { 477b5be541fSEmmanuel Vadot device_printf(dev, "cannot reset the controller\n"); 478b5be541fSEmmanuel Vadot goto fail; 479b5be541fSEmmanuel Vadot } 480b5be541fSEmmanuel Vadot 481b5be541fSEmmanuel Vadot if (aw_mmc_setup_dma(sc) != 0) { 482b5be541fSEmmanuel Vadot device_printf(sc->aw_dev, "Couldn't setup DMA!\n"); 483b5be541fSEmmanuel Vadot goto fail; 484b5be541fSEmmanuel Vadot } 485b5be541fSEmmanuel Vadot 486b5be541fSEmmanuel Vadot if (OF_getencprop(node, "bus-width", &bus_width, sizeof(uint32_t)) <= 0) 487b5be541fSEmmanuel Vadot bus_width = 4; 488b5be541fSEmmanuel Vadot 489ce0618beSEmmanuel Vadot if (regulator_get_by_ofw_property(dev, 0, "vmmc-supply", 4903177f7cdSEmmanuel Vadot &sc->aw_reg_vmmc) == 0) { 4913177f7cdSEmmanuel Vadot if (bootverbose) 492ce0618beSEmmanuel Vadot device_printf(dev, "vmmc-supply regulator found\n"); 4933177f7cdSEmmanuel Vadot } 494ce0618beSEmmanuel Vadot if (regulator_get_by_ofw_property(dev, 0, "vqmmc-supply", 4953177f7cdSEmmanuel Vadot &sc->aw_reg_vqmmc) == 0 && bootverbose) { 4963177f7cdSEmmanuel Vadot if (bootverbose) 497ce0618beSEmmanuel Vadot device_printf(dev, "vqmmc-supply regulator found\n"); 4983177f7cdSEmmanuel Vadot } 499ce0618beSEmmanuel Vadot 500b5be541fSEmmanuel Vadot sc->aw_host.f_min = 400000; 501bbf8c8faSEmmanuel Vadot 502bbf8c8faSEmmanuel Vadot if (OF_getencprop(node, "max-frequency", &max_freq, 503bbf8c8faSEmmanuel Vadot sizeof(uint32_t)) <= 0) 504bbf8c8faSEmmanuel Vadot max_freq = 52000000; 505bbf8c8faSEmmanuel Vadot sc->aw_host.f_max = max_freq; 506bbf8c8faSEmmanuel Vadot 507b5be541fSEmmanuel Vadot sc->aw_host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340; 508ce0618beSEmmanuel Vadot sc->aw_host.caps = MMC_CAP_HSPEED | MMC_CAP_UHS_SDR12 | 509ce0618beSEmmanuel Vadot MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR50 | 510ce0618beSEmmanuel Vadot MMC_CAP_UHS_DDR50 | MMC_CAP_MMC_DDR52; 511ce0618beSEmmanuel Vadot 512dfb8c122SEmmanuel Vadot sc->aw_host.caps |= MMC_CAP_SIGNALING_330 | MMC_CAP_SIGNALING_180; 513ce0618beSEmmanuel Vadot 514b5be541fSEmmanuel Vadot if (bus_width >= 4) 515b5be541fSEmmanuel Vadot sc->aw_host.caps |= MMC_CAP_4_BIT_DATA; 516b5be541fSEmmanuel Vadot if (bus_width >= 8) 517b5be541fSEmmanuel Vadot sc->aw_host.caps |= MMC_CAP_8_BIT_DATA; 518b5be541fSEmmanuel Vadot 5195e03278fSIlya Bakulin #ifdef MMCCAM 5205e03278fSIlya Bakulin child = NULL; /* Not used by MMCCAM, need to silence compiler warnings */ 5215e03278fSIlya Bakulin sc->ccb = NULL; 5225e03278fSIlya Bakulin if ((sc->devq = cam_simq_alloc(1)) == NULL) { 5235e03278fSIlya Bakulin goto fail; 5245e03278fSIlya Bakulin } 5255e03278fSIlya Bakulin 5265e03278fSIlya Bakulin mtx_init(&sc->sim_mtx, "awmmcsim", NULL, MTX_DEF); 5275e03278fSIlya Bakulin sc->sim = cam_sim_alloc(aw_mmc_cam_action, aw_mmc_cam_poll, 5285e03278fSIlya Bakulin "aw_mmc_sim", sc, device_get_unit(dev), 5295e03278fSIlya Bakulin &sc->sim_mtx, 1, 1, sc->devq); 5305e03278fSIlya Bakulin 5315e03278fSIlya Bakulin if (sc->sim == NULL) { 5325e03278fSIlya Bakulin cam_simq_free(sc->devq); 5335e03278fSIlya Bakulin device_printf(dev, "cannot allocate CAM SIM\n"); 5345e03278fSIlya Bakulin goto fail; 5355e03278fSIlya Bakulin } 5365e03278fSIlya Bakulin 5375e03278fSIlya Bakulin mtx_lock(&sc->sim_mtx); 5385e03278fSIlya Bakulin if (xpt_bus_register(sc->sim, sc->aw_dev, 0) != 0) { 5395e03278fSIlya Bakulin device_printf(dev, "cannot register SCSI pass-through bus\n"); 5405e03278fSIlya Bakulin cam_sim_free(sc->sim, FALSE); 5415e03278fSIlya Bakulin cam_simq_free(sc->devq); 5425e03278fSIlya Bakulin mtx_unlock(&sc->sim_mtx); 5435e03278fSIlya Bakulin goto fail; 5445e03278fSIlya Bakulin } 5455e03278fSIlya Bakulin 5465e03278fSIlya Bakulin mtx_unlock(&sc->sim_mtx); 5475e03278fSIlya Bakulin #else /* !MMCCAM */ 548b5be541fSEmmanuel Vadot child = device_add_child(dev, "mmc", -1); 549b5be541fSEmmanuel Vadot if (child == NULL) { 550b5be541fSEmmanuel Vadot device_printf(dev, "attaching MMC bus failed!\n"); 551b5be541fSEmmanuel Vadot goto fail; 552b5be541fSEmmanuel Vadot } 553b5be541fSEmmanuel Vadot if (device_probe_and_attach(child) != 0) { 554b5be541fSEmmanuel Vadot device_printf(dev, "attaching MMC child failed!\n"); 555b5be541fSEmmanuel Vadot device_delete_child(dev, child); 556b5be541fSEmmanuel Vadot goto fail; 557b5be541fSEmmanuel Vadot } 5585e03278fSIlya Bakulin #endif /* MMCCAM */ 559b5be541fSEmmanuel Vadot return (0); 560b5be541fSEmmanuel Vadot 561b5be541fSEmmanuel Vadot fail: 562b5be541fSEmmanuel Vadot callout_drain(&sc->aw_timeoutc); 563b5be541fSEmmanuel Vadot mtx_destroy(&sc->aw_mtx); 564b5be541fSEmmanuel Vadot bus_teardown_intr(dev, sc->aw_res[AW_MMC_IRQRES], sc->aw_intrhand); 565b5be541fSEmmanuel Vadot bus_release_resources(dev, aw_mmc_res_spec, sc->aw_res); 566b5be541fSEmmanuel Vadot 5675e03278fSIlya Bakulin #ifdef MMCCAM 5685e03278fSIlya Bakulin if (sc->sim != NULL) { 5695e03278fSIlya Bakulin mtx_lock(&sc->sim_mtx); 5705e03278fSIlya Bakulin xpt_bus_deregister(cam_sim_path(sc->sim)); 5715e03278fSIlya Bakulin cam_sim_free(sc->sim, FALSE); 5725e03278fSIlya Bakulin mtx_unlock(&sc->sim_mtx); 5735e03278fSIlya Bakulin } 5745e03278fSIlya Bakulin 5755e03278fSIlya Bakulin if (sc->devq != NULL) 5765e03278fSIlya Bakulin cam_simq_free(sc->devq); 5775e03278fSIlya Bakulin #endif 578b5be541fSEmmanuel Vadot return (ENXIO); 579b5be541fSEmmanuel Vadot } 580b5be541fSEmmanuel Vadot 581b5be541fSEmmanuel Vadot static int 582b5be541fSEmmanuel Vadot aw_mmc_detach(device_t dev) 583b5be541fSEmmanuel Vadot { 584b5be541fSEmmanuel Vadot 585b5be541fSEmmanuel Vadot return (EBUSY); 586b5be541fSEmmanuel Vadot } 587b5be541fSEmmanuel Vadot 588b5be541fSEmmanuel Vadot static void 589b5be541fSEmmanuel Vadot aw_dma_desc_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err) 590b5be541fSEmmanuel Vadot { 591b5be541fSEmmanuel Vadot struct aw_mmc_softc *sc; 592b5be541fSEmmanuel Vadot 593b5be541fSEmmanuel Vadot sc = (struct aw_mmc_softc *)arg; 594b5be541fSEmmanuel Vadot if (err) { 595b5be541fSEmmanuel Vadot sc->aw_dma_map_err = err; 596b5be541fSEmmanuel Vadot return; 597b5be541fSEmmanuel Vadot } 598b5be541fSEmmanuel Vadot sc->aw_dma_desc_phys = segs[0].ds_addr; 599b5be541fSEmmanuel Vadot } 600b5be541fSEmmanuel Vadot 601b5be541fSEmmanuel Vadot static int 602b5be541fSEmmanuel Vadot aw_mmc_setup_dma(struct aw_mmc_softc *sc) 603b5be541fSEmmanuel Vadot { 604c39ea909SEmmanuel Vadot int error; 605b5be541fSEmmanuel Vadot 606b5be541fSEmmanuel Vadot /* Allocate the DMA descriptor memory. */ 607c39ea909SEmmanuel Vadot error = bus_dma_tag_create( 608c39ea909SEmmanuel Vadot bus_get_dma_tag(sc->aw_dev), /* parent */ 609c39ea909SEmmanuel Vadot AW_MMC_DMA_ALIGN, 0, /* align, boundary */ 610c39ea909SEmmanuel Vadot BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 611c39ea909SEmmanuel Vadot BUS_SPACE_MAXADDR, /* highaddr */ 612c39ea909SEmmanuel Vadot NULL, NULL, /* filter, filterarg*/ 613c39ea909SEmmanuel Vadot AW_MMC_DMA_DESC_SIZE, 1, /* maxsize, nsegment */ 614c39ea909SEmmanuel Vadot AW_MMC_DMA_DESC_SIZE, /* maxsegsize */ 615c39ea909SEmmanuel Vadot 0, /* flags */ 616c39ea909SEmmanuel Vadot NULL, NULL, /* lock, lockarg*/ 617c39ea909SEmmanuel Vadot &sc->aw_dma_tag); 618b5be541fSEmmanuel Vadot if (error) 619b5be541fSEmmanuel Vadot return (error); 620b5be541fSEmmanuel Vadot 621c39ea909SEmmanuel Vadot error = bus_dmamem_alloc(sc->aw_dma_tag, &sc->aw_dma_desc, 622c39ea909SEmmanuel Vadot BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, 623c39ea909SEmmanuel Vadot &sc->aw_dma_map); 624c39ea909SEmmanuel Vadot if (error) 625c39ea909SEmmanuel Vadot return (error); 626c39ea909SEmmanuel Vadot 627c39ea909SEmmanuel Vadot error = bus_dmamap_load(sc->aw_dma_tag, 628c39ea909SEmmanuel Vadot sc->aw_dma_map, 629c39ea909SEmmanuel Vadot sc->aw_dma_desc, AW_MMC_DMA_DESC_SIZE, 630c39ea909SEmmanuel Vadot aw_dma_desc_cb, sc, 0); 631b5be541fSEmmanuel Vadot if (error) 632b5be541fSEmmanuel Vadot return (error); 633b5be541fSEmmanuel Vadot if (sc->aw_dma_map_err) 634b5be541fSEmmanuel Vadot return (sc->aw_dma_map_err); 635b5be541fSEmmanuel Vadot 636b5be541fSEmmanuel Vadot /* Create the DMA map for data transfers. */ 637c39ea909SEmmanuel Vadot error = bus_dma_tag_create( 638c39ea909SEmmanuel Vadot bus_get_dma_tag(sc->aw_dev), /* parent */ 639c39ea909SEmmanuel Vadot AW_MMC_DMA_ALIGN, 0, /* align, boundary */ 640c39ea909SEmmanuel Vadot BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 641c39ea909SEmmanuel Vadot BUS_SPACE_MAXADDR, /* highaddr */ 642c39ea909SEmmanuel Vadot NULL, NULL, /* filter, filterarg*/ 643c39ea909SEmmanuel Vadot sc->aw_mmc_conf->dma_xferlen * 644c39ea909SEmmanuel Vadot AW_MMC_DMA_SEGS, AW_MMC_DMA_SEGS, /* maxsize, nsegments */ 645c39ea909SEmmanuel Vadot sc->aw_mmc_conf->dma_xferlen, /* maxsegsize */ 646c39ea909SEmmanuel Vadot BUS_DMA_ALLOCNOW, /* flags */ 647c39ea909SEmmanuel Vadot NULL, NULL, /* lock, lockarg*/ 648b5be541fSEmmanuel Vadot &sc->aw_dma_buf_tag); 649b5be541fSEmmanuel Vadot if (error) 650b5be541fSEmmanuel Vadot return (error); 651b5be541fSEmmanuel Vadot error = bus_dmamap_create(sc->aw_dma_buf_tag, 0, 652b5be541fSEmmanuel Vadot &sc->aw_dma_buf_map); 653b5be541fSEmmanuel Vadot if (error) 654b5be541fSEmmanuel Vadot return (error); 655b5be541fSEmmanuel Vadot 656b5be541fSEmmanuel Vadot return (0); 657b5be541fSEmmanuel Vadot } 658b5be541fSEmmanuel Vadot 659b5be541fSEmmanuel Vadot static void 660b5be541fSEmmanuel Vadot aw_dma_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err) 661b5be541fSEmmanuel Vadot { 662b5be541fSEmmanuel Vadot int i; 663b5be541fSEmmanuel Vadot struct aw_mmc_dma_desc *dma_desc; 664b5be541fSEmmanuel Vadot struct aw_mmc_softc *sc; 665b5be541fSEmmanuel Vadot 666b5be541fSEmmanuel Vadot sc = (struct aw_mmc_softc *)arg; 667b5be541fSEmmanuel Vadot sc->aw_dma_map_err = err; 668b5be541fSEmmanuel Vadot 669b5be541fSEmmanuel Vadot if (err) 670b5be541fSEmmanuel Vadot return; 671b5be541fSEmmanuel Vadot 672b5be541fSEmmanuel Vadot dma_desc = sc->aw_dma_desc; 673b5be541fSEmmanuel Vadot for (i = 0; i < nsegs; i++) { 674c39ea909SEmmanuel Vadot if (segs[i].ds_len == sc->aw_mmc_conf->dma_xferlen) 675c39ea909SEmmanuel Vadot dma_desc[i].buf_size = 0; /* Size of 0 indicate max len */ 676c39ea909SEmmanuel Vadot else 677b5be541fSEmmanuel Vadot dma_desc[i].buf_size = segs[i].ds_len; 678b5be541fSEmmanuel Vadot dma_desc[i].buf_addr = segs[i].ds_addr; 679b5be541fSEmmanuel Vadot dma_desc[i].config = AW_MMC_DMA_CONFIG_CH | 680c39ea909SEmmanuel Vadot AW_MMC_DMA_CONFIG_OWN | AW_MMC_DMA_CONFIG_DIC; 681c39ea909SEmmanuel Vadot 682b5be541fSEmmanuel Vadot dma_desc[i].next = sc->aw_dma_desc_phys + 683b5be541fSEmmanuel Vadot ((i + 1) * sizeof(struct aw_mmc_dma_desc)); 684c39ea909SEmmanuel Vadot } 685c39ea909SEmmanuel Vadot 686c39ea909SEmmanuel Vadot dma_desc[0].config |= AW_MMC_DMA_CONFIG_FD; 687c39ea909SEmmanuel Vadot dma_desc[nsegs - 1].config |= AW_MMC_DMA_CONFIG_LD | 688b5be541fSEmmanuel Vadot AW_MMC_DMA_CONFIG_ER; 689c39ea909SEmmanuel Vadot dma_desc[nsegs - 1].config &= ~AW_MMC_DMA_CONFIG_DIC; 690c39ea909SEmmanuel Vadot dma_desc[nsegs - 1].next = 0; 691b5be541fSEmmanuel Vadot } 692b5be541fSEmmanuel Vadot 693b5be541fSEmmanuel Vadot static int 694b5be541fSEmmanuel Vadot aw_mmc_prepare_dma(struct aw_mmc_softc *sc) 695b5be541fSEmmanuel Vadot { 696b5be541fSEmmanuel Vadot bus_dmasync_op_t sync_op; 697b5be541fSEmmanuel Vadot int error; 698b5be541fSEmmanuel Vadot struct mmc_command *cmd; 699b5be541fSEmmanuel Vadot uint32_t val; 700b5be541fSEmmanuel Vadot 7015e03278fSIlya Bakulin #ifdef MMCCAM 7025e03278fSIlya Bakulin cmd = &sc->ccb->mmcio.cmd; 7035e03278fSIlya Bakulin #else 704b5be541fSEmmanuel Vadot cmd = sc->aw_req->cmd; 7055e03278fSIlya Bakulin #endif 706ce0618beSEmmanuel Vadot if (cmd->data->len > (sc->aw_mmc_conf->dma_xferlen * AW_MMC_DMA_SEGS)) 707b5be541fSEmmanuel Vadot return (EFBIG); 708b5be541fSEmmanuel Vadot error = bus_dmamap_load(sc->aw_dma_buf_tag, sc->aw_dma_buf_map, 709b5be541fSEmmanuel Vadot cmd->data->data, cmd->data->len, aw_dma_cb, sc, 0); 710b5be541fSEmmanuel Vadot if (error) 711b5be541fSEmmanuel Vadot return (error); 712b5be541fSEmmanuel Vadot if (sc->aw_dma_map_err) 713b5be541fSEmmanuel Vadot return (sc->aw_dma_map_err); 714b5be541fSEmmanuel Vadot 715b5be541fSEmmanuel Vadot if (cmd->data->flags & MMC_DATA_WRITE) 716b5be541fSEmmanuel Vadot sync_op = BUS_DMASYNC_PREWRITE; 717b5be541fSEmmanuel Vadot else 718b5be541fSEmmanuel Vadot sync_op = BUS_DMASYNC_PREREAD; 719b5be541fSEmmanuel Vadot bus_dmamap_sync(sc->aw_dma_buf_tag, sc->aw_dma_buf_map, sync_op); 720b5be541fSEmmanuel Vadot bus_dmamap_sync(sc->aw_dma_tag, sc->aw_dma_map, BUS_DMASYNC_PREWRITE); 721b5be541fSEmmanuel Vadot 722b5be541fSEmmanuel Vadot /* Enable DMA */ 723b5be541fSEmmanuel Vadot val = AW_MMC_READ_4(sc, AW_MMC_GCTL); 724b091392eSEmmanuel Vadot val &= ~AW_MMC_GCTL_FIFO_AC_MOD; 725b091392eSEmmanuel Vadot val |= AW_MMC_GCTL_DMA_ENB; 726b5be541fSEmmanuel Vadot AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val); 727b5be541fSEmmanuel Vadot 728b5be541fSEmmanuel Vadot /* Reset DMA */ 729b091392eSEmmanuel Vadot val |= AW_MMC_GCTL_DMA_RST; 730b5be541fSEmmanuel Vadot AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val); 731b5be541fSEmmanuel Vadot 732b5be541fSEmmanuel Vadot AW_MMC_WRITE_4(sc, AW_MMC_DMAC, AW_MMC_DMAC_IDMAC_SOFT_RST); 733b5be541fSEmmanuel Vadot AW_MMC_WRITE_4(sc, AW_MMC_DMAC, 734b5be541fSEmmanuel Vadot AW_MMC_DMAC_IDMAC_IDMA_ON | AW_MMC_DMAC_IDMAC_FIX_BURST); 735b5be541fSEmmanuel Vadot 736b5be541fSEmmanuel Vadot /* Enable RX or TX DMA interrupt */ 737a37d59c1SEmmanuel Vadot val = AW_MMC_READ_4(sc, AW_MMC_IDIE); 738b5be541fSEmmanuel Vadot if (cmd->data->flags & MMC_DATA_WRITE) 739b5be541fSEmmanuel Vadot val |= AW_MMC_IDST_TX_INT; 740b5be541fSEmmanuel Vadot else 741b5be541fSEmmanuel Vadot val |= AW_MMC_IDST_RX_INT; 742b5be541fSEmmanuel Vadot AW_MMC_WRITE_4(sc, AW_MMC_IDIE, val); 743b5be541fSEmmanuel Vadot 744b5be541fSEmmanuel Vadot /* Set DMA descritptor list address */ 745b5be541fSEmmanuel Vadot AW_MMC_WRITE_4(sc, AW_MMC_DLBA, sc->aw_dma_desc_phys); 746b5be541fSEmmanuel Vadot 747b5be541fSEmmanuel Vadot /* FIFO trigger level */ 748b5be541fSEmmanuel Vadot AW_MMC_WRITE_4(sc, AW_MMC_FWLR, AW_MMC_DMA_FTRGLEVEL); 749b5be541fSEmmanuel Vadot 750b5be541fSEmmanuel Vadot return (0); 751b5be541fSEmmanuel Vadot } 752b5be541fSEmmanuel Vadot 753b5be541fSEmmanuel Vadot static int 754b5be541fSEmmanuel Vadot aw_mmc_reset(struct aw_mmc_softc *sc) 755b5be541fSEmmanuel Vadot { 756b091392eSEmmanuel Vadot uint32_t reg; 757b5be541fSEmmanuel Vadot int timeout; 758b5be541fSEmmanuel Vadot 759b091392eSEmmanuel Vadot reg = AW_MMC_READ_4(sc, AW_MMC_GCTL); 760b091392eSEmmanuel Vadot reg |= AW_MMC_GCTL_RESET; 761b091392eSEmmanuel Vadot AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg); 762c39ea909SEmmanuel Vadot timeout = AW_MMC_RESET_RETRY; 763b5be541fSEmmanuel Vadot while (--timeout > 0) { 764b091392eSEmmanuel Vadot if ((AW_MMC_READ_4(sc, AW_MMC_GCTL) & AW_MMC_GCTL_RESET) == 0) 765b5be541fSEmmanuel Vadot break; 766b5be541fSEmmanuel Vadot DELAY(100); 767b5be541fSEmmanuel Vadot } 768b5be541fSEmmanuel Vadot if (timeout == 0) 769b5be541fSEmmanuel Vadot return (ETIMEDOUT); 770b5be541fSEmmanuel Vadot 77135a18619SEmmanuel Vadot return (0); 77235a18619SEmmanuel Vadot } 77335a18619SEmmanuel Vadot 77435a18619SEmmanuel Vadot static int 77535a18619SEmmanuel Vadot aw_mmc_init(struct aw_mmc_softc *sc) 77635a18619SEmmanuel Vadot { 777b091392eSEmmanuel Vadot uint32_t reg; 77835a18619SEmmanuel Vadot int ret; 77935a18619SEmmanuel Vadot 78035a18619SEmmanuel Vadot ret = aw_mmc_reset(sc); 78135a18619SEmmanuel Vadot if (ret != 0) 78235a18619SEmmanuel Vadot return (ret); 78335a18619SEmmanuel Vadot 784b5be541fSEmmanuel Vadot /* Set the timeout. */ 785b5be541fSEmmanuel Vadot AW_MMC_WRITE_4(sc, AW_MMC_TMOR, 786b5be541fSEmmanuel Vadot AW_MMC_TMOR_DTO_LMT_SHIFT(AW_MMC_TMOR_DTO_LMT_MASK) | 787b5be541fSEmmanuel Vadot AW_MMC_TMOR_RTO_LMT_SHIFT(AW_MMC_TMOR_RTO_LMT_MASK)); 788b5be541fSEmmanuel Vadot 78935a18619SEmmanuel Vadot /* Unmask interrupts. */ 79035a18619SEmmanuel Vadot AW_MMC_WRITE_4(sc, AW_MMC_IMKR, 0); 79135a18619SEmmanuel Vadot 792b5be541fSEmmanuel Vadot /* Clear pending interrupts. */ 793b5be541fSEmmanuel Vadot AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff); 79435a18619SEmmanuel Vadot 79535a18619SEmmanuel Vadot /* Debug register, undocumented */ 79635a18619SEmmanuel Vadot AW_MMC_WRITE_4(sc, AW_MMC_DBGC, 0xdeb); 79735a18619SEmmanuel Vadot 79835a18619SEmmanuel Vadot /* Function select register */ 79935a18619SEmmanuel Vadot AW_MMC_WRITE_4(sc, AW_MMC_FUNS, 0xceaa0000); 80035a18619SEmmanuel Vadot 801b5be541fSEmmanuel Vadot AW_MMC_WRITE_4(sc, AW_MMC_IDST, 0xffffffff); 80235a18619SEmmanuel Vadot 803b091392eSEmmanuel Vadot /* Enable interrupts and disable AHB access. */ 804b091392eSEmmanuel Vadot reg = AW_MMC_READ_4(sc, AW_MMC_GCTL); 805b091392eSEmmanuel Vadot reg |= AW_MMC_GCTL_INT_ENB; 806b091392eSEmmanuel Vadot reg &= ~AW_MMC_GCTL_FIFO_AC_MOD; 807b091392eSEmmanuel Vadot reg &= ~AW_MMC_GCTL_WAIT_MEM_ACCESS; 808b091392eSEmmanuel Vadot AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg); 809b5be541fSEmmanuel Vadot 810b5be541fSEmmanuel Vadot return (0); 811b5be541fSEmmanuel Vadot } 812b5be541fSEmmanuel Vadot 813b5be541fSEmmanuel Vadot static void 814b5be541fSEmmanuel Vadot aw_mmc_req_done(struct aw_mmc_softc *sc) 815b5be541fSEmmanuel Vadot { 816b5be541fSEmmanuel Vadot struct mmc_command *cmd; 8175e03278fSIlya Bakulin #ifdef MMCCAM 8185e03278fSIlya Bakulin union ccb *ccb; 8195e03278fSIlya Bakulin #else 820b5be541fSEmmanuel Vadot struct mmc_request *req; 8215e03278fSIlya Bakulin #endif 822b5be541fSEmmanuel Vadot uint32_t val, mask; 823b5be541fSEmmanuel Vadot int retry; 824b5be541fSEmmanuel Vadot 8255e03278fSIlya Bakulin #ifdef MMCCAM 8265e03278fSIlya Bakulin ccb = sc->ccb; 8275e03278fSIlya Bakulin cmd = &ccb->mmcio.cmd; 8285e03278fSIlya Bakulin #else 829b5be541fSEmmanuel Vadot cmd = sc->aw_req->cmd; 8305e03278fSIlya Bakulin #endif 8315e03278fSIlya Bakulin #ifdef DEBUG 8325e03278fSIlya Bakulin if (bootverbose) { 8335e03278fSIlya Bakulin device_printf(sc->aw_dev, "%s: cmd %d err %d\n", __func__, cmd->opcode, cmd->error); 8345e03278fSIlya Bakulin } 8355e03278fSIlya Bakulin #endif 836b5be541fSEmmanuel Vadot if (cmd->error != MMC_ERR_NONE) { 837b5be541fSEmmanuel Vadot /* Reset the FIFO and DMA engines. */ 838b091392eSEmmanuel Vadot mask = AW_MMC_GCTL_FIFO_RST | AW_MMC_GCTL_DMA_RST; 839b5be541fSEmmanuel Vadot val = AW_MMC_READ_4(sc, AW_MMC_GCTL); 840b5be541fSEmmanuel Vadot AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val | mask); 841b5be541fSEmmanuel Vadot 842b5be541fSEmmanuel Vadot retry = AW_MMC_RESET_RETRY; 843b5be541fSEmmanuel Vadot while (--retry > 0) { 844c39ea909SEmmanuel Vadot if ((AW_MMC_READ_4(sc, AW_MMC_GCTL) & 845c39ea909SEmmanuel Vadot AW_MMC_GCTL_RESET) == 0) 846b5be541fSEmmanuel Vadot break; 847c39ea909SEmmanuel Vadot DELAY(100); 848b5be541fSEmmanuel Vadot } 849b5be541fSEmmanuel Vadot if (retry == 0) 850b5be541fSEmmanuel Vadot device_printf(sc->aw_dev, 851b5be541fSEmmanuel Vadot "timeout resetting DMA/FIFO\n"); 852b5be541fSEmmanuel Vadot aw_mmc_update_clock(sc, 1); 853b5be541fSEmmanuel Vadot } 854b5be541fSEmmanuel Vadot 855b5be541fSEmmanuel Vadot callout_stop(&sc->aw_timeoutc); 856b5be541fSEmmanuel Vadot sc->aw_intr = 0; 857b5be541fSEmmanuel Vadot sc->aw_resid = 0; 858b5be541fSEmmanuel Vadot sc->aw_dma_map_err = 0; 859b5be541fSEmmanuel Vadot sc->aw_intr_wait = 0; 8605e03278fSIlya Bakulin #ifdef MMCCAM 8615e03278fSIlya Bakulin sc->ccb = NULL; 8625e03278fSIlya Bakulin ccb->ccb_h.status = 8635e03278fSIlya Bakulin (ccb->mmcio.cmd.error == 0 ? CAM_REQ_CMP : CAM_REQ_CMP_ERR); 8645e03278fSIlya Bakulin xpt_done(ccb); 8655e03278fSIlya Bakulin #else 8665e03278fSIlya Bakulin req = sc->aw_req; 8675e03278fSIlya Bakulin sc->aw_req = NULL; 868b5be541fSEmmanuel Vadot req->done(req); 8695e03278fSIlya Bakulin #endif 870b5be541fSEmmanuel Vadot } 871b5be541fSEmmanuel Vadot 872b5be541fSEmmanuel Vadot static void 873b5be541fSEmmanuel Vadot aw_mmc_req_ok(struct aw_mmc_softc *sc) 874b5be541fSEmmanuel Vadot { 875b5be541fSEmmanuel Vadot int timeout; 876b5be541fSEmmanuel Vadot struct mmc_command *cmd; 877b5be541fSEmmanuel Vadot uint32_t status; 878b5be541fSEmmanuel Vadot 879b5be541fSEmmanuel Vadot timeout = 1000; 880b5be541fSEmmanuel Vadot while (--timeout > 0) { 881b5be541fSEmmanuel Vadot status = AW_MMC_READ_4(sc, AW_MMC_STAR); 882b5be541fSEmmanuel Vadot if ((status & AW_MMC_STAR_CARD_BUSY) == 0) 883b5be541fSEmmanuel Vadot break; 884b5be541fSEmmanuel Vadot DELAY(1000); 885b5be541fSEmmanuel Vadot } 8865e03278fSIlya Bakulin #ifdef MMCCAM 8875e03278fSIlya Bakulin cmd = &sc->ccb->mmcio.cmd; 8885e03278fSIlya Bakulin #else 889b5be541fSEmmanuel Vadot cmd = sc->aw_req->cmd; 8905e03278fSIlya Bakulin #endif 891b5be541fSEmmanuel Vadot if (timeout == 0) { 892b5be541fSEmmanuel Vadot cmd->error = MMC_ERR_FAILED; 893b5be541fSEmmanuel Vadot aw_mmc_req_done(sc); 894b5be541fSEmmanuel Vadot return; 895b5be541fSEmmanuel Vadot } 896b5be541fSEmmanuel Vadot if (cmd->flags & MMC_RSP_PRESENT) { 897b5be541fSEmmanuel Vadot if (cmd->flags & MMC_RSP_136) { 898b5be541fSEmmanuel Vadot cmd->resp[0] = AW_MMC_READ_4(sc, AW_MMC_RESP3); 899b5be541fSEmmanuel Vadot cmd->resp[1] = AW_MMC_READ_4(sc, AW_MMC_RESP2); 900b5be541fSEmmanuel Vadot cmd->resp[2] = AW_MMC_READ_4(sc, AW_MMC_RESP1); 901b5be541fSEmmanuel Vadot cmd->resp[3] = AW_MMC_READ_4(sc, AW_MMC_RESP0); 902b5be541fSEmmanuel Vadot } else 903b5be541fSEmmanuel Vadot cmd->resp[0] = AW_MMC_READ_4(sc, AW_MMC_RESP0); 904b5be541fSEmmanuel Vadot } 905b5be541fSEmmanuel Vadot /* All data has been transferred ? */ 906b5be541fSEmmanuel Vadot if (cmd->data != NULL && (sc->aw_resid << 2) < cmd->data->len) 907b5be541fSEmmanuel Vadot cmd->error = MMC_ERR_FAILED; 908b5be541fSEmmanuel Vadot aw_mmc_req_done(sc); 909b5be541fSEmmanuel Vadot } 910b5be541fSEmmanuel Vadot 9115e03278fSIlya Bakulin 9125e03278fSIlya Bakulin static inline void 9135e03278fSIlya Bakulin set_mmc_error(struct aw_mmc_softc *sc, int error_code) 9145e03278fSIlya Bakulin { 9155e03278fSIlya Bakulin #ifdef MMCCAM 9165e03278fSIlya Bakulin sc->ccb->mmcio.cmd.error = error_code; 9175e03278fSIlya Bakulin #else 9185e03278fSIlya Bakulin sc->aw_req->cmd->error = error_code; 9195e03278fSIlya Bakulin #endif 9205e03278fSIlya Bakulin } 9215e03278fSIlya Bakulin 922b5be541fSEmmanuel Vadot static void 923b5be541fSEmmanuel Vadot aw_mmc_timeout(void *arg) 924b5be541fSEmmanuel Vadot { 925b5be541fSEmmanuel Vadot struct aw_mmc_softc *sc; 926b5be541fSEmmanuel Vadot 927b5be541fSEmmanuel Vadot sc = (struct aw_mmc_softc *)arg; 9285e03278fSIlya Bakulin #ifdef MMCCAM 9295e03278fSIlya Bakulin if (sc->ccb != NULL) { 9305e03278fSIlya Bakulin #else 931b5be541fSEmmanuel Vadot if (sc->aw_req != NULL) { 9325e03278fSIlya Bakulin #endif 933b5be541fSEmmanuel Vadot device_printf(sc->aw_dev, "controller timeout\n"); 9345e03278fSIlya Bakulin set_mmc_error(sc, MMC_ERR_TIMEOUT); 935b5be541fSEmmanuel Vadot aw_mmc_req_done(sc); 936b5be541fSEmmanuel Vadot } else 937b5be541fSEmmanuel Vadot device_printf(sc->aw_dev, 938b5be541fSEmmanuel Vadot "Spurious timeout - no active request\n"); 939b5be541fSEmmanuel Vadot } 940b5be541fSEmmanuel Vadot 941b5be541fSEmmanuel Vadot static void 9425e03278fSIlya Bakulin aw_mmc_print_error(uint32_t err) 9435e03278fSIlya Bakulin { 9445e03278fSIlya Bakulin if(err & AW_MMC_INT_RESP_ERR) 9455e03278fSIlya Bakulin printf("AW_MMC_INT_RESP_ERR "); 9465e03278fSIlya Bakulin if (err & AW_MMC_INT_RESP_CRC_ERR) 9475e03278fSIlya Bakulin printf("AW_MMC_INT_RESP_CRC_ERR "); 9485e03278fSIlya Bakulin if (err & AW_MMC_INT_DATA_CRC_ERR) 9495e03278fSIlya Bakulin printf("AW_MMC_INT_DATA_CRC_ERR "); 9505e03278fSIlya Bakulin if (err & AW_MMC_INT_RESP_TIMEOUT) 9515e03278fSIlya Bakulin printf("AW_MMC_INT_RESP_TIMEOUT "); 9525e03278fSIlya Bakulin if (err & AW_MMC_INT_FIFO_RUN_ERR) 9535e03278fSIlya Bakulin printf("AW_MMC_INT_FIFO_RUN_ERR "); 9545e03278fSIlya Bakulin if (err & AW_MMC_INT_CMD_BUSY) 9555e03278fSIlya Bakulin printf("AW_MMC_INT_CMD_BUSY "); 9565e03278fSIlya Bakulin if (err & AW_MMC_INT_DATA_START_ERR) 9575e03278fSIlya Bakulin printf("AW_MMC_INT_DATA_START_ERR "); 9585e03278fSIlya Bakulin if (err & AW_MMC_INT_DATA_END_BIT_ERR) 9595e03278fSIlya Bakulin printf("AW_MMC_INT_DATA_END_BIT_ERR"); 9605e03278fSIlya Bakulin printf("\n"); 9615e03278fSIlya Bakulin } 9625e03278fSIlya Bakulin 9635e03278fSIlya Bakulin static void 964b5be541fSEmmanuel Vadot aw_mmc_intr(void *arg) 965b5be541fSEmmanuel Vadot { 966b5be541fSEmmanuel Vadot bus_dmasync_op_t sync_op; 967b5be541fSEmmanuel Vadot struct aw_mmc_softc *sc; 968b5be541fSEmmanuel Vadot struct mmc_data *data; 969b5be541fSEmmanuel Vadot uint32_t idst, imask, rint; 970b5be541fSEmmanuel Vadot 971b5be541fSEmmanuel Vadot sc = (struct aw_mmc_softc *)arg; 972b5be541fSEmmanuel Vadot AW_MMC_LOCK(sc); 973b5be541fSEmmanuel Vadot rint = AW_MMC_READ_4(sc, AW_MMC_RISR); 974b5be541fSEmmanuel Vadot idst = AW_MMC_READ_4(sc, AW_MMC_IDST); 975b5be541fSEmmanuel Vadot imask = AW_MMC_READ_4(sc, AW_MMC_IMKR); 976b5be541fSEmmanuel Vadot if (idst == 0 && imask == 0 && rint == 0) { 977b5be541fSEmmanuel Vadot AW_MMC_UNLOCK(sc); 978b5be541fSEmmanuel Vadot return; 979b5be541fSEmmanuel Vadot } 980b5be541fSEmmanuel Vadot #ifdef DEBUG 981b5be541fSEmmanuel Vadot device_printf(sc->aw_dev, "idst: %#x, imask: %#x, rint: %#x\n", 982b5be541fSEmmanuel Vadot idst, imask, rint); 983b5be541fSEmmanuel Vadot #endif 9845e03278fSIlya Bakulin #ifdef MMCCAM 9855e03278fSIlya Bakulin if (sc->ccb == NULL) { 9865e03278fSIlya Bakulin #else 987b5be541fSEmmanuel Vadot if (sc->aw_req == NULL) { 9885e03278fSIlya Bakulin #endif 989b5be541fSEmmanuel Vadot device_printf(sc->aw_dev, 990b5be541fSEmmanuel Vadot "Spurious interrupt - no active request, rint: 0x%08X\n", 991b5be541fSEmmanuel Vadot rint); 9925e03278fSIlya Bakulin aw_mmc_print_error(rint); 993b5be541fSEmmanuel Vadot goto end; 994b5be541fSEmmanuel Vadot } 995b5be541fSEmmanuel Vadot if (rint & AW_MMC_INT_ERR_BIT) { 996ce0618beSEmmanuel Vadot if (bootverbose) 997b5be541fSEmmanuel Vadot device_printf(sc->aw_dev, "error rint: 0x%08X\n", rint); 9985e03278fSIlya Bakulin aw_mmc_print_error(rint); 999b5be541fSEmmanuel Vadot if (rint & AW_MMC_INT_RESP_TIMEOUT) 10005e03278fSIlya Bakulin set_mmc_error(sc, MMC_ERR_TIMEOUT); 1001b5be541fSEmmanuel Vadot else 10025e03278fSIlya Bakulin set_mmc_error(sc, MMC_ERR_FAILED); 1003b5be541fSEmmanuel Vadot aw_mmc_req_done(sc); 1004b5be541fSEmmanuel Vadot goto end; 1005b5be541fSEmmanuel Vadot } 1006b5be541fSEmmanuel Vadot if (idst & AW_MMC_IDST_ERROR) { 1007b5be541fSEmmanuel Vadot device_printf(sc->aw_dev, "error idst: 0x%08x\n", idst); 10085e03278fSIlya Bakulin set_mmc_error(sc, MMC_ERR_FAILED); 1009b5be541fSEmmanuel Vadot aw_mmc_req_done(sc); 1010b5be541fSEmmanuel Vadot goto end; 1011b5be541fSEmmanuel Vadot } 1012b5be541fSEmmanuel Vadot 1013b5be541fSEmmanuel Vadot sc->aw_intr |= rint; 10145e03278fSIlya Bakulin #ifdef MMCCAM 10155e03278fSIlya Bakulin data = sc->ccb->mmcio.cmd.data; 10165e03278fSIlya Bakulin #else 1017b5be541fSEmmanuel Vadot data = sc->aw_req->cmd->data; 10185e03278fSIlya Bakulin #endif 1019b5be541fSEmmanuel Vadot if (data != NULL && (idst & AW_MMC_IDST_COMPLETE) != 0) { 1020b5be541fSEmmanuel Vadot if (data->flags & MMC_DATA_WRITE) 1021b5be541fSEmmanuel Vadot sync_op = BUS_DMASYNC_POSTWRITE; 1022b5be541fSEmmanuel Vadot else 1023b5be541fSEmmanuel Vadot sync_op = BUS_DMASYNC_POSTREAD; 1024b5be541fSEmmanuel Vadot bus_dmamap_sync(sc->aw_dma_buf_tag, sc->aw_dma_buf_map, 1025b5be541fSEmmanuel Vadot sync_op); 1026b5be541fSEmmanuel Vadot bus_dmamap_sync(sc->aw_dma_tag, sc->aw_dma_map, 1027b5be541fSEmmanuel Vadot BUS_DMASYNC_POSTWRITE); 1028b5be541fSEmmanuel Vadot bus_dmamap_unload(sc->aw_dma_buf_tag, sc->aw_dma_buf_map); 1029b5be541fSEmmanuel Vadot sc->aw_resid = data->len >> 2; 1030b5be541fSEmmanuel Vadot } 1031b5be541fSEmmanuel Vadot if ((sc->aw_intr & sc->aw_intr_wait) == sc->aw_intr_wait) 1032b5be541fSEmmanuel Vadot aw_mmc_req_ok(sc); 1033b5be541fSEmmanuel Vadot 1034b5be541fSEmmanuel Vadot end: 1035b5be541fSEmmanuel Vadot AW_MMC_WRITE_4(sc, AW_MMC_IDST, idst); 1036b5be541fSEmmanuel Vadot AW_MMC_WRITE_4(sc, AW_MMC_RISR, rint); 1037b5be541fSEmmanuel Vadot AW_MMC_UNLOCK(sc); 1038b5be541fSEmmanuel Vadot } 1039b5be541fSEmmanuel Vadot 1040b5be541fSEmmanuel Vadot static int 1041b5be541fSEmmanuel Vadot aw_mmc_request(device_t bus, device_t child, struct mmc_request *req) 1042b5be541fSEmmanuel Vadot { 1043b5be541fSEmmanuel Vadot int blksz; 1044b5be541fSEmmanuel Vadot struct aw_mmc_softc *sc; 1045b5be541fSEmmanuel Vadot struct mmc_command *cmd; 104635a18619SEmmanuel Vadot uint32_t cmdreg, imask; 1047b5be541fSEmmanuel Vadot int err; 1048b5be541fSEmmanuel Vadot 1049b5be541fSEmmanuel Vadot sc = device_get_softc(bus); 1050c39ea909SEmmanuel Vadot 1051b5be541fSEmmanuel Vadot AW_MMC_LOCK(sc); 10525e03278fSIlya Bakulin #ifdef MMCCAM 10535e03278fSIlya Bakulin KASSERT(req == NULL, ("req should be NULL in MMCCAM case!")); 10545e03278fSIlya Bakulin /* 10555e03278fSIlya Bakulin * For MMCCAM, sc->ccb has been NULL-checked and populated 10565e03278fSIlya Bakulin * by aw_mmc_cam_request() already. 10575e03278fSIlya Bakulin */ 10585e03278fSIlya Bakulin cmd = &sc->ccb->mmcio.cmd; 10595e03278fSIlya Bakulin #else 1060b5be541fSEmmanuel Vadot if (sc->aw_req) { 1061b5be541fSEmmanuel Vadot AW_MMC_UNLOCK(sc); 1062b5be541fSEmmanuel Vadot return (EBUSY); 1063b5be541fSEmmanuel Vadot } 1064b5be541fSEmmanuel Vadot sc->aw_req = req; 1065b5be541fSEmmanuel Vadot cmd = req->cmd; 10665e03278fSIlya Bakulin 10675e03278fSIlya Bakulin #ifdef DEBUG 10685e03278fSIlya Bakulin if (bootverbose) 10695e03278fSIlya Bakulin device_printf(sc->aw_dev, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 10705e03278fSIlya Bakulin cmd->opcode, cmd->arg, cmd->flags, 10715e03278fSIlya Bakulin cmd->data != NULL ? (unsigned int)cmd->data->len : 0, 10725e03278fSIlya Bakulin cmd->data != NULL ? cmd->data->flags: 0); 10735e03278fSIlya Bakulin #endif 10745e03278fSIlya Bakulin #endif 1075b5be541fSEmmanuel Vadot cmdreg = AW_MMC_CMDR_LOAD; 107635a18619SEmmanuel Vadot imask = AW_MMC_INT_ERR_BIT; 107735a18619SEmmanuel Vadot sc->aw_intr_wait = 0; 107835a18619SEmmanuel Vadot sc->aw_intr = 0; 107935a18619SEmmanuel Vadot sc->aw_resid = 0; 108035a18619SEmmanuel Vadot cmd->error = MMC_ERR_NONE; 108135a18619SEmmanuel Vadot 1082b5be541fSEmmanuel Vadot if (cmd->opcode == MMC_GO_IDLE_STATE) 1083b5be541fSEmmanuel Vadot cmdreg |= AW_MMC_CMDR_SEND_INIT_SEQ; 108435a18619SEmmanuel Vadot 1085b5be541fSEmmanuel Vadot if (cmd->flags & MMC_RSP_PRESENT) 1086b5be541fSEmmanuel Vadot cmdreg |= AW_MMC_CMDR_RESP_RCV; 1087b5be541fSEmmanuel Vadot if (cmd->flags & MMC_RSP_136) 1088b5be541fSEmmanuel Vadot cmdreg |= AW_MMC_CMDR_LONG_RESP; 1089b5be541fSEmmanuel Vadot if (cmd->flags & MMC_RSP_CRC) 1090b5be541fSEmmanuel Vadot cmdreg |= AW_MMC_CMDR_CHK_RESP_CRC; 1091b5be541fSEmmanuel Vadot 109235a18619SEmmanuel Vadot if (cmd->data) { 1093b5be541fSEmmanuel Vadot cmdreg |= AW_MMC_CMDR_DATA_TRANS | AW_MMC_CMDR_WAIT_PRE_OVER; 109435a18619SEmmanuel Vadot 1095b5be541fSEmmanuel Vadot if (cmd->data->flags & MMC_DATA_MULTI) { 1096b5be541fSEmmanuel Vadot cmdreg |= AW_MMC_CMDR_STOP_CMD_FLAG; 109735a18619SEmmanuel Vadot imask |= AW_MMC_INT_AUTO_STOP_DONE; 1098b5be541fSEmmanuel Vadot sc->aw_intr_wait |= AW_MMC_INT_AUTO_STOP_DONE; 109935a18619SEmmanuel Vadot } else { 110035a18619SEmmanuel Vadot sc->aw_intr_wait |= AW_MMC_INT_DATA_OVER; 110135a18619SEmmanuel Vadot imask |= AW_MMC_INT_DATA_OVER; 1102b5be541fSEmmanuel Vadot } 1103b5be541fSEmmanuel Vadot if (cmd->data->flags & MMC_DATA_WRITE) 1104b5be541fSEmmanuel Vadot cmdreg |= AW_MMC_CMDR_DIR_WRITE; 110535a18619SEmmanuel Vadot 1106b5be541fSEmmanuel Vadot blksz = min(cmd->data->len, MMC_SECTOR_SIZE); 1107b5be541fSEmmanuel Vadot AW_MMC_WRITE_4(sc, AW_MMC_BKSR, blksz); 1108b5be541fSEmmanuel Vadot AW_MMC_WRITE_4(sc, AW_MMC_BYCR, cmd->data->len); 110935a18619SEmmanuel Vadot } else { 111035a18619SEmmanuel Vadot imask |= AW_MMC_INT_CMD_DONE; 111135a18619SEmmanuel Vadot } 1112b5be541fSEmmanuel Vadot 111335a18619SEmmanuel Vadot /* Enable the interrupts we are interested in */ 111435a18619SEmmanuel Vadot AW_MMC_WRITE_4(sc, AW_MMC_IMKR, imask); 111535a18619SEmmanuel Vadot AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff); 111635a18619SEmmanuel Vadot 111735a18619SEmmanuel Vadot /* Enable auto stop if needed */ 111835a18619SEmmanuel Vadot AW_MMC_WRITE_4(sc, AW_MMC_A12A, 111935a18619SEmmanuel Vadot cmdreg & AW_MMC_CMDR_STOP_CMD_FLAG ? 0 : 0xffff); 112035a18619SEmmanuel Vadot 112135a18619SEmmanuel Vadot /* Write the command argument */ 112235a18619SEmmanuel Vadot AW_MMC_WRITE_4(sc, AW_MMC_CAGR, cmd->arg); 112335a18619SEmmanuel Vadot 112435a18619SEmmanuel Vadot /* 112535a18619SEmmanuel Vadot * If we don't have data start the request 112635a18619SEmmanuel Vadot * if we do prepare the dma request and start the request 112735a18619SEmmanuel Vadot */ 112835a18619SEmmanuel Vadot if (cmd->data == NULL) { 112935a18619SEmmanuel Vadot AW_MMC_WRITE_4(sc, AW_MMC_CMDR, cmdreg | cmd->opcode); 113035a18619SEmmanuel Vadot } else { 1131b5be541fSEmmanuel Vadot err = aw_mmc_prepare_dma(sc); 1132b5be541fSEmmanuel Vadot if (err != 0) 1133b5be541fSEmmanuel Vadot device_printf(sc->aw_dev, "prepare_dma failed: %d\n", err); 113435a18619SEmmanuel Vadot 113535a18619SEmmanuel Vadot AW_MMC_WRITE_4(sc, AW_MMC_CMDR, cmdreg | cmd->opcode); 1136b5be541fSEmmanuel Vadot } 1137b5be541fSEmmanuel Vadot 1138b5be541fSEmmanuel Vadot callout_reset(&sc->aw_timeoutc, sc->aw_timeout * hz, 1139b5be541fSEmmanuel Vadot aw_mmc_timeout, sc); 1140b5be541fSEmmanuel Vadot AW_MMC_UNLOCK(sc); 1141b5be541fSEmmanuel Vadot 1142b5be541fSEmmanuel Vadot return (0); 1143b5be541fSEmmanuel Vadot } 1144b5be541fSEmmanuel Vadot 1145b5be541fSEmmanuel Vadot static int 1146b5be541fSEmmanuel Vadot aw_mmc_read_ivar(device_t bus, device_t child, int which, 1147b5be541fSEmmanuel Vadot uintptr_t *result) 1148b5be541fSEmmanuel Vadot { 1149b5be541fSEmmanuel Vadot struct aw_mmc_softc *sc; 1150b5be541fSEmmanuel Vadot 1151b5be541fSEmmanuel Vadot sc = device_get_softc(bus); 1152b5be541fSEmmanuel Vadot switch (which) { 1153b5be541fSEmmanuel Vadot default: 1154b5be541fSEmmanuel Vadot return (EINVAL); 1155b5be541fSEmmanuel Vadot case MMCBR_IVAR_BUS_MODE: 1156b5be541fSEmmanuel Vadot *(int *)result = sc->aw_host.ios.bus_mode; 1157b5be541fSEmmanuel Vadot break; 1158b5be541fSEmmanuel Vadot case MMCBR_IVAR_BUS_WIDTH: 1159b5be541fSEmmanuel Vadot *(int *)result = sc->aw_host.ios.bus_width; 1160b5be541fSEmmanuel Vadot break; 1161b5be541fSEmmanuel Vadot case MMCBR_IVAR_CHIP_SELECT: 1162b5be541fSEmmanuel Vadot *(int *)result = sc->aw_host.ios.chip_select; 1163b5be541fSEmmanuel Vadot break; 1164b5be541fSEmmanuel Vadot case MMCBR_IVAR_CLOCK: 1165b5be541fSEmmanuel Vadot *(int *)result = sc->aw_host.ios.clock; 1166b5be541fSEmmanuel Vadot break; 1167b5be541fSEmmanuel Vadot case MMCBR_IVAR_F_MIN: 1168b5be541fSEmmanuel Vadot *(int *)result = sc->aw_host.f_min; 1169b5be541fSEmmanuel Vadot break; 1170b5be541fSEmmanuel Vadot case MMCBR_IVAR_F_MAX: 1171b5be541fSEmmanuel Vadot *(int *)result = sc->aw_host.f_max; 1172b5be541fSEmmanuel Vadot break; 1173b5be541fSEmmanuel Vadot case MMCBR_IVAR_HOST_OCR: 1174b5be541fSEmmanuel Vadot *(int *)result = sc->aw_host.host_ocr; 1175b5be541fSEmmanuel Vadot break; 1176b5be541fSEmmanuel Vadot case MMCBR_IVAR_MODE: 1177b5be541fSEmmanuel Vadot *(int *)result = sc->aw_host.mode; 1178b5be541fSEmmanuel Vadot break; 1179b5be541fSEmmanuel Vadot case MMCBR_IVAR_OCR: 1180b5be541fSEmmanuel Vadot *(int *)result = sc->aw_host.ocr; 1181b5be541fSEmmanuel Vadot break; 1182b5be541fSEmmanuel Vadot case MMCBR_IVAR_POWER_MODE: 1183b5be541fSEmmanuel Vadot *(int *)result = sc->aw_host.ios.power_mode; 1184b5be541fSEmmanuel Vadot break; 1185b5be541fSEmmanuel Vadot case MMCBR_IVAR_VDD: 1186b5be541fSEmmanuel Vadot *(int *)result = sc->aw_host.ios.vdd; 1187b5be541fSEmmanuel Vadot break; 1188dfb8c122SEmmanuel Vadot case MMCBR_IVAR_VCCQ: 1189dfb8c122SEmmanuel Vadot *(int *)result = sc->aw_host.ios.vccq; 1190dfb8c122SEmmanuel Vadot break; 1191b5be541fSEmmanuel Vadot case MMCBR_IVAR_CAPS: 1192b5be541fSEmmanuel Vadot *(int *)result = sc->aw_host.caps; 1193b5be541fSEmmanuel Vadot break; 1194ce0618beSEmmanuel Vadot case MMCBR_IVAR_TIMING: 1195ce0618beSEmmanuel Vadot *(int *)result = sc->aw_host.ios.timing; 1196ce0618beSEmmanuel Vadot break; 1197b5be541fSEmmanuel Vadot case MMCBR_IVAR_MAX_DATA: 1198c39ea909SEmmanuel Vadot *(int *)result = (sc->aw_mmc_conf->dma_xferlen * 1199c39ea909SEmmanuel Vadot AW_MMC_DMA_SEGS) / MMC_SECTOR_SIZE; 1200b5be541fSEmmanuel Vadot break; 1201*55f3f71cSEmmanuel Vadot case MMCBR_IVAR_RETUNE_REQ: 1202*55f3f71cSEmmanuel Vadot *(int *)result = retune_req_none; 1203*55f3f71cSEmmanuel Vadot break; 1204b5be541fSEmmanuel Vadot } 1205b5be541fSEmmanuel Vadot 1206b5be541fSEmmanuel Vadot return (0); 1207b5be541fSEmmanuel Vadot } 1208b5be541fSEmmanuel Vadot 1209b5be541fSEmmanuel Vadot static int 1210b5be541fSEmmanuel Vadot aw_mmc_write_ivar(device_t bus, device_t child, int which, 1211b5be541fSEmmanuel Vadot uintptr_t value) 1212b5be541fSEmmanuel Vadot { 1213b5be541fSEmmanuel Vadot struct aw_mmc_softc *sc; 1214b5be541fSEmmanuel Vadot 1215b5be541fSEmmanuel Vadot sc = device_get_softc(bus); 1216b5be541fSEmmanuel Vadot switch (which) { 1217b5be541fSEmmanuel Vadot default: 1218b5be541fSEmmanuel Vadot return (EINVAL); 1219b5be541fSEmmanuel Vadot case MMCBR_IVAR_BUS_MODE: 1220b5be541fSEmmanuel Vadot sc->aw_host.ios.bus_mode = value; 1221b5be541fSEmmanuel Vadot break; 1222b5be541fSEmmanuel Vadot case MMCBR_IVAR_BUS_WIDTH: 1223b5be541fSEmmanuel Vadot sc->aw_host.ios.bus_width = value; 1224b5be541fSEmmanuel Vadot break; 1225b5be541fSEmmanuel Vadot case MMCBR_IVAR_CHIP_SELECT: 1226b5be541fSEmmanuel Vadot sc->aw_host.ios.chip_select = value; 1227b5be541fSEmmanuel Vadot break; 1228b5be541fSEmmanuel Vadot case MMCBR_IVAR_CLOCK: 1229b5be541fSEmmanuel Vadot sc->aw_host.ios.clock = value; 1230b5be541fSEmmanuel Vadot break; 1231b5be541fSEmmanuel Vadot case MMCBR_IVAR_MODE: 1232b5be541fSEmmanuel Vadot sc->aw_host.mode = value; 1233b5be541fSEmmanuel Vadot break; 1234b5be541fSEmmanuel Vadot case MMCBR_IVAR_OCR: 1235b5be541fSEmmanuel Vadot sc->aw_host.ocr = value; 1236b5be541fSEmmanuel Vadot break; 1237b5be541fSEmmanuel Vadot case MMCBR_IVAR_POWER_MODE: 1238b5be541fSEmmanuel Vadot sc->aw_host.ios.power_mode = value; 1239b5be541fSEmmanuel Vadot break; 1240b5be541fSEmmanuel Vadot case MMCBR_IVAR_VDD: 1241b5be541fSEmmanuel Vadot sc->aw_host.ios.vdd = value; 1242b5be541fSEmmanuel Vadot break; 1243dfb8c122SEmmanuel Vadot case MMCBR_IVAR_VCCQ: 1244dfb8c122SEmmanuel Vadot sc->aw_host.ios.vccq = value; 1245dfb8c122SEmmanuel Vadot break; 1246ce0618beSEmmanuel Vadot case MMCBR_IVAR_TIMING: 1247ce0618beSEmmanuel Vadot sc->aw_host.ios.timing = value; 1248ce0618beSEmmanuel Vadot break; 1249b5be541fSEmmanuel Vadot /* These are read-only */ 1250b5be541fSEmmanuel Vadot case MMCBR_IVAR_CAPS: 1251b5be541fSEmmanuel Vadot case MMCBR_IVAR_HOST_OCR: 1252b5be541fSEmmanuel Vadot case MMCBR_IVAR_F_MIN: 1253b5be541fSEmmanuel Vadot case MMCBR_IVAR_F_MAX: 1254b5be541fSEmmanuel Vadot case MMCBR_IVAR_MAX_DATA: 1255b5be541fSEmmanuel Vadot return (EINVAL); 1256b5be541fSEmmanuel Vadot } 1257b5be541fSEmmanuel Vadot 1258b5be541fSEmmanuel Vadot return (0); 1259b5be541fSEmmanuel Vadot } 1260b5be541fSEmmanuel Vadot 1261b5be541fSEmmanuel Vadot static int 1262b5be541fSEmmanuel Vadot aw_mmc_update_clock(struct aw_mmc_softc *sc, uint32_t clkon) 1263b5be541fSEmmanuel Vadot { 1264ce0618beSEmmanuel Vadot uint32_t reg; 1265b5be541fSEmmanuel Vadot int retry; 1266b5be541fSEmmanuel Vadot 1267ce0618beSEmmanuel Vadot reg = AW_MMC_READ_4(sc, AW_MMC_CKCR); 1268ffdb1aa8SEmmanuel Vadot reg &= ~(AW_MMC_CKCR_ENB | AW_MMC_CKCR_LOW_POWER | 1269ffdb1aa8SEmmanuel Vadot AW_MMC_CKCR_MASK_DATA0); 1270b5be541fSEmmanuel Vadot 1271b5be541fSEmmanuel Vadot if (clkon) 1272ffdb1aa8SEmmanuel Vadot reg |= AW_MMC_CKCR_ENB; 1273ce0618beSEmmanuel Vadot if (sc->aw_mmc_conf->mask_data0) 1274ffdb1aa8SEmmanuel Vadot reg |= AW_MMC_CKCR_MASK_DATA0; 1275b5be541fSEmmanuel Vadot 1276ce0618beSEmmanuel Vadot AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg); 1277b5be541fSEmmanuel Vadot 1278ce0618beSEmmanuel Vadot reg = AW_MMC_CMDR_LOAD | AW_MMC_CMDR_PRG_CLK | 1279b5be541fSEmmanuel Vadot AW_MMC_CMDR_WAIT_PRE_OVER; 1280ce0618beSEmmanuel Vadot AW_MMC_WRITE_4(sc, AW_MMC_CMDR, reg); 1281b5be541fSEmmanuel Vadot retry = 0xfffff; 1282ce0618beSEmmanuel Vadot 1283ce0618beSEmmanuel Vadot while (reg & AW_MMC_CMDR_LOAD && --retry > 0) { 1284ce0618beSEmmanuel Vadot reg = AW_MMC_READ_4(sc, AW_MMC_CMDR); 1285b5be541fSEmmanuel Vadot DELAY(10); 1286b5be541fSEmmanuel Vadot } 1287b5be541fSEmmanuel Vadot AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff); 1288b5be541fSEmmanuel Vadot 1289ce0618beSEmmanuel Vadot if (reg & AW_MMC_CMDR_LOAD) { 1290ce0618beSEmmanuel Vadot device_printf(sc->aw_dev, "timeout updating clock\n"); 1291b5be541fSEmmanuel Vadot return (ETIMEDOUT); 1292b5be541fSEmmanuel Vadot } 1293b5be541fSEmmanuel Vadot 1294ce0618beSEmmanuel Vadot if (sc->aw_mmc_conf->mask_data0) { 1295ce0618beSEmmanuel Vadot reg = AW_MMC_READ_4(sc, AW_MMC_CKCR); 1296ffdb1aa8SEmmanuel Vadot reg &= ~AW_MMC_CKCR_MASK_DATA0; 1297ce0618beSEmmanuel Vadot AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg); 1298ce0618beSEmmanuel Vadot } 1299ce0618beSEmmanuel Vadot 1300ce0618beSEmmanuel Vadot return (0); 1301ce0618beSEmmanuel Vadot } 1302ce0618beSEmmanuel Vadot 1303623966e1SEmmanuel Vadot static int 1304623966e1SEmmanuel Vadot aw_mmc_switch_vccq(device_t bus, device_t child) 1305ce0618beSEmmanuel Vadot { 1306623966e1SEmmanuel Vadot struct aw_mmc_softc *sc; 1307623966e1SEmmanuel Vadot int uvolt, err; 1308623966e1SEmmanuel Vadot 1309623966e1SEmmanuel Vadot sc = device_get_softc(bus); 1310ce0618beSEmmanuel Vadot 13113177f7cdSEmmanuel Vadot if (sc->aw_reg_vqmmc == NULL) 1312623966e1SEmmanuel Vadot return EOPNOTSUPP; 1313ce0618beSEmmanuel Vadot 1314623966e1SEmmanuel Vadot switch (sc->aw_host.ios.vccq) { 1315dfb8c122SEmmanuel Vadot case vccq_180: 1316dfb8c122SEmmanuel Vadot uvolt = 1800000; 1317ce0618beSEmmanuel Vadot break; 1318dfb8c122SEmmanuel Vadot case vccq_330: 1319dfb8c122SEmmanuel Vadot uvolt = 3300000; 1320ce0618beSEmmanuel Vadot break; 1321dfb8c122SEmmanuel Vadot default: 1322623966e1SEmmanuel Vadot return EINVAL; 1323ce0618beSEmmanuel Vadot } 1324ce0618beSEmmanuel Vadot 1325623966e1SEmmanuel Vadot err = regulator_set_voltage(sc->aw_reg_vqmmc, uvolt, uvolt); 1326623966e1SEmmanuel Vadot if (err != 0) { 1327ce0618beSEmmanuel Vadot device_printf(sc->aw_dev, 1328ce0618beSEmmanuel Vadot "Cannot set vqmmc to %d<->%d\n", 1329dfb8c122SEmmanuel Vadot uvolt, 1330dfb8c122SEmmanuel Vadot uvolt); 1331623966e1SEmmanuel Vadot return (err); 1332623966e1SEmmanuel Vadot } 1333623966e1SEmmanuel Vadot 1334623966e1SEmmanuel Vadot return (0); 1335ce0618beSEmmanuel Vadot } 1336ce0618beSEmmanuel Vadot 1337b5be541fSEmmanuel Vadot static int 1338b5be541fSEmmanuel Vadot aw_mmc_update_ios(device_t bus, device_t child) 1339b5be541fSEmmanuel Vadot { 1340b5be541fSEmmanuel Vadot int error; 1341b5be541fSEmmanuel Vadot struct aw_mmc_softc *sc; 1342b5be541fSEmmanuel Vadot struct mmc_ios *ios; 1343ce0618beSEmmanuel Vadot unsigned int clock; 1344ce0618beSEmmanuel Vadot uint32_t reg, div = 1; 1345b5be541fSEmmanuel Vadot 1346b5be541fSEmmanuel Vadot sc = device_get_softc(bus); 1347b5be541fSEmmanuel Vadot 1348b5be541fSEmmanuel Vadot ios = &sc->aw_host.ios; 1349b5be541fSEmmanuel Vadot 1350b5be541fSEmmanuel Vadot /* Set the bus width. */ 1351b5be541fSEmmanuel Vadot switch (ios->bus_width) { 1352b5be541fSEmmanuel Vadot case bus_width_1: 1353b5be541fSEmmanuel Vadot AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR1); 1354b5be541fSEmmanuel Vadot break; 1355b5be541fSEmmanuel Vadot case bus_width_4: 1356b5be541fSEmmanuel Vadot AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR4); 1357b5be541fSEmmanuel Vadot break; 1358b5be541fSEmmanuel Vadot case bus_width_8: 1359b5be541fSEmmanuel Vadot AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR8); 1360b5be541fSEmmanuel Vadot break; 1361b5be541fSEmmanuel Vadot } 1362b5be541fSEmmanuel Vadot 136335a18619SEmmanuel Vadot switch (ios->power_mode) { 136435a18619SEmmanuel Vadot case power_on: 136535a18619SEmmanuel Vadot break; 136635a18619SEmmanuel Vadot case power_off: 1367ce0618beSEmmanuel Vadot if (bootverbose) 1368ce0618beSEmmanuel Vadot device_printf(sc->aw_dev, "Powering down sd/mmc\n"); 1369dfb8c122SEmmanuel Vadot 1370dfb8c122SEmmanuel Vadot if (sc->aw_reg_vmmc) 1371dfb8c122SEmmanuel Vadot regulator_disable(sc->aw_reg_vmmc); 1372dfb8c122SEmmanuel Vadot if (sc->aw_reg_vqmmc) 1373dfb8c122SEmmanuel Vadot regulator_disable(sc->aw_reg_vqmmc); 1374dfb8c122SEmmanuel Vadot 137535a18619SEmmanuel Vadot aw_mmc_reset(sc); 137635a18619SEmmanuel Vadot break; 137735a18619SEmmanuel Vadot case power_up: 137835a18619SEmmanuel Vadot if (bootverbose) 137935a18619SEmmanuel Vadot device_printf(sc->aw_dev, "Powering up sd/mmc\n"); 1380dfb8c122SEmmanuel Vadot 1381dfb8c122SEmmanuel Vadot if (sc->aw_reg_vmmc) 1382dfb8c122SEmmanuel Vadot regulator_enable(sc->aw_reg_vmmc); 1383dfb8c122SEmmanuel Vadot if (sc->aw_reg_vqmmc) 1384dfb8c122SEmmanuel Vadot regulator_enable(sc->aw_reg_vqmmc); 138535a18619SEmmanuel Vadot aw_mmc_init(sc); 138635a18619SEmmanuel Vadot break; 138735a18619SEmmanuel Vadot }; 1388ce0618beSEmmanuel Vadot 1389ce0618beSEmmanuel Vadot /* Enable ddr mode if needed */ 1390ce0618beSEmmanuel Vadot reg = AW_MMC_READ_4(sc, AW_MMC_GCTL); 1391ce0618beSEmmanuel Vadot if (ios->timing == bus_timing_uhs_ddr50 || 1392ce0618beSEmmanuel Vadot ios->timing == bus_timing_mmc_ddr52) 1393b091392eSEmmanuel Vadot reg |= AW_MMC_GCTL_DDR_MOD_SEL; 1394ce0618beSEmmanuel Vadot else 1395b091392eSEmmanuel Vadot reg &= ~AW_MMC_GCTL_DDR_MOD_SEL; 1396ce0618beSEmmanuel Vadot AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg); 1397ce0618beSEmmanuel Vadot 13980f7a6420SEmmanuel Vadot if (ios->clock && ios->clock != sc->aw_clock) { 13990f7a6420SEmmanuel Vadot sc->aw_clock = clock = ios->clock; 1400b5be541fSEmmanuel Vadot 1401b5be541fSEmmanuel Vadot /* Disable clock */ 1402b5be541fSEmmanuel Vadot error = aw_mmc_update_clock(sc, 0); 1403b5be541fSEmmanuel Vadot if (error != 0) 1404b5be541fSEmmanuel Vadot return (error); 1405b5be541fSEmmanuel Vadot 1406ce0618beSEmmanuel Vadot if (ios->timing == bus_timing_mmc_ddr52 && 1407ce0618beSEmmanuel Vadot (sc->aw_mmc_conf->new_timing || 1408ce0618beSEmmanuel Vadot ios->bus_width == bus_width_8)) { 1409ce0618beSEmmanuel Vadot div = 2; 1410ce0618beSEmmanuel Vadot clock <<= 1; 1411ce0618beSEmmanuel Vadot } 1412ce0618beSEmmanuel Vadot 1413b5be541fSEmmanuel Vadot /* Reset the divider. */ 1414ce0618beSEmmanuel Vadot reg = AW_MMC_READ_4(sc, AW_MMC_CKCR); 1415ffdb1aa8SEmmanuel Vadot reg &= ~AW_MMC_CKCR_DIV; 1416ce0618beSEmmanuel Vadot reg |= div - 1; 1417ce0618beSEmmanuel Vadot AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg); 1418ce0618beSEmmanuel Vadot 1419ce0618beSEmmanuel Vadot /* New timing mode if needed */ 1420ce0618beSEmmanuel Vadot if (sc->aw_mmc_conf->new_timing) { 1421ce0618beSEmmanuel Vadot reg = AW_MMC_READ_4(sc, AW_MMC_NTSR); 1422ce0618beSEmmanuel Vadot reg |= AW_MMC_NTSR_MODE_SELECT; 1423ce0618beSEmmanuel Vadot AW_MMC_WRITE_4(sc, AW_MMC_NTSR, reg); 1424ce0618beSEmmanuel Vadot } 1425b5be541fSEmmanuel Vadot 1426b5be541fSEmmanuel Vadot /* Set the MMC clock. */ 1427ce0618beSEmmanuel Vadot error = clk_set_freq(sc->aw_clk_mmc, clock, 1428b5be541fSEmmanuel Vadot CLK_SET_ROUND_DOWN); 1429b5be541fSEmmanuel Vadot if (error != 0) { 1430b5be541fSEmmanuel Vadot device_printf(sc->aw_dev, 1431b5be541fSEmmanuel Vadot "failed to set frequency to %u Hz: %d\n", 1432ce0618beSEmmanuel Vadot clock, error); 1433b5be541fSEmmanuel Vadot return (error); 1434b5be541fSEmmanuel Vadot } 1435b5be541fSEmmanuel Vadot 1436ce0618beSEmmanuel Vadot if (sc->aw_mmc_conf->can_calibrate) 1437ce0618beSEmmanuel Vadot AW_MMC_WRITE_4(sc, AW_MMC_SAMP_DL, AW_MMC_SAMP_DL_SW_EN); 1438ce0618beSEmmanuel Vadot 1439b5be541fSEmmanuel Vadot /* Enable clock. */ 1440b5be541fSEmmanuel Vadot error = aw_mmc_update_clock(sc, 1); 1441b5be541fSEmmanuel Vadot if (error != 0) 1442b5be541fSEmmanuel Vadot return (error); 1443b5be541fSEmmanuel Vadot } 1444b5be541fSEmmanuel Vadot 1445b5be541fSEmmanuel Vadot 1446b5be541fSEmmanuel Vadot return (0); 1447b5be541fSEmmanuel Vadot } 1448b5be541fSEmmanuel Vadot 1449b5be541fSEmmanuel Vadot static int 1450b5be541fSEmmanuel Vadot aw_mmc_get_ro(device_t bus, device_t child) 1451b5be541fSEmmanuel Vadot { 1452b5be541fSEmmanuel Vadot 1453b5be541fSEmmanuel Vadot return (0); 1454b5be541fSEmmanuel Vadot } 1455b5be541fSEmmanuel Vadot 1456b5be541fSEmmanuel Vadot static int 1457b5be541fSEmmanuel Vadot aw_mmc_acquire_host(device_t bus, device_t child) 1458b5be541fSEmmanuel Vadot { 1459b5be541fSEmmanuel Vadot struct aw_mmc_softc *sc; 1460b5be541fSEmmanuel Vadot int error; 1461b5be541fSEmmanuel Vadot 1462b5be541fSEmmanuel Vadot sc = device_get_softc(bus); 1463b5be541fSEmmanuel Vadot AW_MMC_LOCK(sc); 1464b5be541fSEmmanuel Vadot while (sc->aw_bus_busy) { 1465b5be541fSEmmanuel Vadot error = msleep(sc, &sc->aw_mtx, PCATCH, "mmchw", 0); 1466b5be541fSEmmanuel Vadot if (error != 0) { 1467b5be541fSEmmanuel Vadot AW_MMC_UNLOCK(sc); 1468b5be541fSEmmanuel Vadot return (error); 1469b5be541fSEmmanuel Vadot } 1470b5be541fSEmmanuel Vadot } 1471b5be541fSEmmanuel Vadot sc->aw_bus_busy++; 1472b5be541fSEmmanuel Vadot AW_MMC_UNLOCK(sc); 1473b5be541fSEmmanuel Vadot 1474b5be541fSEmmanuel Vadot return (0); 1475b5be541fSEmmanuel Vadot } 1476b5be541fSEmmanuel Vadot 1477b5be541fSEmmanuel Vadot static int 1478b5be541fSEmmanuel Vadot aw_mmc_release_host(device_t bus, device_t child) 1479b5be541fSEmmanuel Vadot { 1480b5be541fSEmmanuel Vadot struct aw_mmc_softc *sc; 1481b5be541fSEmmanuel Vadot 1482b5be541fSEmmanuel Vadot sc = device_get_softc(bus); 1483b5be541fSEmmanuel Vadot AW_MMC_LOCK(sc); 1484b5be541fSEmmanuel Vadot sc->aw_bus_busy--; 1485b5be541fSEmmanuel Vadot wakeup(sc); 1486b5be541fSEmmanuel Vadot AW_MMC_UNLOCK(sc); 1487b5be541fSEmmanuel Vadot 1488b5be541fSEmmanuel Vadot return (0); 1489b5be541fSEmmanuel Vadot } 1490b5be541fSEmmanuel Vadot 1491b5be541fSEmmanuel Vadot static device_method_t aw_mmc_methods[] = { 1492b5be541fSEmmanuel Vadot /* Device interface */ 1493b5be541fSEmmanuel Vadot DEVMETHOD(device_probe, aw_mmc_probe), 1494b5be541fSEmmanuel Vadot DEVMETHOD(device_attach, aw_mmc_attach), 1495b5be541fSEmmanuel Vadot DEVMETHOD(device_detach, aw_mmc_detach), 1496b5be541fSEmmanuel Vadot 1497b5be541fSEmmanuel Vadot /* Bus interface */ 1498b5be541fSEmmanuel Vadot DEVMETHOD(bus_read_ivar, aw_mmc_read_ivar), 1499b5be541fSEmmanuel Vadot DEVMETHOD(bus_write_ivar, aw_mmc_write_ivar), 1500b5be541fSEmmanuel Vadot 1501b5be541fSEmmanuel Vadot /* MMC bridge interface */ 1502b5be541fSEmmanuel Vadot DEVMETHOD(mmcbr_update_ios, aw_mmc_update_ios), 1503b5be541fSEmmanuel Vadot DEVMETHOD(mmcbr_request, aw_mmc_request), 1504b5be541fSEmmanuel Vadot DEVMETHOD(mmcbr_get_ro, aw_mmc_get_ro), 1505623966e1SEmmanuel Vadot DEVMETHOD(mmcbr_switch_vccq, aw_mmc_switch_vccq), 1506b5be541fSEmmanuel Vadot DEVMETHOD(mmcbr_acquire_host, aw_mmc_acquire_host), 1507b5be541fSEmmanuel Vadot DEVMETHOD(mmcbr_release_host, aw_mmc_release_host), 1508b5be541fSEmmanuel Vadot 1509b5be541fSEmmanuel Vadot DEVMETHOD_END 1510b5be541fSEmmanuel Vadot }; 1511b5be541fSEmmanuel Vadot 1512b5be541fSEmmanuel Vadot static devclass_t aw_mmc_devclass; 1513b5be541fSEmmanuel Vadot 1514b5be541fSEmmanuel Vadot static driver_t aw_mmc_driver = { 1515b5be541fSEmmanuel Vadot "aw_mmc", 1516b5be541fSEmmanuel Vadot aw_mmc_methods, 1517b5be541fSEmmanuel Vadot sizeof(struct aw_mmc_softc), 1518b5be541fSEmmanuel Vadot }; 1519b5be541fSEmmanuel Vadot 1520b5be541fSEmmanuel Vadot DRIVER_MODULE(aw_mmc, simplebus, aw_mmc_driver, aw_mmc_devclass, NULL, 1521b5be541fSEmmanuel Vadot NULL); 15225e03278fSIlya Bakulin #ifndef MMCCAM 1523b5be541fSEmmanuel Vadot MMC_DECLARE_BRIDGE(aw_mmc); 15245e03278fSIlya Bakulin #endif 1525