1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2020 Oleksandr Tymoshenko <gonzo@FreeBSD.org> 5 * Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 #include <sys/kernel.h> 33 #include <sys/lock.h> 34 #include <sys/module.h> 35 #include <sys/mutex.h> 36 #include <sys/rman.h> 37 #include <sys/resource.h> 38 #include <machine/bus.h> 39 40 #include <dev/ofw/ofw_bus.h> 41 #include <dev/ofw/ofw_bus_subr.h> 42 43 #include <dev/clk/clk.h> 44 #include <dev/hwreset/hwreset.h> 45 46 #include "syscon_if.h" 47 48 #include "opt_snd.h" 49 #include <dev/sound/pcm/sound.h> 50 #include <dev/sound/fdt/audio_dai.h> 51 #include "audio_dai_if.h" 52 53 #define FIFO_LEVEL 0x40 54 55 #define DA_CTL 0x00 56 #define DA_CTL_BCLK_OUT (1 << 18) /* sun8i */ 57 #define DA_CLK_LRCK_OUT (1 << 17) /* sun8i */ 58 #define DA_CTL_SDO_EN (1 << 8) 59 #define DA_CTL_MS (1 << 5) /* sun4i */ 60 #define DA_CTL_PCM (1 << 4) /* sun4i */ 61 #define DA_CTL_MODE_SEL_MASK (3 << 4) /* sun8i */ 62 #define DA_CTL_MODE_SEL_PCM (0 << 4) /* sun8i */ 63 #define DA_CTL_MODE_SEL_LJ (1 << 4) /* sun8i */ 64 #define DA_CTL_MODE_SEL_RJ (2 << 4) /* sun8i */ 65 #define DA_CTL_TXEN (1 << 2) 66 #define DA_CTL_RXEN (1 << 1) 67 #define DA_CTL_GEN (1 << 0) 68 #define DA_FAT0 0x04 69 #define DA_FAT0_LRCK_PERIOD_MASK (0x3ff << 8) /* sun8i */ 70 #define DA_FAT0_LRCK_PERIOD(n) (((n) & 0x3fff) << 8) /* sun8i */ 71 #define DA_FAT0_LRCP_MASK (1 << 7) 72 #define DA_LRCP_NORMAL (0 << 7) 73 #define DA_LRCP_INVERTED (1 << 7) 74 #define DA_FAT0_BCP_MASK (1 << 6) 75 #define DA_BCP_NORMAL (0 << 6) 76 #define DA_BCP_INVERTED (1 << 6) 77 #define DA_FAT0_SR __BITS(5,4) 78 #define DA_FAT0_WSS __BITS(3,2) 79 #define DA_FAT0_FMT_MASK (3 << 0) 80 #define DA_FMT_I2S 0 81 #define DA_FMT_LJ 1 82 #define DA_FMT_RJ 2 83 #define DA_FAT1 0x08 84 #define DA_ISTA 0x0c 85 #define DA_ISTA_TXUI_INT (1 << 6) 86 #define DA_ISTA_TXEI_INT (1 << 4) 87 #define DA_ISTA_RXAI_INT (1 << 0) 88 #define DA_RXFIFO 0x10 89 #define DA_FCTL 0x14 90 #define DA_FCTL_HUB_EN (1 << 31) 91 #define DA_FCTL_FTX (1 << 25) 92 #define DA_FCTL_FRX (1 << 24) 93 #define DA_FCTL_TXTL_MASK (0x7f << 12) 94 #define DA_FCTL_TXTL(v) (((v) & 0x7f) << 12) 95 #define DA_FCTL_TXIM (1 << 2) 96 #define DA_FSTA 0x18 97 #define DA_FSTA_TXE_CNT(v) (((v) >> 16) & 0xff) 98 #define DA_FSTA_RXA_CNT(v) ((v) & 0x3f) 99 #define DA_INT 0x1c 100 #define DA_INT_TX_DRQ (1 << 7) 101 #define DA_INT_TXUI_EN (1 << 6) 102 #define DA_INT_TXEI_EN (1 << 4) 103 #define DA_INT_RX_DRQ (1 << 3) 104 #define DA_INT_RXAI_EN (1 << 0) 105 #define DA_TXFIFO 0x20 106 #define DA_CLKD 0x24 107 #define DA_CLKD_MCLKO_EN_SUN8I (1 << 8) 108 #define DA_CLKD_MCLKO_EN_SUN4I (1 << 7) 109 #define DA_CLKD_BCLKDIV_SUN8I(n) (((n) & 0xf) << 4) 110 #define DA_CLKD_BCLKDIV_SUN8I_MASK (0xf << 4) 111 #define DA_CLKD_BCLKDIV_SUN4I(n) (((n) & 7) << 4) 112 #define DA_CLKD_BCLKDIV_SUN4I_MASK (7 << 4) 113 #define DA_CLKD_BCLKDIV_8 3 114 #define DA_CLKD_BCLKDIV_16 5 115 #define DA_CLKD_MCLKDIV(n) (((n) & 0xff) << 0) 116 #define DA_CLKD_MCLKDIV_MASK (0xf << 0) 117 #define DA_CLKD_MCLKDIV_1 0 118 #define DA_TXCNT 0x28 119 #define DA_RXCNT 0x2c 120 #define DA_CHCFG 0x30 /* sun8i */ 121 #define DA_CHCFG_TX_SLOT_HIZ (1 << 9) 122 #define DA_CHCFG_TXN_STATE (1 << 8) 123 #define DA_CHCFG_RX_SLOT_NUM_MASK (7 << 4) 124 #define DA_CHCFG_RX_SLOT_NUM(n) (((n) & 7) << 4) 125 #define DA_CHCFG_TX_SLOT_NUM_MASK (7 << 0) 126 #define DA_CHCFG_TX_SLOT_NUM(n) (((n) & 7) << 0) 127 128 #define DA_CHSEL_OFFSET(n) (((n) & 3) << 12) /* sun8i */ 129 #define DA_CHSEL_OFFSET_MASK (3 << 12) /* sun8i */ 130 #define DA_CHSEL_EN(n) (((n) & 0xff) << 4) 131 #define DA_CHSEL_EN_MASK (0xff << 4) 132 #define DA_CHSEL_SEL(n) (((n) & 7) << 0) 133 #define DA_CHSEL_SEL_MASK (7 << 0) 134 135 #define AUDIO_BUFFER_SIZE 48000 * 4 136 137 #define AW_I2S_SAMPLE_RATE 48000 138 #define AW_I2S_CLK_RATE 24576000 139 140 enum sunxi_i2s_type { 141 SUNXI_I2S_SUN4I, 142 SUNXI_I2S_SUN8I, 143 }; 144 145 struct sunxi_i2s_config { 146 const char *name; 147 enum sunxi_i2s_type type; 148 bus_size_t txchsel; 149 bus_size_t txchmap; 150 bus_size_t rxchsel; 151 bus_size_t rxchmap; 152 }; 153 154 static const struct sunxi_i2s_config sun50i_a64_codec_config = { 155 .name = "Audio Codec (digital part)", 156 .type = SUNXI_I2S_SUN4I, 157 .txchsel = 0x30, 158 .txchmap = 0x34, 159 .rxchsel = 0x38, 160 .rxchmap = 0x3c, 161 }; 162 163 static const struct sunxi_i2s_config sun8i_h3_config = { 164 .name = "I2S/PCM controller", 165 .type = SUNXI_I2S_SUN8I, 166 .txchsel = 0x34, 167 .txchmap = 0x44, 168 .rxchsel = 0x54, 169 .rxchmap = 0x58, 170 }; 171 172 static const u_int sun4i_i2s_bclk_divmap[] = { 173 [0] = 2, 174 [1] = 4, 175 [2] = 6, 176 [3] = 8, 177 [4] = 12, 178 [5] = 16, 179 }; 180 181 static const u_int sun4i_i2s_mclk_divmap[] = { 182 [0] = 1, 183 [1] = 2, 184 [2] = 4, 185 [3] = 6, 186 [4] = 8, 187 [5] = 12, 188 [6] = 16, 189 [7] = 24, 190 }; 191 192 static const u_int sun8i_i2s_divmap[] = { 193 [1] = 1, 194 [2] = 2, 195 [3] = 4, 196 [4] = 6, 197 [5] = 8, 198 [6] = 12, 199 [7] = 16, 200 [8] = 24, 201 [9] = 32, 202 [10] = 48, 203 [11] = 64, 204 [12] = 96, 205 [13] = 128, 206 [14] = 176, 207 [15] = 192, 208 }; 209 210 211 static struct ofw_compat_data compat_data[] = { 212 { "allwinner,sun50i-a64-codec-i2s", (uintptr_t)&sun50i_a64_codec_config }, 213 { "allwinner,sun8i-h3-i2s", (uintptr_t)&sun8i_h3_config }, 214 { NULL, 0 } 215 }; 216 217 static struct resource_spec aw_i2s_spec[] = { 218 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 219 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 220 { -1, 0 } 221 }; 222 223 struct aw_i2s_softc { 224 device_t dev; 225 struct resource *res[2]; 226 struct mtx mtx; 227 clk_t clk; 228 struct sunxi_i2s_config *cfg; 229 void * intrhand; 230 /* pointers to playback/capture buffers */ 231 uint32_t play_ptr; 232 uint32_t rec_ptr; 233 }; 234 235 #define I2S_LOCK(sc) mtx_lock(&(sc)->mtx) 236 #define I2S_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 237 #define I2S_READ(sc, reg) bus_read_4((sc)->res[0], (reg)) 238 #define I2S_WRITE(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val)) 239 #define I2S_TYPE(sc) ((sc)->cfg->type) 240 241 static int aw_i2s_probe(device_t dev); 242 static int aw_i2s_attach(device_t dev); 243 static int aw_i2s_detach(device_t dev); 244 245 static u_int 246 sunxi_i2s_div_to_regval(const u_int *divmap, u_int divmaplen, u_int div) 247 { 248 u_int n; 249 250 for (n = 0; n < divmaplen; n++) 251 if (divmap[n] == div) 252 return n; 253 254 return -1; 255 } 256 257 static uint32_t sc_fmt[] = { 258 SND_FORMAT(AFMT_S16_LE, 2, 0), 259 0 260 }; 261 static struct pcmchan_caps aw_i2s_caps = {AW_I2S_SAMPLE_RATE, AW_I2S_SAMPLE_RATE, sc_fmt, 0}; 262 263 264 static int 265 aw_i2s_init(struct aw_i2s_softc *sc) 266 { 267 uint32_t val; 268 int error; 269 270 error = clk_enable(sc->clk); 271 if (error != 0) { 272 device_printf(sc->dev, "cannot enable mod clock\n"); 273 return (ENXIO); 274 } 275 276 /* Reset */ 277 val = I2S_READ(sc, DA_CTL); 278 val &= ~(DA_CTL_TXEN|DA_CTL_RXEN|DA_CTL_GEN); 279 I2S_WRITE(sc, DA_CTL, val); 280 281 val = I2S_READ(sc, DA_FCTL); 282 val &= ~(DA_FCTL_FTX|DA_FCTL_FRX); 283 val &= ~(DA_FCTL_TXTL_MASK); 284 val |= DA_FCTL_TXTL(FIFO_LEVEL); 285 I2S_WRITE(sc, DA_FCTL, val); 286 287 I2S_WRITE(sc, DA_TXCNT, 0); 288 I2S_WRITE(sc, DA_RXCNT, 0); 289 290 /* Enable */ 291 val = I2S_READ(sc, DA_CTL); 292 val |= DA_CTL_GEN; 293 I2S_WRITE(sc, DA_CTL, val); 294 val |= DA_CTL_SDO_EN; 295 I2S_WRITE(sc, DA_CTL, val); 296 297 /* Setup channels */ 298 I2S_WRITE(sc, sc->cfg->txchmap, 0x76543210); 299 val = I2S_READ(sc, sc->cfg->txchsel); 300 val &= ~DA_CHSEL_EN_MASK; 301 val |= DA_CHSEL_EN(3); 302 val &= ~DA_CHSEL_SEL_MASK; 303 val |= DA_CHSEL_SEL(1); 304 I2S_WRITE(sc, sc->cfg->txchsel, val); 305 I2S_WRITE(sc, sc->cfg->rxchmap, 0x76543210); 306 val = I2S_READ(sc, sc->cfg->rxchsel); 307 val &= ~DA_CHSEL_EN_MASK; 308 val |= DA_CHSEL_EN(3); 309 val &= ~DA_CHSEL_SEL_MASK; 310 val |= DA_CHSEL_SEL(1); 311 I2S_WRITE(sc, sc->cfg->rxchsel, val); 312 313 if (I2S_TYPE(sc) == SUNXI_I2S_SUN8I) { 314 val = I2S_READ(sc, DA_CHCFG); 315 val &= ~DA_CHCFG_TX_SLOT_NUM_MASK; 316 val |= DA_CHCFG_TX_SLOT_NUM(1); 317 val &= ~DA_CHCFG_RX_SLOT_NUM_MASK; 318 val |= DA_CHCFG_RX_SLOT_NUM(1); 319 I2S_WRITE(sc, DA_CHCFG, val); 320 } 321 322 return (0); 323 } 324 325 static int 326 aw_i2s_probe(device_t dev) 327 { 328 if (!ofw_bus_status_okay(dev)) 329 return (ENXIO); 330 331 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) 332 return (ENXIO); 333 334 device_set_desc(dev, "Allwinner I2S"); 335 return (BUS_PROBE_DEFAULT); 336 } 337 338 static int 339 aw_i2s_attach(device_t dev) 340 { 341 struct aw_i2s_softc *sc; 342 int error; 343 phandle_t node; 344 hwreset_t rst; 345 clk_t clk; 346 347 sc = device_get_softc(dev); 348 sc->dev = dev; 349 350 sc->cfg = (void*)ofw_bus_search_compatible(dev, compat_data)->ocd_data; 351 352 mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); 353 354 if (bus_alloc_resources(dev, aw_i2s_spec, sc->res) != 0) { 355 device_printf(dev, "cannot allocate resources for device\n"); 356 error = ENXIO; 357 goto fail; 358 } 359 360 error = clk_get_by_ofw_name(dev, 0, "mod", &sc->clk); 361 if (error != 0) { 362 device_printf(dev, "cannot get i2s_clk clock\n"); 363 goto fail; 364 } 365 366 error = clk_get_by_ofw_name(dev, 0, "apb", &clk); 367 if (error != 0) { 368 device_printf(dev, "cannot get APB clock\n"); 369 goto fail; 370 } 371 372 error = clk_enable(clk); 373 if (error != 0) { 374 device_printf(dev, "cannot enable APB clock\n"); 375 goto fail; 376 } 377 378 if (hwreset_get_by_ofw_idx(dev, 0, 0, &rst) == 0) { 379 error = hwreset_deassert(rst); 380 if (error != 0) { 381 device_printf(dev, "cannot de-assert reset\n"); 382 goto fail; 383 } 384 } 385 386 aw_i2s_init(sc); 387 388 node = ofw_bus_get_node(dev); 389 OF_device_register_xref(OF_xref_from_node(node), dev); 390 391 return (0); 392 393 fail: 394 aw_i2s_detach(dev); 395 return (error); 396 } 397 398 static int 399 aw_i2s_detach(device_t dev) 400 { 401 struct aw_i2s_softc *i2s; 402 403 i2s = device_get_softc(dev); 404 405 if (i2s->clk) 406 clk_release(i2s->clk); 407 408 if (i2s->intrhand != NULL) 409 bus_teardown_intr(i2s->dev, i2s->res[1], i2s->intrhand); 410 411 bus_release_resources(dev, aw_i2s_spec, i2s->res); 412 mtx_destroy(&i2s->mtx); 413 414 return (0); 415 } 416 417 static int 418 aw_i2s_dai_init(device_t dev, uint32_t format) 419 { 420 struct aw_i2s_softc *sc; 421 int fmt, pol; 422 uint32_t ctl, fat0, chsel; 423 u_int offset; 424 425 sc = device_get_softc(dev); 426 427 fmt = AUDIO_DAI_FORMAT_FORMAT(format); 428 pol = AUDIO_DAI_FORMAT_POLARITY(format); 429 430 ctl = I2S_READ(sc, DA_CTL); 431 fat0 = I2S_READ(sc, DA_FAT0); 432 433 if (I2S_TYPE(sc) == SUNXI_I2S_SUN4I) { 434 fat0 &= ~DA_FAT0_FMT_MASK; 435 switch (fmt) { 436 case AUDIO_DAI_FORMAT_I2S: 437 fat0 |= DA_FMT_I2S; 438 break; 439 case AUDIO_DAI_FORMAT_RJ: 440 fat0 |= DA_FMT_RJ; 441 break; 442 case AUDIO_DAI_FORMAT_LJ: 443 fat0 |= DA_FMT_LJ; 444 break; 445 default: 446 return EINVAL; 447 } 448 ctl &= ~DA_CTL_PCM; 449 } else { 450 ctl &= ~DA_CTL_MODE_SEL_MASK; 451 switch (fmt) { 452 case AUDIO_DAI_FORMAT_I2S: 453 ctl |= DA_CTL_MODE_SEL_LJ; 454 offset = 1; 455 break; 456 case AUDIO_DAI_FORMAT_LJ: 457 ctl |= DA_CTL_MODE_SEL_LJ; 458 offset = 0; 459 break; 460 case AUDIO_DAI_FORMAT_RJ: 461 ctl |= DA_CTL_MODE_SEL_RJ; 462 offset = 0; 463 break; 464 case AUDIO_DAI_FORMAT_DSPA: 465 ctl |= DA_CTL_MODE_SEL_PCM; 466 offset = 1; 467 break; 468 case AUDIO_DAI_FORMAT_DSPB: 469 ctl |= DA_CTL_MODE_SEL_PCM; 470 offset = 0; 471 break; 472 default: 473 return EINVAL; 474 } 475 476 chsel = I2S_READ(sc, sc->cfg->txchsel); 477 chsel &= ~DA_CHSEL_OFFSET_MASK; 478 chsel |= DA_CHSEL_OFFSET(offset); 479 I2S_WRITE(sc, sc->cfg->txchsel, chsel); 480 481 chsel = I2S_READ(sc, sc->cfg->rxchsel); 482 chsel &= ~DA_CHSEL_OFFSET_MASK; 483 chsel |= DA_CHSEL_OFFSET(offset); 484 I2S_WRITE(sc, sc->cfg->rxchsel, chsel); 485 } 486 487 fat0 &= ~(DA_FAT0_LRCP_MASK|DA_FAT0_BCP_MASK); 488 if (I2S_TYPE(sc) == SUNXI_I2S_SUN4I) { 489 if (AUDIO_DAI_POLARITY_INVERTED_BCLK(pol)) 490 fat0 |= DA_BCP_INVERTED; 491 if (AUDIO_DAI_POLARITY_INVERTED_FRAME(pol)) 492 fat0 |= DA_LRCP_INVERTED; 493 } else { 494 if (AUDIO_DAI_POLARITY_INVERTED_BCLK(pol)) 495 fat0 |= DA_BCP_INVERTED; 496 if (!AUDIO_DAI_POLARITY_INVERTED_FRAME(pol)) 497 fat0 |= DA_LRCP_INVERTED; 498 499 fat0 &= ~DA_FAT0_LRCK_PERIOD_MASK; 500 fat0 |= DA_FAT0_LRCK_PERIOD(32 - 1); 501 } 502 503 I2S_WRITE(sc, DA_CTL, ctl); 504 I2S_WRITE(sc, DA_FAT0, fat0); 505 506 return (0); 507 } 508 509 510 static int 511 aw_i2s_dai_intr(device_t dev, struct snd_dbuf *play_buf, struct snd_dbuf *rec_buf) 512 { 513 struct aw_i2s_softc *sc; 514 int ret = 0; 515 uint32_t val, status; 516 517 sc = device_get_softc(dev); 518 519 I2S_LOCK(sc); 520 521 status = I2S_READ(sc, DA_ISTA); 522 /* Clear interrupts */ 523 // device_printf(sc->dev, "status: %08x\n", status); 524 I2S_WRITE(sc, DA_ISTA, status); 525 526 if (status & DA_ISTA_TXEI_INT) { 527 uint8_t *samples; 528 uint32_t count, size, readyptr, written, empty; 529 530 val = I2S_READ(sc, DA_FSTA); 531 empty = DA_FSTA_TXE_CNT(val); 532 count = sndbuf_getready(play_buf); 533 size = sndbuf_getsize(play_buf); 534 readyptr = sndbuf_getreadyptr(play_buf); 535 536 samples = (uint8_t*)sndbuf_getbuf(play_buf); 537 written = 0; 538 if (empty > count / 2) 539 empty = count / 2; 540 for (; empty > 0; empty--) { 541 val = (samples[readyptr++ % size] << 16); 542 val |= (samples[readyptr++ % size] << 24); 543 written += 2; 544 I2S_WRITE(sc, DA_TXFIFO, val); 545 } 546 sc->play_ptr += written; 547 sc->play_ptr %= size; 548 ret |= AUDIO_DAI_PLAY_INTR; 549 } 550 551 if (status & DA_ISTA_RXAI_INT) { 552 uint8_t *samples; 553 uint32_t count, size, freeptr, recorded, available; 554 555 val = I2S_READ(sc, DA_FSTA); 556 available = DA_FSTA_RXA_CNT(val); 557 558 count = sndbuf_getfree(rec_buf); 559 size = sndbuf_getsize(rec_buf); 560 freeptr = sndbuf_getfreeptr(rec_buf); 561 samples = (uint8_t*)sndbuf_getbuf(rec_buf); 562 recorded = 0; 563 if (available > count / 2) 564 available = count / 2; 565 566 for (; available > 0; available--) { 567 val = I2S_READ(sc, DA_RXFIFO); 568 samples[freeptr++ % size] = (val >> 16) & 0xff; 569 samples[freeptr++ % size] = (val >> 24) & 0xff; 570 recorded += 2; 571 } 572 sc->rec_ptr += recorded; 573 sc->rec_ptr %= size; 574 ret |= AUDIO_DAI_REC_INTR; 575 } 576 577 I2S_UNLOCK(sc); 578 579 return (ret); 580 } 581 582 static struct pcmchan_caps * 583 aw_i2s_dai_get_caps(device_t dev) 584 { 585 return (&aw_i2s_caps); 586 } 587 588 static int 589 aw_i2s_dai_trigger(device_t dev, int go, int pcm_dir) 590 { 591 struct aw_i2s_softc *sc = device_get_softc(dev); 592 uint32_t val; 593 594 if ((pcm_dir != PCMDIR_PLAY) && (pcm_dir != PCMDIR_REC)) 595 return (EINVAL); 596 597 switch (go) { 598 case PCMTRIG_START: 599 if (pcm_dir == PCMDIR_PLAY) { 600 /* Flush FIFO */ 601 val = I2S_READ(sc, DA_FCTL); 602 I2S_WRITE(sc, DA_FCTL, val | DA_FCTL_FTX); 603 I2S_WRITE(sc, DA_FCTL, val & ~DA_FCTL_FTX); 604 605 /* Reset TX sample counter */ 606 I2S_WRITE(sc, DA_TXCNT, 0); 607 608 /* Enable TX block */ 609 val = I2S_READ(sc, DA_CTL); 610 I2S_WRITE(sc, DA_CTL, val | DA_CTL_TXEN); 611 612 /* Enable TX underrun interrupt */ 613 val = I2S_READ(sc, DA_INT); 614 I2S_WRITE(sc, DA_INT, val | DA_INT_TXEI_EN); 615 } 616 617 if (pcm_dir == PCMDIR_REC) { 618 /* Flush FIFO */ 619 val = I2S_READ(sc, DA_FCTL); 620 I2S_WRITE(sc, DA_FCTL, val | DA_FCTL_FRX); 621 I2S_WRITE(sc, DA_FCTL, val & ~DA_FCTL_FRX); 622 623 /* Reset RX sample counter */ 624 I2S_WRITE(sc, DA_RXCNT, 0); 625 626 /* Enable RX block */ 627 val = I2S_READ(sc, DA_CTL); 628 I2S_WRITE(sc, DA_CTL, val | DA_CTL_RXEN); 629 630 /* Enable RX data available interrupt */ 631 val = I2S_READ(sc, DA_INT); 632 I2S_WRITE(sc, DA_INT, val | DA_INT_RXAI_EN); 633 } 634 635 break; 636 637 case PCMTRIG_STOP: 638 case PCMTRIG_ABORT: 639 I2S_LOCK(sc); 640 641 if (pcm_dir == PCMDIR_PLAY) { 642 /* Disable TX block */ 643 val = I2S_READ(sc, DA_CTL); 644 I2S_WRITE(sc, DA_CTL, val & ~DA_CTL_TXEN); 645 646 /* Enable TX underrun interrupt */ 647 val = I2S_READ(sc, DA_INT); 648 I2S_WRITE(sc, DA_INT, val & ~DA_INT_TXEI_EN); 649 650 sc->play_ptr = 0; 651 } else { 652 /* Disable RX block */ 653 val = I2S_READ(sc, DA_CTL); 654 I2S_WRITE(sc, DA_CTL, val & ~DA_CTL_RXEN); 655 656 /* Disable RX data available interrupt */ 657 val = I2S_READ(sc, DA_INT); 658 I2S_WRITE(sc, DA_INT, val & ~DA_INT_RXAI_EN); 659 660 sc->rec_ptr = 0; 661 } 662 663 I2S_UNLOCK(sc); 664 break; 665 } 666 667 return (0); 668 } 669 670 static uint32_t 671 aw_i2s_dai_get_ptr(device_t dev, int pcm_dir) 672 { 673 struct aw_i2s_softc *sc; 674 uint32_t ptr; 675 676 sc = device_get_softc(dev); 677 678 I2S_LOCK(sc); 679 if (pcm_dir == PCMDIR_PLAY) 680 ptr = sc->play_ptr; 681 else 682 ptr = sc->rec_ptr; 683 I2S_UNLOCK(sc); 684 685 return ptr; 686 } 687 688 static int 689 aw_i2s_dai_setup_intr(device_t dev, driver_intr_t intr_handler, void *intr_arg) 690 { 691 struct aw_i2s_softc *sc = device_get_softc(dev); 692 693 if (bus_setup_intr(dev, sc->res[1], 694 INTR_TYPE_MISC | INTR_MPSAFE, NULL, intr_handler, intr_arg, 695 &sc->intrhand)) { 696 device_printf(dev, "cannot setup interrupt handler\n"); 697 return (ENXIO); 698 } 699 700 return (0); 701 } 702 703 static uint32_t 704 aw_i2s_dai_set_chanformat(device_t dev, uint32_t format) 705 { 706 707 return (0); 708 } 709 710 static int 711 aw_i2s_dai_set_sysclk(device_t dev, unsigned int rate, int dai_dir) 712 { 713 struct aw_i2s_softc *sc; 714 int bclk_val, mclk_val; 715 uint32_t val; 716 int error; 717 718 sc = device_get_softc(dev); 719 720 error = clk_set_freq(sc->clk, AW_I2S_CLK_RATE, CLK_SET_ROUND_DOWN); 721 if (error != 0) { 722 device_printf(sc->dev, 723 "couldn't set mod clock rate to %u Hz: %d\n", AW_I2S_CLK_RATE, error); 724 return error; 725 } 726 error = clk_enable(sc->clk); 727 if (error != 0) { 728 device_printf(sc->dev, 729 "couldn't enable mod clock: %d\n", error); 730 return error; 731 } 732 733 const u_int bclk_prate = I2S_TYPE(sc) == SUNXI_I2S_SUN4I ? rate : AW_I2S_CLK_RATE; 734 735 const u_int bclk_div = bclk_prate / (2 * 32 * AW_I2S_SAMPLE_RATE); 736 const u_int mclk_div = AW_I2S_CLK_RATE / rate; 737 738 if (I2S_TYPE(sc) == SUNXI_I2S_SUN4I) { 739 bclk_val = sunxi_i2s_div_to_regval(sun4i_i2s_bclk_divmap, 740 nitems(sun4i_i2s_bclk_divmap), bclk_div); 741 mclk_val = sunxi_i2s_div_to_regval(sun4i_i2s_mclk_divmap, 742 nitems(sun4i_i2s_mclk_divmap), mclk_div); 743 } else { 744 bclk_val = sunxi_i2s_div_to_regval(sun8i_i2s_divmap, 745 nitems(sun8i_i2s_divmap), bclk_div); 746 mclk_val = sunxi_i2s_div_to_regval(sun8i_i2s_divmap, 747 nitems(sun8i_i2s_divmap), mclk_div); 748 } 749 if (bclk_val == -1 || mclk_val == -1) { 750 device_printf(sc->dev, "couldn't configure bclk/mclk dividers\n"); 751 return EIO; 752 } 753 754 val = I2S_READ(sc, DA_CLKD); 755 if (I2S_TYPE(sc) == SUNXI_I2S_SUN4I) { 756 val |= DA_CLKD_MCLKO_EN_SUN4I; 757 val &= ~DA_CLKD_BCLKDIV_SUN4I_MASK; 758 val |= DA_CLKD_BCLKDIV_SUN4I(bclk_val); 759 } else { 760 val |= DA_CLKD_MCLKO_EN_SUN8I; 761 val &= ~DA_CLKD_BCLKDIV_SUN8I_MASK; 762 val |= DA_CLKD_BCLKDIV_SUN8I(bclk_val); 763 } 764 val &= ~DA_CLKD_MCLKDIV_MASK; 765 val |= DA_CLKD_MCLKDIV(mclk_val); 766 I2S_WRITE(sc, DA_CLKD, val); 767 768 769 return (0); 770 } 771 772 static uint32_t 773 aw_i2s_dai_set_chanspeed(device_t dev, uint32_t speed) 774 { 775 776 return (speed); 777 } 778 779 static device_method_t aw_i2s_methods[] = { 780 /* Device interface */ 781 DEVMETHOD(device_probe, aw_i2s_probe), 782 DEVMETHOD(device_attach, aw_i2s_attach), 783 DEVMETHOD(device_detach, aw_i2s_detach), 784 785 DEVMETHOD(audio_dai_init, aw_i2s_dai_init), 786 DEVMETHOD(audio_dai_setup_intr, aw_i2s_dai_setup_intr), 787 DEVMETHOD(audio_dai_set_sysclk, aw_i2s_dai_set_sysclk), 788 DEVMETHOD(audio_dai_set_chanspeed, aw_i2s_dai_set_chanspeed), 789 DEVMETHOD(audio_dai_set_chanformat, aw_i2s_dai_set_chanformat), 790 DEVMETHOD(audio_dai_intr, aw_i2s_dai_intr), 791 DEVMETHOD(audio_dai_get_caps, aw_i2s_dai_get_caps), 792 DEVMETHOD(audio_dai_trigger, aw_i2s_dai_trigger), 793 DEVMETHOD(audio_dai_get_ptr, aw_i2s_dai_get_ptr), 794 795 DEVMETHOD_END 796 }; 797 798 static driver_t aw_i2s_driver = { 799 "i2s", 800 aw_i2s_methods, 801 sizeof(struct aw_i2s_softc), 802 }; 803 804 DRIVER_MODULE(aw_i2s, simplebus, aw_i2s_driver, 0, 0); 805 SIMPLEBUS_PNP_INFO(compat_data); 806