1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2020 Oleksandr Tymoshenko <gonzo@FreeBSD.org> 5 * Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/kernel.h> 36 #include <sys/lock.h> 37 #include <sys/module.h> 38 #include <sys/mutex.h> 39 #include <sys/rman.h> 40 #include <sys/resource.h> 41 #include <machine/bus.h> 42 43 #include <dev/ofw/ofw_bus.h> 44 #include <dev/ofw/ofw_bus_subr.h> 45 46 #include <dev/extres/clk/clk.h> 47 #include <dev/extres/hwreset/hwreset.h> 48 49 #include "syscon_if.h" 50 51 #include "opt_snd.h" 52 #include <dev/sound/pcm/sound.h> 53 #include <dev/sound/fdt/audio_dai.h> 54 #include "audio_dai_if.h" 55 56 #define FIFO_LEVEL 0x40 57 58 #define DA_CTL 0x00 59 #define DA_CTL_BCLK_OUT (1 << 18) /* sun8i */ 60 #define DA_CLK_LRCK_OUT (1 << 17) /* sun8i */ 61 #define DA_CTL_SDO_EN (1 << 8) 62 #define DA_CTL_MS (1 << 5) /* sun4i */ 63 #define DA_CTL_PCM (1 << 4) /* sun4i */ 64 #define DA_CTL_MODE_SEL_MASK (3 << 4) /* sun8i */ 65 #define DA_CTL_MODE_SEL_PCM (0 << 4) /* sun8i */ 66 #define DA_CTL_MODE_SEL_LJ (1 << 4) /* sun8i */ 67 #define DA_CTL_MODE_SEL_RJ (2 << 4) /* sun8i */ 68 #define DA_CTL_TXEN (1 << 2) 69 #define DA_CTL_RXEN (1 << 1) 70 #define DA_CTL_GEN (1 << 0) 71 #define DA_FAT0 0x04 72 #define DA_FAT0_LRCK_PERIOD_MASK (0x3ff << 8) /* sun8i */ 73 #define DA_FAT0_LRCK_PERIOD(n) (((n) & 0x3fff) << 8) /* sun8i */ 74 #define DA_FAT0_LRCP_MASK (1 << 7) 75 #define DA_LRCP_NORMAL (0 << 7) 76 #define DA_LRCP_INVERTED (1 << 7) 77 #define DA_FAT0_BCP_MASK (1 << 6) 78 #define DA_BCP_NORMAL (0 << 6) 79 #define DA_BCP_INVERTED (1 << 6) 80 #define DA_FAT0_SR __BITS(5,4) 81 #define DA_FAT0_WSS __BITS(3,2) 82 #define DA_FAT0_FMT_MASK (3 << 0) 83 #define DA_FMT_I2S 0 84 #define DA_FMT_LJ 1 85 #define DA_FMT_RJ 2 86 #define DA_FAT1 0x08 87 #define DA_ISTA 0x0c 88 #define DA_ISTA_TXUI_INT (1 << 6) 89 #define DA_ISTA_TXEI_INT (1 << 4) 90 #define DA_ISTA_RXAI_INT (1 << 0) 91 #define DA_RXFIFO 0x10 92 #define DA_FCTL 0x14 93 #define DA_FCTL_HUB_EN (1 << 31) 94 #define DA_FCTL_FTX (1 << 25) 95 #define DA_FCTL_FRX (1 << 24) 96 #define DA_FCTL_TXTL_MASK (0x7f << 12) 97 #define DA_FCTL_TXTL(v) (((v) & 0x7f) << 12) 98 #define DA_FCTL_TXIM (1 << 2) 99 #define DA_FSTA 0x18 100 #define DA_FSTA_TXE_CNT(v) (((v) >> 16) & 0xff) 101 #define DA_FSTA_RXA_CNT(v) ((v) & 0x3f) 102 #define DA_INT 0x1c 103 #define DA_INT_TX_DRQ (1 << 7) 104 #define DA_INT_TXUI_EN (1 << 6) 105 #define DA_INT_TXEI_EN (1 << 4) 106 #define DA_INT_RX_DRQ (1 << 3) 107 #define DA_INT_RXAI_EN (1 << 0) 108 #define DA_TXFIFO 0x20 109 #define DA_CLKD 0x24 110 #define DA_CLKD_MCLKO_EN_SUN8I (1 << 8) 111 #define DA_CLKD_MCLKO_EN_SUN4I (1 << 7) 112 #define DA_CLKD_BCLKDIV_SUN8I(n) (((n) & 0xf) << 4) 113 #define DA_CLKD_BCLKDIV_SUN8I_MASK (0xf << 4) 114 #define DA_CLKD_BCLKDIV_SUN4I(n) (((n) & 7) << 4) 115 #define DA_CLKD_BCLKDIV_SUN4I_MASK (7 << 4) 116 #define DA_CLKD_BCLKDIV_8 3 117 #define DA_CLKD_BCLKDIV_16 5 118 #define DA_CLKD_MCLKDIV(n) (((n) & 0xff) << 0) 119 #define DA_CLKD_MCLKDIV_MASK (0xf << 0) 120 #define DA_CLKD_MCLKDIV_1 0 121 #define DA_TXCNT 0x28 122 #define DA_RXCNT 0x2c 123 #define DA_CHCFG 0x30 /* sun8i */ 124 #define DA_CHCFG_TX_SLOT_HIZ (1 << 9) 125 #define DA_CHCFG_TXN_STATE (1 << 8) 126 #define DA_CHCFG_RX_SLOT_NUM_MASK (7 << 4) 127 #define DA_CHCFG_RX_SLOT_NUM(n) (((n) & 7) << 4) 128 #define DA_CHCFG_TX_SLOT_NUM_MASK (7 << 0) 129 #define DA_CHCFG_TX_SLOT_NUM(n) (((n) & 7) << 0) 130 131 #define DA_CHSEL_OFFSET(n) (((n) & 3) << 12) /* sun8i */ 132 #define DA_CHSEL_OFFSET_MASK (3 << 12) /* sun8i */ 133 #define DA_CHSEL_EN(n) (((n) & 0xff) << 4) 134 #define DA_CHSEL_EN_MASK (0xff << 4) 135 #define DA_CHSEL_SEL(n) (((n) & 7) << 0) 136 #define DA_CHSEL_SEL_MASK (7 << 0) 137 138 #define AUDIO_BUFFER_SIZE 48000 * 4 139 140 #define AW_I2S_SAMPLE_RATE 48000 141 #define AW_I2S_CLK_RATE 24576000 142 143 enum sunxi_i2s_type { 144 SUNXI_I2S_SUN4I, 145 SUNXI_I2S_SUN8I, 146 }; 147 148 struct sunxi_i2s_config { 149 const char *name; 150 enum sunxi_i2s_type type; 151 bus_size_t txchsel; 152 bus_size_t txchmap; 153 bus_size_t rxchsel; 154 bus_size_t rxchmap; 155 }; 156 157 static const struct sunxi_i2s_config sun50i_a64_codec_config = { 158 .name = "Audio Codec (digital part)", 159 .type = SUNXI_I2S_SUN4I, 160 .txchsel = 0x30, 161 .txchmap = 0x34, 162 .rxchsel = 0x38, 163 .rxchmap = 0x3c, 164 }; 165 166 static const struct sunxi_i2s_config sun8i_h3_config = { 167 .name = "I2S/PCM controller", 168 .type = SUNXI_I2S_SUN8I, 169 .txchsel = 0x34, 170 .txchmap = 0x44, 171 .rxchsel = 0x54, 172 .rxchmap = 0x58, 173 }; 174 175 static const u_int sun4i_i2s_bclk_divmap[] = { 176 [0] = 2, 177 [1] = 4, 178 [2] = 6, 179 [3] = 8, 180 [4] = 12, 181 [5] = 16, 182 }; 183 184 static const u_int sun4i_i2s_mclk_divmap[] = { 185 [0] = 1, 186 [1] = 2, 187 [2] = 4, 188 [3] = 6, 189 [4] = 8, 190 [5] = 12, 191 [6] = 16, 192 [7] = 24, 193 }; 194 195 static const u_int sun8i_i2s_divmap[] = { 196 [1] = 1, 197 [2] = 2, 198 [3] = 4, 199 [4] = 6, 200 [5] = 8, 201 [6] = 12, 202 [7] = 16, 203 [8] = 24, 204 [9] = 32, 205 [10] = 48, 206 [11] = 64, 207 [12] = 96, 208 [13] = 128, 209 [14] = 176, 210 [15] = 192, 211 }; 212 213 214 static struct ofw_compat_data compat_data[] = { 215 { "allwinner,sun50i-a64-codec-i2s", (uintptr_t)&sun50i_a64_codec_config }, 216 { "allwinner,sun8i-h3-i2s", (uintptr_t)&sun8i_h3_config }, 217 { NULL, 0 } 218 }; 219 220 static struct resource_spec aw_i2s_spec[] = { 221 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 222 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 223 { -1, 0 } 224 }; 225 226 struct aw_i2s_softc { 227 device_t dev; 228 struct resource *res[2]; 229 struct mtx mtx; 230 clk_t clk; 231 struct sunxi_i2s_config *cfg; 232 void * intrhand; 233 /* pointers to playback/capture buffers */ 234 uint32_t play_ptr; 235 uint32_t rec_ptr; 236 }; 237 238 #define I2S_LOCK(sc) mtx_lock(&(sc)->mtx) 239 #define I2S_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 240 #define I2S_READ(sc, reg) bus_read_4((sc)->res[0], (reg)) 241 #define I2S_WRITE(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val)) 242 #define I2S_TYPE(sc) ((sc)->cfg->type) 243 244 static int aw_i2s_probe(device_t dev); 245 static int aw_i2s_attach(device_t dev); 246 static int aw_i2s_detach(device_t dev); 247 248 static u_int 249 sunxi_i2s_div_to_regval(const u_int *divmap, u_int divmaplen, u_int div) 250 { 251 u_int n; 252 253 for (n = 0; n < divmaplen; n++) 254 if (divmap[n] == div) 255 return n; 256 257 return -1; 258 } 259 260 static uint32_t sc_fmt[] = { 261 SND_FORMAT(AFMT_S16_LE, 2, 0), 262 0 263 }; 264 static struct pcmchan_caps aw_i2s_caps = {AW_I2S_SAMPLE_RATE, AW_I2S_SAMPLE_RATE, sc_fmt, 0}; 265 266 267 static int 268 aw_i2s_init(struct aw_i2s_softc *sc) 269 { 270 uint32_t val; 271 int error; 272 273 error = clk_enable(sc->clk); 274 if (error != 0) { 275 device_printf(sc->dev, "cannot enable mod clock\n"); 276 return (ENXIO); 277 } 278 279 /* Reset */ 280 val = I2S_READ(sc, DA_CTL); 281 val &= ~(DA_CTL_TXEN|DA_CTL_RXEN|DA_CTL_GEN); 282 I2S_WRITE(sc, DA_CTL, val); 283 284 val = I2S_READ(sc, DA_FCTL); 285 val &= ~(DA_FCTL_FTX|DA_FCTL_FRX); 286 val &= ~(DA_FCTL_TXTL_MASK); 287 val |= DA_FCTL_TXTL(FIFO_LEVEL); 288 I2S_WRITE(sc, DA_FCTL, val); 289 290 I2S_WRITE(sc, DA_TXCNT, 0); 291 I2S_WRITE(sc, DA_RXCNT, 0); 292 293 /* Enable */ 294 val = I2S_READ(sc, DA_CTL); 295 val |= DA_CTL_GEN; 296 I2S_WRITE(sc, DA_CTL, val); 297 val |= DA_CTL_SDO_EN; 298 I2S_WRITE(sc, DA_CTL, val); 299 300 /* Setup channels */ 301 I2S_WRITE(sc, sc->cfg->txchmap, 0x76543210); 302 val = I2S_READ(sc, sc->cfg->txchsel); 303 val &= ~DA_CHSEL_EN_MASK; 304 val |= DA_CHSEL_EN(3); 305 val &= ~DA_CHSEL_SEL_MASK; 306 val |= DA_CHSEL_SEL(1); 307 I2S_WRITE(sc, sc->cfg->txchsel, val); 308 I2S_WRITE(sc, sc->cfg->rxchmap, 0x76543210); 309 val = I2S_READ(sc, sc->cfg->rxchsel); 310 val &= ~DA_CHSEL_EN_MASK; 311 val |= DA_CHSEL_EN(3); 312 val &= ~DA_CHSEL_SEL_MASK; 313 val |= DA_CHSEL_SEL(1); 314 I2S_WRITE(sc, sc->cfg->rxchsel, val); 315 316 if (I2S_TYPE(sc) == SUNXI_I2S_SUN8I) { 317 val = I2S_READ(sc, DA_CHCFG); 318 val &= ~DA_CHCFG_TX_SLOT_NUM_MASK; 319 val |= DA_CHCFG_TX_SLOT_NUM(1); 320 val &= ~DA_CHCFG_RX_SLOT_NUM_MASK; 321 val |= DA_CHCFG_RX_SLOT_NUM(1); 322 I2S_WRITE(sc, DA_CHCFG, val); 323 } 324 325 return (0); 326 } 327 328 static int 329 aw_i2s_probe(device_t dev) 330 { 331 if (!ofw_bus_status_okay(dev)) 332 return (ENXIO); 333 334 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) 335 return (ENXIO); 336 337 device_set_desc(dev, "Allwinner I2S"); 338 return (BUS_PROBE_DEFAULT); 339 } 340 341 static int 342 aw_i2s_attach(device_t dev) 343 { 344 struct aw_i2s_softc *sc; 345 int error; 346 phandle_t node; 347 hwreset_t rst; 348 clk_t clk; 349 350 sc = device_get_softc(dev); 351 sc->dev = dev; 352 353 sc->cfg = (void*)ofw_bus_search_compatible(dev, compat_data)->ocd_data; 354 355 mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); 356 357 if (bus_alloc_resources(dev, aw_i2s_spec, sc->res) != 0) { 358 device_printf(dev, "cannot allocate resources for device\n"); 359 error = ENXIO; 360 goto fail; 361 } 362 363 error = clk_get_by_ofw_name(dev, 0, "mod", &sc->clk); 364 if (error != 0) { 365 device_printf(dev, "cannot get i2s_clk clock\n"); 366 goto fail; 367 } 368 369 error = clk_get_by_ofw_name(dev, 0, "apb", &clk); 370 if (error != 0) { 371 device_printf(dev, "cannot get APB clock\n"); 372 goto fail; 373 } 374 375 error = clk_enable(clk); 376 if (error != 0) { 377 device_printf(dev, "cannot enable APB clock\n"); 378 goto fail; 379 } 380 381 if (hwreset_get_by_ofw_idx(dev, 0, 0, &rst) == 0) { 382 error = hwreset_deassert(rst); 383 if (error != 0) { 384 device_printf(dev, "cannot de-assert reset\n"); 385 goto fail; 386 } 387 } 388 389 aw_i2s_init(sc); 390 391 node = ofw_bus_get_node(dev); 392 OF_device_register_xref(OF_xref_from_node(node), dev); 393 394 return (0); 395 396 fail: 397 aw_i2s_detach(dev); 398 return (error); 399 } 400 401 static int 402 aw_i2s_detach(device_t dev) 403 { 404 struct aw_i2s_softc *i2s; 405 406 i2s = device_get_softc(dev); 407 408 if (i2s->clk) 409 clk_release(i2s->clk); 410 411 if (i2s->intrhand != NULL) 412 bus_teardown_intr(i2s->dev, i2s->res[1], i2s->intrhand); 413 414 bus_release_resources(dev, aw_i2s_spec, i2s->res); 415 mtx_destroy(&i2s->mtx); 416 417 return (0); 418 } 419 420 static int 421 aw_i2s_dai_init(device_t dev, uint32_t format) 422 { 423 struct aw_i2s_softc *sc; 424 int fmt, pol; 425 uint32_t ctl, fat0, chsel; 426 u_int offset; 427 428 sc = device_get_softc(dev); 429 430 fmt = AUDIO_DAI_FORMAT_FORMAT(format); 431 pol = AUDIO_DAI_FORMAT_POLARITY(format); 432 433 ctl = I2S_READ(sc, DA_CTL); 434 fat0 = I2S_READ(sc, DA_FAT0); 435 436 if (I2S_TYPE(sc) == SUNXI_I2S_SUN4I) { 437 fat0 &= ~DA_FAT0_FMT_MASK; 438 switch (fmt) { 439 case AUDIO_DAI_FORMAT_I2S: 440 fat0 |= DA_FMT_I2S; 441 break; 442 case AUDIO_DAI_FORMAT_RJ: 443 fat0 |= DA_FMT_RJ; 444 break; 445 case AUDIO_DAI_FORMAT_LJ: 446 fat0 |= DA_FMT_LJ; 447 break; 448 default: 449 return EINVAL; 450 } 451 ctl &= ~DA_CTL_PCM; 452 } else { 453 ctl &= ~DA_CTL_MODE_SEL_MASK; 454 switch (fmt) { 455 case AUDIO_DAI_FORMAT_I2S: 456 ctl |= DA_CTL_MODE_SEL_LJ; 457 offset = 1; 458 break; 459 case AUDIO_DAI_FORMAT_LJ: 460 ctl |= DA_CTL_MODE_SEL_LJ; 461 offset = 0; 462 break; 463 case AUDIO_DAI_FORMAT_RJ: 464 ctl |= DA_CTL_MODE_SEL_RJ; 465 offset = 0; 466 break; 467 case AUDIO_DAI_FORMAT_DSPA: 468 ctl |= DA_CTL_MODE_SEL_PCM; 469 offset = 1; 470 break; 471 case AUDIO_DAI_FORMAT_DSPB: 472 ctl |= DA_CTL_MODE_SEL_PCM; 473 offset = 0; 474 break; 475 default: 476 return EINVAL; 477 } 478 479 chsel = I2S_READ(sc, sc->cfg->txchsel); 480 chsel &= ~DA_CHSEL_OFFSET_MASK; 481 chsel |= DA_CHSEL_OFFSET(offset); 482 I2S_WRITE(sc, sc->cfg->txchsel, chsel); 483 484 chsel = I2S_READ(sc, sc->cfg->rxchsel); 485 chsel &= ~DA_CHSEL_OFFSET_MASK; 486 chsel |= DA_CHSEL_OFFSET(offset); 487 I2S_WRITE(sc, sc->cfg->rxchsel, chsel); 488 } 489 490 fat0 &= ~(DA_FAT0_LRCP_MASK|DA_FAT0_BCP_MASK); 491 if (I2S_TYPE(sc) == SUNXI_I2S_SUN4I) { 492 if (AUDIO_DAI_POLARITY_INVERTED_BCLK(pol)) 493 fat0 |= DA_BCP_INVERTED; 494 if (AUDIO_DAI_POLARITY_INVERTED_FRAME(pol)) 495 fat0 |= DA_LRCP_INVERTED; 496 } else { 497 if (AUDIO_DAI_POLARITY_INVERTED_BCLK(pol)) 498 fat0 |= DA_BCP_INVERTED; 499 if (!AUDIO_DAI_POLARITY_INVERTED_FRAME(pol)) 500 fat0 |= DA_LRCP_INVERTED; 501 502 fat0 &= ~DA_FAT0_LRCK_PERIOD_MASK; 503 fat0 |= DA_FAT0_LRCK_PERIOD(32 - 1); 504 } 505 506 I2S_WRITE(sc, DA_CTL, ctl); 507 I2S_WRITE(sc, DA_FAT0, fat0); 508 509 return (0); 510 } 511 512 513 static int 514 aw_i2s_dai_intr(device_t dev, struct snd_dbuf *play_buf, struct snd_dbuf *rec_buf) 515 { 516 struct aw_i2s_softc *sc; 517 int ret = 0; 518 uint32_t val, status; 519 520 sc = device_get_softc(dev); 521 522 I2S_LOCK(sc); 523 524 status = I2S_READ(sc, DA_ISTA); 525 /* Clear interrupts */ 526 // device_printf(sc->dev, "status: %08x\n", status); 527 I2S_WRITE(sc, DA_ISTA, status); 528 529 if (status & DA_ISTA_TXEI_INT) { 530 uint8_t *samples; 531 uint32_t count, size, readyptr, written, empty; 532 533 val = I2S_READ(sc, DA_FSTA); 534 empty = DA_FSTA_TXE_CNT(val); 535 count = sndbuf_getready(play_buf); 536 size = sndbuf_getsize(play_buf); 537 readyptr = sndbuf_getreadyptr(play_buf); 538 539 samples = (uint8_t*)sndbuf_getbuf(play_buf); 540 written = 0; 541 if (empty > count / 2) 542 empty = count / 2; 543 for (; empty > 0; empty--) { 544 val = (samples[readyptr++ % size] << 16); 545 val |= (samples[readyptr++ % size] << 24); 546 written += 2; 547 I2S_WRITE(sc, DA_TXFIFO, val); 548 } 549 sc->play_ptr += written; 550 sc->play_ptr %= size; 551 ret |= AUDIO_DAI_PLAY_INTR; 552 } 553 554 if (status & DA_ISTA_RXAI_INT) { 555 uint8_t *samples; 556 uint32_t count, size, freeptr, recorded, available; 557 558 val = I2S_READ(sc, DA_FSTA); 559 available = DA_FSTA_RXA_CNT(val); 560 561 count = sndbuf_getfree(rec_buf); 562 size = sndbuf_getsize(rec_buf); 563 freeptr = sndbuf_getfreeptr(rec_buf); 564 samples = (uint8_t*)sndbuf_getbuf(rec_buf); 565 recorded = 0; 566 if (available > count / 2) 567 available = count / 2; 568 569 for (; available > 0; available--) { 570 val = I2S_READ(sc, DA_RXFIFO); 571 samples[freeptr++ % size] = (val >> 16) & 0xff; 572 samples[freeptr++ % size] = (val >> 24) & 0xff; 573 recorded += 2; 574 } 575 sc->rec_ptr += recorded; 576 sc->rec_ptr %= size; 577 ret |= AUDIO_DAI_REC_INTR; 578 } 579 580 I2S_UNLOCK(sc); 581 582 return (ret); 583 } 584 585 static struct pcmchan_caps * 586 aw_i2s_dai_get_caps(device_t dev) 587 { 588 return (&aw_i2s_caps); 589 } 590 591 static int 592 aw_i2s_dai_trigger(device_t dev, int go, int pcm_dir) 593 { 594 struct aw_i2s_softc *sc = device_get_softc(dev); 595 uint32_t val; 596 597 if ((pcm_dir != PCMDIR_PLAY) && (pcm_dir != PCMDIR_REC)) 598 return (EINVAL); 599 600 switch (go) { 601 case PCMTRIG_START: 602 if (pcm_dir == PCMDIR_PLAY) { 603 /* Flush FIFO */ 604 val = I2S_READ(sc, DA_FCTL); 605 I2S_WRITE(sc, DA_FCTL, val | DA_FCTL_FTX); 606 I2S_WRITE(sc, DA_FCTL, val & ~DA_FCTL_FTX); 607 608 /* Reset TX sample counter */ 609 I2S_WRITE(sc, DA_TXCNT, 0); 610 611 /* Enable TX block */ 612 val = I2S_READ(sc, DA_CTL); 613 I2S_WRITE(sc, DA_CTL, val | DA_CTL_TXEN); 614 615 /* Enable TX underrun interrupt */ 616 val = I2S_READ(sc, DA_INT); 617 I2S_WRITE(sc, DA_INT, val | DA_INT_TXEI_EN); 618 } 619 620 if (pcm_dir == PCMDIR_REC) { 621 /* Flush FIFO */ 622 val = I2S_READ(sc, DA_FCTL); 623 I2S_WRITE(sc, DA_FCTL, val | DA_FCTL_FRX); 624 I2S_WRITE(sc, DA_FCTL, val & ~DA_FCTL_FRX); 625 626 /* Reset RX sample counter */ 627 I2S_WRITE(sc, DA_RXCNT, 0); 628 629 /* Enable RX block */ 630 val = I2S_READ(sc, DA_CTL); 631 I2S_WRITE(sc, DA_CTL, val | DA_CTL_RXEN); 632 633 /* Enable RX data available interrupt */ 634 val = I2S_READ(sc, DA_INT); 635 I2S_WRITE(sc, DA_INT, val | DA_INT_RXAI_EN); 636 } 637 638 break; 639 640 case PCMTRIG_STOP: 641 case PCMTRIG_ABORT: 642 I2S_LOCK(sc); 643 644 if (pcm_dir == PCMDIR_PLAY) { 645 /* Disable TX block */ 646 val = I2S_READ(sc, DA_CTL); 647 I2S_WRITE(sc, DA_CTL, val & ~DA_CTL_TXEN); 648 649 /* Enable TX underrun interrupt */ 650 val = I2S_READ(sc, DA_INT); 651 I2S_WRITE(sc, DA_INT, val & ~DA_INT_TXEI_EN); 652 653 sc->play_ptr = 0; 654 } else { 655 /* Disable RX block */ 656 val = I2S_READ(sc, DA_CTL); 657 I2S_WRITE(sc, DA_CTL, val & ~DA_CTL_RXEN); 658 659 /* Disable RX data available interrupt */ 660 val = I2S_READ(sc, DA_INT); 661 I2S_WRITE(sc, DA_INT, val & ~DA_INT_RXAI_EN); 662 663 sc->rec_ptr = 0; 664 } 665 666 I2S_UNLOCK(sc); 667 break; 668 } 669 670 return (0); 671 } 672 673 static uint32_t 674 aw_i2s_dai_get_ptr(device_t dev, int pcm_dir) 675 { 676 struct aw_i2s_softc *sc; 677 uint32_t ptr; 678 679 sc = device_get_softc(dev); 680 681 I2S_LOCK(sc); 682 if (pcm_dir == PCMDIR_PLAY) 683 ptr = sc->play_ptr; 684 else 685 ptr = sc->rec_ptr; 686 I2S_UNLOCK(sc); 687 688 return ptr; 689 } 690 691 static int 692 aw_i2s_dai_setup_intr(device_t dev, driver_intr_t intr_handler, void *intr_arg) 693 { 694 struct aw_i2s_softc *sc = device_get_softc(dev); 695 696 if (bus_setup_intr(dev, sc->res[1], 697 INTR_TYPE_MISC | INTR_MPSAFE, NULL, intr_handler, intr_arg, 698 &sc->intrhand)) { 699 device_printf(dev, "cannot setup interrupt handler\n"); 700 return (ENXIO); 701 } 702 703 return (0); 704 } 705 706 static uint32_t 707 aw_i2s_dai_set_chanformat(device_t dev, uint32_t format) 708 { 709 710 return (0); 711 } 712 713 static int 714 aw_i2s_dai_set_sysclk(device_t dev, unsigned int rate, int dai_dir) 715 { 716 struct aw_i2s_softc *sc; 717 int bclk_val, mclk_val; 718 uint32_t val; 719 int error; 720 721 sc = device_get_softc(dev); 722 723 error = clk_set_freq(sc->clk, AW_I2S_CLK_RATE, CLK_SET_ROUND_DOWN); 724 if (error != 0) { 725 device_printf(sc->dev, 726 "couldn't set mod clock rate to %u Hz: %d\n", AW_I2S_CLK_RATE, error); 727 return error; 728 } 729 error = clk_enable(sc->clk); 730 if (error != 0) { 731 device_printf(sc->dev, 732 "couldn't enable mod clock: %d\n", error); 733 return error; 734 } 735 736 const u_int bclk_prate = I2S_TYPE(sc) == SUNXI_I2S_SUN4I ? rate : AW_I2S_CLK_RATE; 737 738 const u_int bclk_div = bclk_prate / (2 * 32 * AW_I2S_SAMPLE_RATE); 739 const u_int mclk_div = AW_I2S_CLK_RATE / rate; 740 741 if (I2S_TYPE(sc) == SUNXI_I2S_SUN4I) { 742 bclk_val = sunxi_i2s_div_to_regval(sun4i_i2s_bclk_divmap, 743 nitems(sun4i_i2s_bclk_divmap), bclk_div); 744 mclk_val = sunxi_i2s_div_to_regval(sun4i_i2s_mclk_divmap, 745 nitems(sun4i_i2s_mclk_divmap), mclk_div); 746 } else { 747 bclk_val = sunxi_i2s_div_to_regval(sun8i_i2s_divmap, 748 nitems(sun8i_i2s_divmap), bclk_div); 749 mclk_val = sunxi_i2s_div_to_regval(sun8i_i2s_divmap, 750 nitems(sun8i_i2s_divmap), mclk_div); 751 } 752 if (bclk_val == -1 || mclk_val == -1) { 753 device_printf(sc->dev, "couldn't configure bclk/mclk dividers\n"); 754 return EIO; 755 } 756 757 val = I2S_READ(sc, DA_CLKD); 758 if (I2S_TYPE(sc) == SUNXI_I2S_SUN4I) { 759 val |= DA_CLKD_MCLKO_EN_SUN4I; 760 val &= ~DA_CLKD_BCLKDIV_SUN4I_MASK; 761 val |= DA_CLKD_BCLKDIV_SUN4I(bclk_val); 762 } else { 763 val |= DA_CLKD_MCLKO_EN_SUN8I; 764 val &= ~DA_CLKD_BCLKDIV_SUN8I_MASK; 765 val |= DA_CLKD_BCLKDIV_SUN8I(bclk_val); 766 } 767 val &= ~DA_CLKD_MCLKDIV_MASK; 768 val |= DA_CLKD_MCLKDIV(mclk_val); 769 I2S_WRITE(sc, DA_CLKD, val); 770 771 772 return (0); 773 } 774 775 static uint32_t 776 aw_i2s_dai_set_chanspeed(device_t dev, uint32_t speed) 777 { 778 779 return (speed); 780 } 781 782 static device_method_t aw_i2s_methods[] = { 783 /* Device interface */ 784 DEVMETHOD(device_probe, aw_i2s_probe), 785 DEVMETHOD(device_attach, aw_i2s_attach), 786 DEVMETHOD(device_detach, aw_i2s_detach), 787 788 DEVMETHOD(audio_dai_init, aw_i2s_dai_init), 789 DEVMETHOD(audio_dai_setup_intr, aw_i2s_dai_setup_intr), 790 DEVMETHOD(audio_dai_set_sysclk, aw_i2s_dai_set_sysclk), 791 DEVMETHOD(audio_dai_set_chanspeed, aw_i2s_dai_set_chanspeed), 792 DEVMETHOD(audio_dai_set_chanformat, aw_i2s_dai_set_chanformat), 793 DEVMETHOD(audio_dai_intr, aw_i2s_dai_intr), 794 DEVMETHOD(audio_dai_get_caps, aw_i2s_dai_get_caps), 795 DEVMETHOD(audio_dai_trigger, aw_i2s_dai_trigger), 796 DEVMETHOD(audio_dai_get_ptr, aw_i2s_dai_get_ptr), 797 798 DEVMETHOD_END 799 }; 800 801 static driver_t aw_i2s_driver = { 802 "i2s", 803 aw_i2s_methods, 804 sizeof(struct aw_i2s_softc), 805 }; 806 807 DRIVER_MODULE(aw_i2s, simplebus, aw_i2s_driver, 0, 0); 808 SIMPLEBUS_PNP_INFO(compat_data); 809