1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold@freebsd.org> 5 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 6 * Copyright (c) 2012 Luiz Otavio O Souza. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 38 #include <sys/kernel.h> 39 #include <sys/module.h> 40 #include <sys/rman.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <sys/gpio.h> 44 45 #include <machine/bus.h> 46 #include <machine/resource.h> 47 #include <machine/intr.h> 48 49 #include <dev/gpio/gpiobusvar.h> 50 #include <dev/ofw/ofw_bus.h> 51 #include <dev/ofw/ofw_bus_subr.h> 52 #include <dev/fdt/fdt_pinctrl.h> 53 54 #include <arm/allwinner/aw_machdep.h> 55 #include <arm/allwinner/allwinner_pinctrl.h> 56 #include <dev/extres/clk/clk.h> 57 #include <dev/extres/hwreset/hwreset.h> 58 59 #if defined(__aarch64__) 60 #include "opt_soc.h" 61 #endif 62 63 #include "gpio_if.h" 64 65 #define AW_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \ 66 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN) 67 68 #define AW_GPIO_NONE 0 69 #define AW_GPIO_PULLUP 1 70 #define AW_GPIO_PULLDOWN 2 71 72 #define AW_GPIO_INPUT 0 73 #define AW_GPIO_OUTPUT 1 74 75 #define AW_GPIO_DRV_MASK 0x3 76 #define AW_GPIO_PUD_MASK 0x3 77 78 #define AW_PINCTRL 1 79 #define AW_R_PINCTRL 2 80 81 /* Defined in aw_padconf.c */ 82 #ifdef SOC_ALLWINNER_A10 83 extern const struct allwinner_padconf a10_padconf; 84 #endif 85 86 /* Defined in a13_padconf.c */ 87 #ifdef SOC_ALLWINNER_A13 88 extern const struct allwinner_padconf a13_padconf; 89 #endif 90 91 /* Defined in a20_padconf.c */ 92 #ifdef SOC_ALLWINNER_A20 93 extern const struct allwinner_padconf a20_padconf; 94 #endif 95 96 /* Defined in a31_padconf.c */ 97 #ifdef SOC_ALLWINNER_A31 98 extern const struct allwinner_padconf a31_padconf; 99 #endif 100 101 /* Defined in a31s_padconf.c */ 102 #ifdef SOC_ALLWINNER_A31S 103 extern const struct allwinner_padconf a31s_padconf; 104 #endif 105 106 #if defined(SOC_ALLWINNER_A31) || defined(SOC_ALLWINNER_A31S) 107 extern const struct allwinner_padconf a31_r_padconf; 108 #endif 109 110 /* Defined in a33_padconf.c */ 111 #ifdef SOC_ALLWINNER_A33 112 extern const struct allwinner_padconf a33_padconf; 113 #endif 114 115 /* Defined in h3_padconf.c */ 116 #if defined(SOC_ALLWINNER_H3) || defined(SOC_ALLWINNER_H5) 117 extern const struct allwinner_padconf h3_padconf; 118 extern const struct allwinner_padconf h3_r_padconf; 119 #endif 120 121 /* Defined in a83t_padconf.c */ 122 #ifdef SOC_ALLWINNER_A83T 123 extern const struct allwinner_padconf a83t_padconf; 124 extern const struct allwinner_padconf a83t_r_padconf; 125 #endif 126 127 /* Defined in a64_padconf.c */ 128 #ifdef SOC_ALLWINNER_A64 129 extern const struct allwinner_padconf a64_padconf; 130 extern const struct allwinner_padconf a64_r_padconf; 131 #endif 132 133 static struct ofw_compat_data compat_data[] = { 134 #ifdef SOC_ALLWINNER_A10 135 {"allwinner,sun4i-a10-pinctrl", (uintptr_t)&a10_padconf}, 136 #endif 137 #ifdef SOC_ALLWINNER_A13 138 {"allwinner,sun5i-a13-pinctrl", (uintptr_t)&a13_padconf}, 139 #endif 140 #ifdef SOC_ALLWINNER_A20 141 {"allwinner,sun7i-a20-pinctrl", (uintptr_t)&a20_padconf}, 142 #endif 143 #ifdef SOC_ALLWINNER_A31 144 {"allwinner,sun6i-a31-pinctrl", (uintptr_t)&a31_padconf}, 145 #endif 146 #ifdef SOC_ALLWINNER_A31S 147 {"allwinner,sun6i-a31s-pinctrl", (uintptr_t)&a31s_padconf}, 148 #endif 149 #if defined(SOC_ALLWINNER_A31) || defined(SOC_ALLWINNER_A31S) 150 {"allwinner,sun6i-a31-r-pinctrl", (uintptr_t)&a31_r_padconf}, 151 #endif 152 #ifdef SOC_ALLWINNER_A33 153 {"allwinner,sun6i-a33-pinctrl", (uintptr_t)&a33_padconf}, 154 #endif 155 #ifdef SOC_ALLWINNER_A83T 156 {"allwinner,sun8i-a83t-pinctrl", (uintptr_t)&a83t_padconf}, 157 {"allwinner,sun8i-a83t-r-pinctrl", (uintptr_t)&a83t_r_padconf}, 158 #endif 159 #if defined(SOC_ALLWINNER_H3) || defined(SOC_ALLWINNER_H5) 160 {"allwinner,sun8i-h3-pinctrl", (uintptr_t)&h3_padconf}, 161 {"allwinner,sun50i-h5-pinctrl", (uintptr_t)&h3_padconf}, 162 {"allwinner,sun8i-h3-r-pinctrl", (uintptr_t)&h3_r_padconf}, 163 #endif 164 #ifdef SOC_ALLWINNER_A64 165 {"allwinner,sun50i-a64-pinctrl", (uintptr_t)&a64_padconf}, 166 {"allwinner,sun50i-a64-r-pinctrl", (uintptr_t)&a64_r_padconf}, 167 #endif 168 {NULL, 0} 169 }; 170 171 struct clk_list { 172 TAILQ_ENTRY(clk_list) next; 173 clk_t clk; 174 }; 175 176 struct aw_gpio_softc { 177 device_t sc_dev; 178 device_t sc_busdev; 179 struct mtx sc_mtx; 180 struct resource * sc_mem_res; 181 struct resource * sc_irq_res; 182 bus_space_tag_t sc_bst; 183 bus_space_handle_t sc_bsh; 184 void * sc_intrhand; 185 const struct allwinner_padconf * padconf; 186 TAILQ_HEAD(, clk_list) clk_list; 187 }; 188 189 #define AW_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx) 190 #define AW_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx) 191 #define AW_GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 192 193 #define AW_GPIO_GP_CFG(_bank, _idx) 0x00 + ((_bank) * 0x24) + ((_idx) << 2) 194 #define AW_GPIO_GP_DAT(_bank) 0x10 + ((_bank) * 0x24) 195 #define AW_GPIO_GP_DRV(_bank, _idx) 0x14 + ((_bank) * 0x24) + ((_idx) << 2) 196 #define AW_GPIO_GP_PUL(_bank, _idx) 0x1c + ((_bank) * 0x24) + ((_idx) << 2) 197 198 #define AW_GPIO_GP_INT_CFG0 0x200 199 #define AW_GPIO_GP_INT_CFG1 0x204 200 #define AW_GPIO_GP_INT_CFG2 0x208 201 #define AW_GPIO_GP_INT_CFG3 0x20c 202 203 #define AW_GPIO_GP_INT_CTL 0x210 204 #define AW_GPIO_GP_INT_STA 0x214 205 #define AW_GPIO_GP_INT_DEB 0x218 206 207 static char *aw_gpio_parse_function(phandle_t node); 208 static const char **aw_gpio_parse_pins(phandle_t node, int *pins_nb); 209 static uint32_t aw_gpio_parse_bias(phandle_t node); 210 static int aw_gpio_parse_drive_strength(phandle_t node, uint32_t *drive); 211 212 static int aw_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value); 213 static int aw_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value); 214 static int aw_gpio_pin_get_locked(struct aw_gpio_softc *sc, uint32_t pin, unsigned int *value); 215 static int aw_gpio_pin_set_locked(struct aw_gpio_softc *sc, uint32_t pin, unsigned int value); 216 217 #define AW_GPIO_WRITE(_sc, _off, _val) \ 218 bus_space_write_4(_sc->sc_bst, _sc->sc_bsh, _off, _val) 219 #define AW_GPIO_READ(_sc, _off) \ 220 bus_space_read_4(_sc->sc_bst, _sc->sc_bsh, _off) 221 222 static uint32_t 223 aw_gpio_get_function(struct aw_gpio_softc *sc, uint32_t pin) 224 { 225 uint32_t bank, func, offset; 226 227 /* Must be called with lock held. */ 228 AW_GPIO_LOCK_ASSERT(sc); 229 230 if (pin > sc->padconf->npins) 231 return (0); 232 bank = sc->padconf->pins[pin].port; 233 pin = sc->padconf->pins[pin].pin; 234 offset = ((pin & 0x07) << 2); 235 236 func = AW_GPIO_READ(sc, AW_GPIO_GP_CFG(bank, pin >> 3)); 237 238 return ((func >> offset) & 0x7); 239 } 240 241 static int 242 aw_gpio_set_function(struct aw_gpio_softc *sc, uint32_t pin, uint32_t f) 243 { 244 uint32_t bank, data, offset; 245 246 /* Check if the function exists in the padconf data */ 247 if (sc->padconf->pins[pin].functions[f] == NULL) 248 return (EINVAL); 249 250 /* Must be called with lock held. */ 251 AW_GPIO_LOCK_ASSERT(sc); 252 253 bank = sc->padconf->pins[pin].port; 254 pin = sc->padconf->pins[pin].pin; 255 offset = ((pin & 0x07) << 2); 256 257 data = AW_GPIO_READ(sc, AW_GPIO_GP_CFG(bank, pin >> 3)); 258 data &= ~(7 << offset); 259 data |= (f << offset); 260 AW_GPIO_WRITE(sc, AW_GPIO_GP_CFG(bank, pin >> 3), data); 261 262 return (0); 263 } 264 265 static uint32_t 266 aw_gpio_get_pud(struct aw_gpio_softc *sc, uint32_t pin) 267 { 268 uint32_t bank, offset, val; 269 270 /* Must be called with lock held. */ 271 AW_GPIO_LOCK_ASSERT(sc); 272 273 bank = sc->padconf->pins[pin].port; 274 pin = sc->padconf->pins[pin].pin; 275 offset = ((pin & 0x0f) << 1); 276 277 val = AW_GPIO_READ(sc, AW_GPIO_GP_PUL(bank, pin >> 4)); 278 279 return ((val >> offset) & AW_GPIO_PUD_MASK); 280 } 281 282 static void 283 aw_gpio_set_pud(struct aw_gpio_softc *sc, uint32_t pin, uint32_t state) 284 { 285 uint32_t bank, offset, val; 286 287 if (aw_gpio_get_pud(sc, pin) == state) 288 return; 289 290 /* Must be called with lock held. */ 291 AW_GPIO_LOCK_ASSERT(sc); 292 293 bank = sc->padconf->pins[pin].port; 294 pin = sc->padconf->pins[pin].pin; 295 offset = ((pin & 0x0f) << 1); 296 297 val = AW_GPIO_READ(sc, AW_GPIO_GP_PUL(bank, pin >> 4)); 298 val &= ~(AW_GPIO_PUD_MASK << offset); 299 val |= (state << offset); 300 AW_GPIO_WRITE(sc, AW_GPIO_GP_PUL(bank, pin >> 4), val); 301 } 302 303 static uint32_t 304 aw_gpio_get_drv(struct aw_gpio_softc *sc, uint32_t pin) 305 { 306 uint32_t bank, offset, val; 307 308 /* Must be called with lock held. */ 309 AW_GPIO_LOCK_ASSERT(sc); 310 311 bank = sc->padconf->pins[pin].port; 312 pin = sc->padconf->pins[pin].pin; 313 offset = ((pin & 0x0f) << 1); 314 315 val = AW_GPIO_READ(sc, AW_GPIO_GP_DRV(bank, pin >> 4)); 316 317 return ((val >> offset) & AW_GPIO_DRV_MASK); 318 } 319 320 static void 321 aw_gpio_set_drv(struct aw_gpio_softc *sc, uint32_t pin, uint32_t drive) 322 { 323 uint32_t bank, offset, val; 324 325 if (aw_gpio_get_drv(sc, pin) == drive) 326 return; 327 328 /* Must be called with lock held. */ 329 AW_GPIO_LOCK_ASSERT(sc); 330 331 bank = sc->padconf->pins[pin].port; 332 pin = sc->padconf->pins[pin].pin; 333 offset = ((pin & 0x0f) << 1); 334 335 val = AW_GPIO_READ(sc, AW_GPIO_GP_DRV(bank, pin >> 4)); 336 val &= ~(AW_GPIO_DRV_MASK << offset); 337 val |= (drive << offset); 338 AW_GPIO_WRITE(sc, AW_GPIO_GP_DRV(bank, pin >> 4), val); 339 } 340 341 static int 342 aw_gpio_pin_configure(struct aw_gpio_softc *sc, uint32_t pin, uint32_t flags) 343 { 344 u_int val; 345 int err = 0; 346 347 /* Must be called with lock held. */ 348 AW_GPIO_LOCK_ASSERT(sc); 349 350 if (pin > sc->padconf->npins) 351 return (EINVAL); 352 353 /* Manage input/output. */ 354 if (flags & GPIO_PIN_INPUT) { 355 err = aw_gpio_set_function(sc, pin, AW_GPIO_INPUT); 356 } else if ((flags & GPIO_PIN_OUTPUT) && 357 aw_gpio_get_function(sc, pin) != AW_GPIO_OUTPUT) { 358 if (flags & GPIO_PIN_PRESET_LOW) { 359 aw_gpio_pin_set_locked(sc, pin, 0); 360 } else if (flags & GPIO_PIN_PRESET_HIGH) { 361 aw_gpio_pin_set_locked(sc, pin, 1); 362 } else { 363 /* Read the pin and preset output to current state. */ 364 err = aw_gpio_set_function(sc, pin, AW_GPIO_INPUT); 365 if (err == 0) { 366 aw_gpio_pin_get_locked(sc, pin, &val); 367 aw_gpio_pin_set_locked(sc, pin, val); 368 } 369 } 370 if (err == 0) 371 err = aw_gpio_set_function(sc, pin, AW_GPIO_OUTPUT); 372 } 373 374 if (err) 375 return (err); 376 377 /* Manage Pull-up/pull-down. */ 378 if (flags & GPIO_PIN_PULLUP) 379 aw_gpio_set_pud(sc, pin, AW_GPIO_PULLUP); 380 else if (flags & GPIO_PIN_PULLDOWN) 381 aw_gpio_set_pud(sc, pin, AW_GPIO_PULLDOWN); 382 else 383 aw_gpio_set_pud(sc, pin, AW_GPIO_NONE); 384 385 return (0); 386 } 387 388 static device_t 389 aw_gpio_get_bus(device_t dev) 390 { 391 struct aw_gpio_softc *sc; 392 393 sc = device_get_softc(dev); 394 395 return (sc->sc_busdev); 396 } 397 398 static int 399 aw_gpio_pin_max(device_t dev, int *maxpin) 400 { 401 struct aw_gpio_softc *sc; 402 403 sc = device_get_softc(dev); 404 405 *maxpin = sc->padconf->npins - 1; 406 return (0); 407 } 408 409 static int 410 aw_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 411 { 412 struct aw_gpio_softc *sc; 413 414 sc = device_get_softc(dev); 415 if (pin >= sc->padconf->npins) 416 return (EINVAL); 417 418 *caps = AW_GPIO_DEFAULT_CAPS; 419 420 return (0); 421 } 422 423 static int 424 aw_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 425 { 426 struct aw_gpio_softc *sc; 427 uint32_t func; 428 uint32_t pud; 429 430 sc = device_get_softc(dev); 431 if (pin >= sc->padconf->npins) 432 return (EINVAL); 433 434 AW_GPIO_LOCK(sc); 435 func = aw_gpio_get_function(sc, pin); 436 switch (func) { 437 case AW_GPIO_INPUT: 438 *flags = GPIO_PIN_INPUT; 439 break; 440 case AW_GPIO_OUTPUT: 441 *flags = GPIO_PIN_OUTPUT; 442 break; 443 default: 444 *flags = 0; 445 break; 446 } 447 448 pud = aw_gpio_get_pud(sc, pin); 449 switch (pud) { 450 case AW_GPIO_PULLDOWN: 451 *flags |= GPIO_PIN_PULLDOWN; 452 break; 453 case AW_GPIO_PULLUP: 454 *flags |= GPIO_PIN_PULLUP; 455 break; 456 default: 457 break; 458 } 459 460 AW_GPIO_UNLOCK(sc); 461 462 return (0); 463 } 464 465 static int 466 aw_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 467 { 468 struct aw_gpio_softc *sc; 469 470 sc = device_get_softc(dev); 471 if (pin >= sc->padconf->npins) 472 return (EINVAL); 473 474 snprintf(name, GPIOMAXNAME - 1, "%s", 475 sc->padconf->pins[pin].name); 476 name[GPIOMAXNAME - 1] = '\0'; 477 478 return (0); 479 } 480 481 static int 482 aw_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 483 { 484 struct aw_gpio_softc *sc; 485 int err; 486 487 sc = device_get_softc(dev); 488 if (pin > sc->padconf->npins) 489 return (EINVAL); 490 491 AW_GPIO_LOCK(sc); 492 err = aw_gpio_pin_configure(sc, pin, flags); 493 AW_GPIO_UNLOCK(sc); 494 495 return (err); 496 } 497 498 static int 499 aw_gpio_pin_set_locked(struct aw_gpio_softc *sc, uint32_t pin, 500 unsigned int value) 501 { 502 uint32_t bank, data; 503 504 AW_GPIO_LOCK_ASSERT(sc); 505 506 if (pin > sc->padconf->npins) 507 return (EINVAL); 508 509 bank = sc->padconf->pins[pin].port; 510 pin = sc->padconf->pins[pin].pin; 511 512 data = AW_GPIO_READ(sc, AW_GPIO_GP_DAT(bank)); 513 if (value) 514 data |= (1 << pin); 515 else 516 data &= ~(1 << pin); 517 AW_GPIO_WRITE(sc, AW_GPIO_GP_DAT(bank), data); 518 519 return (0); 520 } 521 522 static int 523 aw_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 524 { 525 struct aw_gpio_softc *sc; 526 int ret; 527 528 sc = device_get_softc(dev); 529 530 AW_GPIO_LOCK(sc); 531 ret = aw_gpio_pin_set_locked(sc, pin, value); 532 AW_GPIO_UNLOCK(sc); 533 534 return (ret); 535 } 536 537 static int 538 aw_gpio_pin_get_locked(struct aw_gpio_softc *sc,uint32_t pin, 539 unsigned int *val) 540 { 541 uint32_t bank, reg_data; 542 543 AW_GPIO_LOCK_ASSERT(sc); 544 545 if (pin > sc->padconf->npins) 546 return (EINVAL); 547 548 bank = sc->padconf->pins[pin].port; 549 pin = sc->padconf->pins[pin].pin; 550 551 reg_data = AW_GPIO_READ(sc, AW_GPIO_GP_DAT(bank)); 552 *val = (reg_data & (1 << pin)) ? 1 : 0; 553 554 return (0); 555 } 556 557 static char * 558 aw_gpio_parse_function(phandle_t node) 559 { 560 char *function; 561 562 if (OF_getprop_alloc(node, "function", sizeof(*function), 563 (void **)&function) != -1) 564 return (function); 565 if (OF_getprop_alloc(node, "allwinner,function", sizeof(*function), 566 (void **)&function) != -1) 567 return (function); 568 569 return (NULL); 570 } 571 572 static const char ** 573 aw_gpio_parse_pins(phandle_t node, int *pins_nb) 574 { 575 const char **pinlist; 576 577 *pins_nb = ofw_bus_string_list_to_array(node, "pins", &pinlist); 578 if (*pins_nb > 0) 579 return (pinlist); 580 581 *pins_nb = ofw_bus_string_list_to_array(node, "allwinner,pins", 582 &pinlist); 583 if (*pins_nb > 0) 584 return (pinlist); 585 586 return (NULL); 587 } 588 589 static uint32_t 590 aw_gpio_parse_bias(phandle_t node) 591 { 592 uint32_t bias; 593 594 if (OF_getencprop(node, "pull", &bias, sizeof(bias)) != -1) 595 return (bias); 596 if (OF_getencprop(node, "allwinner,pull", &bias, sizeof(bias)) != -1) 597 return (bias); 598 if (OF_hasprop(node, "bias-disable")) 599 return (AW_GPIO_NONE); 600 if (OF_hasprop(node, "bias-pull-up")) 601 return (AW_GPIO_PULLUP); 602 if (OF_hasprop(node, "bias-pull-down")) 603 return (AW_GPIO_PULLDOWN); 604 605 return (AW_GPIO_NONE); 606 } 607 608 static int 609 aw_gpio_parse_drive_strength(phandle_t node, uint32_t *drive) 610 { 611 uint32_t drive_str; 612 613 if (OF_getencprop(node, "drive", drive, sizeof(*drive)) != -1) 614 return (0); 615 if (OF_getencprop(node, "allwinner,drive", drive, sizeof(*drive)) != -1) 616 return (0); 617 if (OF_getencprop(node, "drive-strength", &drive_str, 618 sizeof(drive_str)) != -1) { 619 *drive = (drive_str / 10) - 1; 620 return (0); 621 } 622 623 return (1); 624 } 625 626 static int 627 aw_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) 628 { 629 struct aw_gpio_softc *sc; 630 int ret; 631 632 sc = device_get_softc(dev); 633 634 AW_GPIO_LOCK(sc); 635 ret = aw_gpio_pin_get_locked(sc, pin, val); 636 AW_GPIO_UNLOCK(sc); 637 638 return (ret); 639 } 640 641 static int 642 aw_gpio_pin_toggle(device_t dev, uint32_t pin) 643 { 644 struct aw_gpio_softc *sc; 645 uint32_t bank, data; 646 647 sc = device_get_softc(dev); 648 if (pin > sc->padconf->npins) 649 return (EINVAL); 650 651 bank = sc->padconf->pins[pin].port; 652 pin = sc->padconf->pins[pin].pin; 653 654 AW_GPIO_LOCK(sc); 655 data = AW_GPIO_READ(sc, AW_GPIO_GP_DAT(bank)); 656 if (data & (1 << pin)) 657 data &= ~(1 << pin); 658 else 659 data |= (1 << pin); 660 AW_GPIO_WRITE(sc, AW_GPIO_GP_DAT(bank), data); 661 AW_GPIO_UNLOCK(sc); 662 663 return (0); 664 } 665 666 static int 667 aw_gpio_pin_access_32(device_t dev, uint32_t first_pin, uint32_t clear_pins, 668 uint32_t change_pins, uint32_t *orig_pins) 669 { 670 struct aw_gpio_softc *sc; 671 uint32_t bank, data, pin; 672 673 sc = device_get_softc(dev); 674 if (first_pin > sc->padconf->npins) 675 return (EINVAL); 676 677 /* 678 * We require that first_pin refers to the first pin in a bank, because 679 * this API is not about convenience, it's for making a set of pins 680 * change simultaneously (required) with reasonably high performance 681 * (desired); we need to do a read-modify-write on a single register. 682 */ 683 bank = sc->padconf->pins[first_pin].port; 684 pin = sc->padconf->pins[first_pin].pin; 685 if (pin != 0) 686 return (EINVAL); 687 688 AW_GPIO_LOCK(sc); 689 data = AW_GPIO_READ(sc, AW_GPIO_GP_DAT(bank)); 690 if ((clear_pins | change_pins) != 0) 691 AW_GPIO_WRITE(sc, AW_GPIO_GP_DAT(bank), 692 (data & ~clear_pins) ^ change_pins); 693 AW_GPIO_UNLOCK(sc); 694 695 if (orig_pins != NULL) 696 *orig_pins = data; 697 698 return (0); 699 } 700 701 static int 702 aw_gpio_pin_config_32(device_t dev, uint32_t first_pin, uint32_t num_pins, 703 uint32_t *pin_flags) 704 { 705 struct aw_gpio_softc *sc; 706 uint32_t bank, pin; 707 int err; 708 709 sc = device_get_softc(dev); 710 if (first_pin > sc->padconf->npins) 711 return (EINVAL); 712 713 bank = sc->padconf->pins[first_pin].port; 714 if (sc->padconf->pins[first_pin].pin != 0) 715 return (EINVAL); 716 717 /* 718 * The configuration for a bank of pins is scattered among several 719 * registers; we cannot g'tee to simultaneously change the state of all 720 * the pins in the flags array. So just loop through the array 721 * configuring each pin for now. If there was a strong need, it might 722 * be possible to support some limited simultaneous config, such as 723 * adjacent groups of 8 pins that line up the same as the config regs. 724 */ 725 for (err = 0, pin = first_pin; err == 0 && pin < num_pins; ++pin) { 726 if (pin_flags[pin] & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) 727 err = aw_gpio_pin_configure(sc, pin, pin_flags[pin]); 728 } 729 730 return (err); 731 } 732 733 static int 734 aw_find_pinnum_by_name(struct aw_gpio_softc *sc, const char *pinname) 735 { 736 int i; 737 738 for (i = 0; i < sc->padconf->npins; i++) 739 if (!strcmp(pinname, sc->padconf->pins[i].name)) 740 return i; 741 742 return (-1); 743 } 744 745 static int 746 aw_find_pin_func(struct aw_gpio_softc *sc, int pin, const char *func) 747 { 748 int i; 749 750 for (i = 0; i < AW_MAX_FUNC_BY_PIN; i++) 751 if (sc->padconf->pins[pin].functions[i] && 752 !strcmp(func, sc->padconf->pins[pin].functions[i])) 753 return (i); 754 755 return (-1); 756 } 757 758 static int 759 aw_fdt_configure_pins(device_t dev, phandle_t cfgxref) 760 { 761 struct aw_gpio_softc *sc; 762 phandle_t node; 763 const char **pinlist = NULL; 764 char *pin_function = NULL; 765 uint32_t pin_drive, pin_pull; 766 int pins_nb, pin_num, pin_func, i, ret; 767 bool set_drive; 768 769 sc = device_get_softc(dev); 770 node = OF_node_from_xref(cfgxref); 771 ret = 0; 772 set_drive = false; 773 774 /* Getting all prop for configuring pins */ 775 pinlist = aw_gpio_parse_pins(node, &pins_nb); 776 if (pinlist == NULL) 777 return (ENOENT); 778 779 pin_function = aw_gpio_parse_function(node); 780 if (pin_function == NULL) { 781 ret = ENOENT; 782 goto out; 783 } 784 785 if (aw_gpio_parse_drive_strength(node, &pin_drive) == 0) 786 set_drive = true; 787 788 pin_pull = aw_gpio_parse_bias(node); 789 790 /* Configure each pin to the correct function, drive and pull */ 791 for (i = 0; i < pins_nb; i++) { 792 pin_num = aw_find_pinnum_by_name(sc, pinlist[i]); 793 if (pin_num == -1) { 794 ret = ENOENT; 795 goto out; 796 } 797 pin_func = aw_find_pin_func(sc, pin_num, pin_function); 798 if (pin_func == -1) { 799 ret = ENOENT; 800 goto out; 801 } 802 803 AW_GPIO_LOCK(sc); 804 805 if (aw_gpio_get_function(sc, pin_num) != pin_func) 806 aw_gpio_set_function(sc, pin_num, pin_func); 807 if (set_drive) 808 aw_gpio_set_drv(sc, pin_num, pin_drive); 809 if (pin_pull != AW_GPIO_NONE) 810 aw_gpio_set_pud(sc, pin_num, pin_pull); 811 812 AW_GPIO_UNLOCK(sc); 813 } 814 815 out: 816 OF_prop_free(pinlist); 817 OF_prop_free(pin_function); 818 return (ret); 819 } 820 821 static int 822 aw_gpio_probe(device_t dev) 823 { 824 825 if (!ofw_bus_status_okay(dev)) 826 return (ENXIO); 827 828 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 829 return (ENXIO); 830 831 device_set_desc(dev, "Allwinner GPIO/Pinmux controller"); 832 return (BUS_PROBE_DEFAULT); 833 } 834 835 static int 836 aw_gpio_attach(device_t dev) 837 { 838 int rid, error; 839 phandle_t gpio; 840 struct aw_gpio_softc *sc; 841 struct clk_list *clkp, *clkp_tmp; 842 clk_t clk; 843 hwreset_t rst = NULL; 844 int off, err, clkret; 845 846 sc = device_get_softc(dev); 847 sc->sc_dev = dev; 848 849 mtx_init(&sc->sc_mtx, "aw gpio", "gpio", MTX_SPIN); 850 851 rid = 0; 852 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 853 RF_ACTIVE); 854 if (!sc->sc_mem_res) { 855 device_printf(dev, "cannot allocate memory window\n"); 856 goto fail; 857 } 858 859 sc->sc_bst = rman_get_bustag(sc->sc_mem_res); 860 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); 861 862 rid = 0; 863 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 864 RF_ACTIVE); 865 if (!sc->sc_irq_res) { 866 device_printf(dev, "cannot allocate interrupt\n"); 867 goto fail; 868 } 869 870 /* Find our node. */ 871 gpio = ofw_bus_get_node(sc->sc_dev); 872 if (!OF_hasprop(gpio, "gpio-controller")) 873 /* Node is not a GPIO controller. */ 874 goto fail; 875 876 /* Use the right pin data for the current SoC */ 877 sc->padconf = (struct allwinner_padconf *)ofw_bus_search_compatible(dev, 878 compat_data)->ocd_data; 879 880 if (hwreset_get_by_ofw_idx(dev, 0, 0, &rst) == 0) { 881 error = hwreset_deassert(rst); 882 if (error != 0) { 883 device_printf(dev, "cannot de-assert reset\n"); 884 goto fail; 885 } 886 } 887 888 TAILQ_INIT(&sc->clk_list); 889 for (off = 0, clkret = 0; clkret == 0; off++) { 890 clkret = clk_get_by_ofw_index(dev, 0, off, &clk); 891 if (clkret != 0) 892 break; 893 err = clk_enable(clk); 894 if (err != 0) { 895 device_printf(dev, "Could not enable clock %s\n", 896 clk_get_name(clk)); 897 goto fail; 898 } 899 clkp = malloc(sizeof(*clkp), M_DEVBUF, M_WAITOK | M_ZERO); 900 clkp->clk = clk; 901 TAILQ_INSERT_TAIL(&sc->clk_list, clkp, next); 902 } 903 if (clkret != 0 && clkret != ENOENT) { 904 device_printf(dev, "Could not find clock at offset %d (%d)\n", 905 off, clkret); 906 goto fail; 907 } 908 909 sc->sc_busdev = gpiobus_attach_bus(dev); 910 if (sc->sc_busdev == NULL) 911 goto fail; 912 913 /* 914 * Register as a pinctrl device 915 */ 916 fdt_pinctrl_register(dev, "pins"); 917 fdt_pinctrl_configure_tree(dev); 918 fdt_pinctrl_register(dev, "allwinner,pins"); 919 fdt_pinctrl_configure_tree(dev); 920 921 return (0); 922 923 fail: 924 if (sc->sc_irq_res) 925 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 926 if (sc->sc_mem_res) 927 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 928 mtx_destroy(&sc->sc_mtx); 929 930 /* Disable clock */ 931 TAILQ_FOREACH_SAFE(clkp, &sc->clk_list, next, clkp_tmp) { 932 err = clk_disable(clkp->clk); 933 if (err != 0) 934 device_printf(dev, "Could not disable clock %s\n", 935 clk_get_name(clkp->clk)); 936 err = clk_release(clkp->clk); 937 if (err != 0) 938 device_printf(dev, "Could not release clock %s\n", 939 clk_get_name(clkp->clk)); 940 TAILQ_REMOVE(&sc->clk_list, clkp, next); 941 free(clkp, M_DEVBUF); 942 } 943 944 /* Assert resets */ 945 if (rst) { 946 hwreset_assert(rst); 947 hwreset_release(rst); 948 } 949 950 return (ENXIO); 951 } 952 953 static int 954 aw_gpio_detach(device_t dev) 955 { 956 957 return (EBUSY); 958 } 959 960 static phandle_t 961 aw_gpio_get_node(device_t dev, device_t bus) 962 { 963 964 /* We only have one child, the GPIO bus, which needs our own node. */ 965 return (ofw_bus_get_node(dev)); 966 } 967 968 static int 969 aw_gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, int gcells, 970 pcell_t *gpios, uint32_t *pin, uint32_t *flags) 971 { 972 struct aw_gpio_softc *sc; 973 int i; 974 975 sc = device_get_softc(bus); 976 977 /* The GPIO pins are mapped as: <gpio-phandle bank pin flags>. */ 978 for (i = 0; i < sc->padconf->npins; i++) 979 if (sc->padconf->pins[i].port == gpios[0] && 980 sc->padconf->pins[i].pin == gpios[1]) { 981 *pin = i; 982 break; 983 } 984 *flags = gpios[gcells - 1]; 985 986 return (0); 987 } 988 989 static device_method_t aw_gpio_methods[] = { 990 /* Device interface */ 991 DEVMETHOD(device_probe, aw_gpio_probe), 992 DEVMETHOD(device_attach, aw_gpio_attach), 993 DEVMETHOD(device_detach, aw_gpio_detach), 994 995 /* GPIO protocol */ 996 DEVMETHOD(gpio_get_bus, aw_gpio_get_bus), 997 DEVMETHOD(gpio_pin_max, aw_gpio_pin_max), 998 DEVMETHOD(gpio_pin_getname, aw_gpio_pin_getname), 999 DEVMETHOD(gpio_pin_getflags, aw_gpio_pin_getflags), 1000 DEVMETHOD(gpio_pin_getcaps, aw_gpio_pin_getcaps), 1001 DEVMETHOD(gpio_pin_setflags, aw_gpio_pin_setflags), 1002 DEVMETHOD(gpio_pin_get, aw_gpio_pin_get), 1003 DEVMETHOD(gpio_pin_set, aw_gpio_pin_set), 1004 DEVMETHOD(gpio_pin_toggle, aw_gpio_pin_toggle), 1005 DEVMETHOD(gpio_pin_access_32, aw_gpio_pin_access_32), 1006 DEVMETHOD(gpio_pin_config_32, aw_gpio_pin_config_32), 1007 DEVMETHOD(gpio_map_gpios, aw_gpio_map_gpios), 1008 1009 /* ofw_bus interface */ 1010 DEVMETHOD(ofw_bus_get_node, aw_gpio_get_node), 1011 1012 /* fdt_pinctrl interface */ 1013 DEVMETHOD(fdt_pinctrl_configure,aw_fdt_configure_pins), 1014 1015 DEVMETHOD_END 1016 }; 1017 1018 static devclass_t aw_gpio_devclass; 1019 1020 static driver_t aw_gpio_driver = { 1021 "gpio", 1022 aw_gpio_methods, 1023 sizeof(struct aw_gpio_softc), 1024 }; 1025 1026 EARLY_DRIVER_MODULE(aw_gpio, simplebus, aw_gpio_driver, aw_gpio_devclass, 0, 0, 1027 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE); 1028