1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold@freebsd.org> 5 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 6 * Copyright (c) 2012 Luiz Otavio O Souza. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 38 #include <sys/kernel.h> 39 #include <sys/module.h> 40 #include <sys/rman.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <sys/gpio.h> 44 45 #include <machine/bus.h> 46 #include <machine/resource.h> 47 #include <machine/intr.h> 48 49 #include <dev/gpio/gpiobusvar.h> 50 #include <dev/ofw/ofw_bus.h> 51 #include <dev/ofw/ofw_bus_subr.h> 52 #include <dev/fdt/fdt_pinctrl.h> 53 54 #include <arm/allwinner/aw_machdep.h> 55 #include <arm/allwinner/allwinner_pinctrl.h> 56 #include <dev/extres/clk/clk.h> 57 #include <dev/extres/hwreset/hwreset.h> 58 #include <dev/extres/regulator/regulator.h> 59 60 #if defined(__aarch64__) 61 #include "opt_soc.h" 62 #endif 63 64 #include "gpio_if.h" 65 66 #define AW_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \ 67 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN) 68 69 #define AW_GPIO_NONE 0 70 #define AW_GPIO_PULLUP 1 71 #define AW_GPIO_PULLDOWN 2 72 73 #define AW_GPIO_INPUT 0 74 #define AW_GPIO_OUTPUT 1 75 76 #define AW_GPIO_DRV_MASK 0x3 77 #define AW_GPIO_PUD_MASK 0x3 78 79 #define AW_PINCTRL 1 80 #define AW_R_PINCTRL 2 81 82 struct aw_gpio_conf { 83 struct allwinner_padconf *padconf; 84 const char *banks; 85 }; 86 87 /* Defined in aw_padconf.c */ 88 #ifdef SOC_ALLWINNER_A10 89 extern struct allwinner_padconf a10_padconf; 90 struct aw_gpio_conf a10_gpio_conf = { 91 .padconf = &a10_padconf, 92 .banks = "abcdefghi", 93 }; 94 #endif 95 96 /* Defined in a13_padconf.c */ 97 #ifdef SOC_ALLWINNER_A13 98 extern struct allwinner_padconf a13_padconf; 99 struct aw_gpio_conf a13_gpio_conf = { 100 .padconf = &a13_padconf, 101 .banks = "bcdefg", 102 }; 103 #endif 104 105 /* Defined in a20_padconf.c */ 106 #ifdef SOC_ALLWINNER_A20 107 extern struct allwinner_padconf a20_padconf; 108 struct aw_gpio_conf a20_gpio_conf = { 109 .padconf = &a20_padconf, 110 .banks = "abcdefghi", 111 }; 112 #endif 113 114 /* Defined in a31_padconf.c */ 115 #ifdef SOC_ALLWINNER_A31 116 extern struct allwinner_padconf a31_padconf; 117 struct aw_gpio_conf a31_gpio_conf = { 118 .padconf = &a31_padconf, 119 .banks = "abcdefgh", 120 }; 121 #endif 122 123 /* Defined in a31s_padconf.c */ 124 #ifdef SOC_ALLWINNER_A31S 125 extern struct allwinner_padconf a31s_padconf; 126 struct aw_gpio_conf a31s_gpio_conf = { 127 .padconf = &a31s_padconf, 128 .banks = "abcdefgh", 129 }; 130 #endif 131 132 #if defined(SOC_ALLWINNER_A31) || defined(SOC_ALLWINNER_A31S) 133 extern struct allwinner_padconf a31_r_padconf; 134 struct aw_gpio_conf a31_r_gpio_conf = { 135 .padconf = &a31_r_padconf, 136 .banks = "lm", 137 }; 138 #endif 139 140 /* Defined in a33_padconf.c */ 141 #ifdef SOC_ALLWINNER_A33 142 extern struct allwinner_padconf a33_padconf; 143 struct aw_gpio_conf a33_gpio_conf = { 144 .padconf = &a33_padconf, 145 .banks = "bcdefgh", 146 }; 147 #endif 148 149 /* Defined in h3_padconf.c */ 150 #if defined(SOC_ALLWINNER_H3) || defined(SOC_ALLWINNER_H5) 151 extern struct allwinner_padconf h3_padconf; 152 extern struct allwinner_padconf h3_r_padconf; 153 struct aw_gpio_conf h3_gpio_conf = { 154 .padconf = &h3_padconf, 155 .banks = "acdefg", 156 }; 157 struct aw_gpio_conf h3_r_gpio_conf = { 158 .padconf = &h3_r_padconf, 159 .banks = "l", 160 }; 161 #endif 162 163 /* Defined in a83t_padconf.c */ 164 #ifdef SOC_ALLWINNER_A83T 165 extern struct allwinner_padconf a83t_padconf; 166 extern struct allwinner_padconf a83t_r_padconf; 167 struct aw_gpio_conf a83t_gpio_conf = { 168 .padconf = &a83t_padconf, 169 .banks = "bcdefgh" 170 }; 171 struct aw_gpio_conf a83t_r_gpio_conf = { 172 .padconf = &a83t_r_padconf, 173 .banks = "l", 174 }; 175 #endif 176 177 /* Defined in a64_padconf.c */ 178 #ifdef SOC_ALLWINNER_A64 179 extern struct allwinner_padconf a64_padconf; 180 extern struct allwinner_padconf a64_r_padconf; 181 struct aw_gpio_conf a64_gpio_conf = { 182 .padconf = &a64_padconf, 183 .banks = "bcdefgh", 184 }; 185 struct aw_gpio_conf a64_r_gpio_conf = { 186 .padconf = &a64_r_padconf, 187 .banks = "l", 188 }; 189 #endif 190 191 /* Defined in h6_padconf.c */ 192 #ifdef SOC_ALLWINNER_H6 193 extern struct allwinner_padconf h6_padconf; 194 extern struct allwinner_padconf h6_r_padconf; 195 struct aw_gpio_conf h6_gpio_conf = { 196 .padconf = &h6_padconf, 197 .banks = "cdfgh", 198 }; 199 struct aw_gpio_conf h6_r_gpio_conf = { 200 .padconf = &h6_r_padconf, 201 .banks = "lm", 202 }; 203 #endif 204 205 static struct ofw_compat_data compat_data[] = { 206 #ifdef SOC_ALLWINNER_A10 207 {"allwinner,sun4i-a10-pinctrl", (uintptr_t)&a10_gpio_conf}, 208 #endif 209 #ifdef SOC_ALLWINNER_A13 210 {"allwinner,sun5i-a13-pinctrl", (uintptr_t)&a13_gpio_conf}, 211 #endif 212 #ifdef SOC_ALLWINNER_A20 213 {"allwinner,sun7i-a20-pinctrl", (uintptr_t)&a20_gpio_conf}, 214 #endif 215 #ifdef SOC_ALLWINNER_A31 216 {"allwinner,sun6i-a31-pinctrl", (uintptr_t)&a31_gpio_conf}, 217 #endif 218 #ifdef SOC_ALLWINNER_A31S 219 {"allwinner,sun6i-a31s-pinctrl", (uintptr_t)&a31s_gpio_conf}, 220 #endif 221 #if defined(SOC_ALLWINNER_A31) || defined(SOC_ALLWINNER_A31S) 222 {"allwinner,sun6i-a31-r-pinctrl", (uintptr_t)&a31_r_gpio_conf}, 223 #endif 224 #ifdef SOC_ALLWINNER_A33 225 {"allwinner,sun6i-a33-pinctrl", (uintptr_t)&a33_gpio_conf}, 226 #endif 227 #ifdef SOC_ALLWINNER_A83T 228 {"allwinner,sun8i-a83t-pinctrl", (uintptr_t)&a83t_gpio_conf}, 229 {"allwinner,sun8i-a83t-r-pinctrl", (uintptr_t)&a83t_r_gpio_conf}, 230 #endif 231 #if defined(SOC_ALLWINNER_H3) || defined(SOC_ALLWINNER_H5) 232 {"allwinner,sun8i-h3-pinctrl", (uintptr_t)&h3_gpio_conf}, 233 {"allwinner,sun50i-h5-pinctrl", (uintptr_t)&h3_gpio_conf}, 234 {"allwinner,sun8i-h3-r-pinctrl", (uintptr_t)&h3_r_gpio_conf}, 235 #endif 236 #ifdef SOC_ALLWINNER_A64 237 {"allwinner,sun50i-a64-pinctrl", (uintptr_t)&a64_gpio_conf}, 238 {"allwinner,sun50i-a64-r-pinctrl", (uintptr_t)&a64_r_gpio_conf}, 239 #endif 240 #ifdef SOC_ALLWINNER_H6 241 {"allwinner,sun50i-h6-pinctrl", (uintptr_t)&h6_gpio_conf}, 242 {"allwinner,sun50i-h6-r-pinctrl", (uintptr_t)&h6_r_gpio_conf}, 243 #endif 244 {NULL, 0} 245 }; 246 247 struct clk_list { 248 TAILQ_ENTRY(clk_list) next; 249 clk_t clk; 250 }; 251 252 struct aw_gpio_softc { 253 device_t sc_dev; 254 device_t sc_busdev; 255 struct mtx sc_mtx; 256 struct resource * sc_mem_res; 257 struct resource * sc_irq_res; 258 bus_space_tag_t sc_bst; 259 bus_space_handle_t sc_bsh; 260 void * sc_intrhand; 261 struct aw_gpio_conf *conf; 262 TAILQ_HEAD(, clk_list) clk_list; 263 }; 264 265 #define AW_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx) 266 #define AW_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx) 267 #define AW_GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 268 269 #define AW_GPIO_GP_CFG(_bank, _idx) 0x00 + ((_bank) * 0x24) + ((_idx) << 2) 270 #define AW_GPIO_GP_DAT(_bank) 0x10 + ((_bank) * 0x24) 271 #define AW_GPIO_GP_DRV(_bank, _idx) 0x14 + ((_bank) * 0x24) + ((_idx) << 2) 272 #define AW_GPIO_GP_PUL(_bank, _idx) 0x1c + ((_bank) * 0x24) + ((_idx) << 2) 273 274 #define AW_GPIO_GP_INT_CFG0 0x200 275 #define AW_GPIO_GP_INT_CFG1 0x204 276 #define AW_GPIO_GP_INT_CFG2 0x208 277 #define AW_GPIO_GP_INT_CFG3 0x20c 278 279 #define AW_GPIO_GP_INT_CTL 0x210 280 #define AW_GPIO_GP_INT_STA 0x214 281 #define AW_GPIO_GP_INT_DEB 0x218 282 283 static char *aw_gpio_parse_function(phandle_t node); 284 static const char **aw_gpio_parse_pins(phandle_t node, int *pins_nb); 285 static uint32_t aw_gpio_parse_bias(phandle_t node); 286 static int aw_gpio_parse_drive_strength(phandle_t node, uint32_t *drive); 287 288 static int aw_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value); 289 static int aw_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value); 290 static int aw_gpio_pin_get_locked(struct aw_gpio_softc *sc, uint32_t pin, unsigned int *value); 291 static int aw_gpio_pin_set_locked(struct aw_gpio_softc *sc, uint32_t pin, unsigned int value); 292 293 #define AW_GPIO_WRITE(_sc, _off, _val) \ 294 bus_space_write_4(_sc->sc_bst, _sc->sc_bsh, _off, _val) 295 #define AW_GPIO_READ(_sc, _off) \ 296 bus_space_read_4(_sc->sc_bst, _sc->sc_bsh, _off) 297 298 static uint32_t 299 aw_gpio_get_function(struct aw_gpio_softc *sc, uint32_t pin) 300 { 301 uint32_t bank, func, offset; 302 303 /* Must be called with lock held. */ 304 AW_GPIO_LOCK_ASSERT(sc); 305 306 if (pin > sc->conf->padconf->npins) 307 return (0); 308 bank = sc->conf->padconf->pins[pin].port; 309 pin = sc->conf->padconf->pins[pin].pin; 310 offset = ((pin & 0x07) << 2); 311 312 func = AW_GPIO_READ(sc, AW_GPIO_GP_CFG(bank, pin >> 3)); 313 314 return ((func >> offset) & 0x7); 315 } 316 317 static int 318 aw_gpio_set_function(struct aw_gpio_softc *sc, uint32_t pin, uint32_t f) 319 { 320 uint32_t bank, data, offset; 321 322 /* Check if the function exists in the padconf data */ 323 if (sc->conf->padconf->pins[pin].functions[f] == NULL) 324 return (EINVAL); 325 326 /* Must be called with lock held. */ 327 AW_GPIO_LOCK_ASSERT(sc); 328 329 bank = sc->conf->padconf->pins[pin].port; 330 pin = sc->conf->padconf->pins[pin].pin; 331 offset = ((pin & 0x07) << 2); 332 333 data = AW_GPIO_READ(sc, AW_GPIO_GP_CFG(bank, pin >> 3)); 334 data &= ~(7 << offset); 335 data |= (f << offset); 336 AW_GPIO_WRITE(sc, AW_GPIO_GP_CFG(bank, pin >> 3), data); 337 338 return (0); 339 } 340 341 static uint32_t 342 aw_gpio_get_pud(struct aw_gpio_softc *sc, uint32_t pin) 343 { 344 uint32_t bank, offset, val; 345 346 /* Must be called with lock held. */ 347 AW_GPIO_LOCK_ASSERT(sc); 348 349 bank = sc->conf->padconf->pins[pin].port; 350 pin = sc->conf->padconf->pins[pin].pin; 351 offset = ((pin & 0x0f) << 1); 352 353 val = AW_GPIO_READ(sc, AW_GPIO_GP_PUL(bank, pin >> 4)); 354 355 return ((val >> offset) & AW_GPIO_PUD_MASK); 356 } 357 358 static void 359 aw_gpio_set_pud(struct aw_gpio_softc *sc, uint32_t pin, uint32_t state) 360 { 361 uint32_t bank, offset, val; 362 363 if (aw_gpio_get_pud(sc, pin) == state) 364 return; 365 366 /* Must be called with lock held. */ 367 AW_GPIO_LOCK_ASSERT(sc); 368 369 bank = sc->conf->padconf->pins[pin].port; 370 pin = sc->conf->padconf->pins[pin].pin; 371 offset = ((pin & 0x0f) << 1); 372 373 val = AW_GPIO_READ(sc, AW_GPIO_GP_PUL(bank, pin >> 4)); 374 val &= ~(AW_GPIO_PUD_MASK << offset); 375 val |= (state << offset); 376 AW_GPIO_WRITE(sc, AW_GPIO_GP_PUL(bank, pin >> 4), val); 377 } 378 379 static uint32_t 380 aw_gpio_get_drv(struct aw_gpio_softc *sc, uint32_t pin) 381 { 382 uint32_t bank, offset, val; 383 384 /* Must be called with lock held. */ 385 AW_GPIO_LOCK_ASSERT(sc); 386 387 bank = sc->conf->padconf->pins[pin].port; 388 pin = sc->conf->padconf->pins[pin].pin; 389 offset = ((pin & 0x0f) << 1); 390 391 val = AW_GPIO_READ(sc, AW_GPIO_GP_DRV(bank, pin >> 4)); 392 393 return ((val >> offset) & AW_GPIO_DRV_MASK); 394 } 395 396 static void 397 aw_gpio_set_drv(struct aw_gpio_softc *sc, uint32_t pin, uint32_t drive) 398 { 399 uint32_t bank, offset, val; 400 401 if (aw_gpio_get_drv(sc, pin) == drive) 402 return; 403 404 /* Must be called with lock held. */ 405 AW_GPIO_LOCK_ASSERT(sc); 406 407 bank = sc->conf->padconf->pins[pin].port; 408 pin = sc->conf->padconf->pins[pin].pin; 409 offset = ((pin & 0x0f) << 1); 410 411 val = AW_GPIO_READ(sc, AW_GPIO_GP_DRV(bank, pin >> 4)); 412 val &= ~(AW_GPIO_DRV_MASK << offset); 413 val |= (drive << offset); 414 AW_GPIO_WRITE(sc, AW_GPIO_GP_DRV(bank, pin >> 4), val); 415 } 416 417 static int 418 aw_gpio_pin_configure(struct aw_gpio_softc *sc, uint32_t pin, uint32_t flags) 419 { 420 u_int val; 421 int err = 0; 422 423 /* Must be called with lock held. */ 424 AW_GPIO_LOCK_ASSERT(sc); 425 426 if (pin > sc->conf->padconf->npins) 427 return (EINVAL); 428 429 /* Manage input/output. */ 430 if (flags & GPIO_PIN_INPUT) { 431 err = aw_gpio_set_function(sc, pin, AW_GPIO_INPUT); 432 } else if ((flags & GPIO_PIN_OUTPUT) && 433 aw_gpio_get_function(sc, pin) != AW_GPIO_OUTPUT) { 434 if (flags & GPIO_PIN_PRESET_LOW) { 435 aw_gpio_pin_set_locked(sc, pin, 0); 436 } else if (flags & GPIO_PIN_PRESET_HIGH) { 437 aw_gpio_pin_set_locked(sc, pin, 1); 438 } else { 439 /* Read the pin and preset output to current state. */ 440 err = aw_gpio_set_function(sc, pin, AW_GPIO_INPUT); 441 if (err == 0) { 442 aw_gpio_pin_get_locked(sc, pin, &val); 443 aw_gpio_pin_set_locked(sc, pin, val); 444 } 445 } 446 if (err == 0) 447 err = aw_gpio_set_function(sc, pin, AW_GPIO_OUTPUT); 448 } 449 450 if (err) 451 return (err); 452 453 /* Manage Pull-up/pull-down. */ 454 if (flags & GPIO_PIN_PULLUP) 455 aw_gpio_set_pud(sc, pin, AW_GPIO_PULLUP); 456 else if (flags & GPIO_PIN_PULLDOWN) 457 aw_gpio_set_pud(sc, pin, AW_GPIO_PULLDOWN); 458 else 459 aw_gpio_set_pud(sc, pin, AW_GPIO_NONE); 460 461 return (0); 462 } 463 464 static device_t 465 aw_gpio_get_bus(device_t dev) 466 { 467 struct aw_gpio_softc *sc; 468 469 sc = device_get_softc(dev); 470 471 return (sc->sc_busdev); 472 } 473 474 static int 475 aw_gpio_pin_max(device_t dev, int *maxpin) 476 { 477 struct aw_gpio_softc *sc; 478 479 sc = device_get_softc(dev); 480 481 *maxpin = sc->conf->padconf->npins - 1; 482 return (0); 483 } 484 485 static int 486 aw_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 487 { 488 struct aw_gpio_softc *sc; 489 490 sc = device_get_softc(dev); 491 if (pin >= sc->conf->padconf->npins) 492 return (EINVAL); 493 494 *caps = AW_GPIO_DEFAULT_CAPS; 495 496 return (0); 497 } 498 499 static int 500 aw_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 501 { 502 struct aw_gpio_softc *sc; 503 uint32_t func; 504 uint32_t pud; 505 506 sc = device_get_softc(dev); 507 if (pin >= sc->conf->padconf->npins) 508 return (EINVAL); 509 510 AW_GPIO_LOCK(sc); 511 func = aw_gpio_get_function(sc, pin); 512 switch (func) { 513 case AW_GPIO_INPUT: 514 *flags = GPIO_PIN_INPUT; 515 break; 516 case AW_GPIO_OUTPUT: 517 *flags = GPIO_PIN_OUTPUT; 518 break; 519 default: 520 *flags = 0; 521 break; 522 } 523 524 pud = aw_gpio_get_pud(sc, pin); 525 switch (pud) { 526 case AW_GPIO_PULLDOWN: 527 *flags |= GPIO_PIN_PULLDOWN; 528 break; 529 case AW_GPIO_PULLUP: 530 *flags |= GPIO_PIN_PULLUP; 531 break; 532 default: 533 break; 534 } 535 536 AW_GPIO_UNLOCK(sc); 537 538 return (0); 539 } 540 541 static int 542 aw_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 543 { 544 struct aw_gpio_softc *sc; 545 546 sc = device_get_softc(dev); 547 if (pin >= sc->conf->padconf->npins) 548 return (EINVAL); 549 550 snprintf(name, GPIOMAXNAME - 1, "%s", 551 sc->conf->padconf->pins[pin].name); 552 name[GPIOMAXNAME - 1] = '\0'; 553 554 return (0); 555 } 556 557 static int 558 aw_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 559 { 560 struct aw_gpio_softc *sc; 561 int err; 562 563 sc = device_get_softc(dev); 564 if (pin > sc->conf->padconf->npins) 565 return (EINVAL); 566 567 AW_GPIO_LOCK(sc); 568 err = aw_gpio_pin_configure(sc, pin, flags); 569 AW_GPIO_UNLOCK(sc); 570 571 return (err); 572 } 573 574 static int 575 aw_gpio_pin_set_locked(struct aw_gpio_softc *sc, uint32_t pin, 576 unsigned int value) 577 { 578 uint32_t bank, data; 579 580 AW_GPIO_LOCK_ASSERT(sc); 581 582 if (pin > sc->conf->padconf->npins) 583 return (EINVAL); 584 585 bank = sc->conf->padconf->pins[pin].port; 586 pin = sc->conf->padconf->pins[pin].pin; 587 588 data = AW_GPIO_READ(sc, AW_GPIO_GP_DAT(bank)); 589 if (value) 590 data |= (1 << pin); 591 else 592 data &= ~(1 << pin); 593 AW_GPIO_WRITE(sc, AW_GPIO_GP_DAT(bank), data); 594 595 return (0); 596 } 597 598 static int 599 aw_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 600 { 601 struct aw_gpio_softc *sc; 602 int ret; 603 604 sc = device_get_softc(dev); 605 606 AW_GPIO_LOCK(sc); 607 ret = aw_gpio_pin_set_locked(sc, pin, value); 608 AW_GPIO_UNLOCK(sc); 609 610 return (ret); 611 } 612 613 static int 614 aw_gpio_pin_get_locked(struct aw_gpio_softc *sc,uint32_t pin, 615 unsigned int *val) 616 { 617 uint32_t bank, reg_data; 618 619 AW_GPIO_LOCK_ASSERT(sc); 620 621 if (pin > sc->conf->padconf->npins) 622 return (EINVAL); 623 624 bank = sc->conf->padconf->pins[pin].port; 625 pin = sc->conf->padconf->pins[pin].pin; 626 627 reg_data = AW_GPIO_READ(sc, AW_GPIO_GP_DAT(bank)); 628 *val = (reg_data & (1 << pin)) ? 1 : 0; 629 630 return (0); 631 } 632 633 static char * 634 aw_gpio_parse_function(phandle_t node) 635 { 636 char *function; 637 638 if (OF_getprop_alloc(node, "function", 639 (void **)&function) != -1) 640 return (function); 641 if (OF_getprop_alloc(node, "allwinner,function", 642 (void **)&function) != -1) 643 return (function); 644 645 return (NULL); 646 } 647 648 static const char ** 649 aw_gpio_parse_pins(phandle_t node, int *pins_nb) 650 { 651 const char **pinlist; 652 653 *pins_nb = ofw_bus_string_list_to_array(node, "pins", &pinlist); 654 if (*pins_nb > 0) 655 return (pinlist); 656 657 *pins_nb = ofw_bus_string_list_to_array(node, "allwinner,pins", 658 &pinlist); 659 if (*pins_nb > 0) 660 return (pinlist); 661 662 return (NULL); 663 } 664 665 static uint32_t 666 aw_gpio_parse_bias(phandle_t node) 667 { 668 uint32_t bias; 669 670 if (OF_getencprop(node, "pull", &bias, sizeof(bias)) != -1) 671 return (bias); 672 if (OF_getencprop(node, "allwinner,pull", &bias, sizeof(bias)) != -1) 673 return (bias); 674 if (OF_hasprop(node, "bias-disable")) 675 return (AW_GPIO_NONE); 676 if (OF_hasprop(node, "bias-pull-up")) 677 return (AW_GPIO_PULLUP); 678 if (OF_hasprop(node, "bias-pull-down")) 679 return (AW_GPIO_PULLDOWN); 680 681 return (AW_GPIO_NONE); 682 } 683 684 static int 685 aw_gpio_parse_drive_strength(phandle_t node, uint32_t *drive) 686 { 687 uint32_t drive_str; 688 689 if (OF_getencprop(node, "drive", drive, sizeof(*drive)) != -1) 690 return (0); 691 if (OF_getencprop(node, "allwinner,drive", drive, sizeof(*drive)) != -1) 692 return (0); 693 if (OF_getencprop(node, "drive-strength", &drive_str, 694 sizeof(drive_str)) != -1) { 695 *drive = (drive_str / 10) - 1; 696 return (0); 697 } 698 699 return (1); 700 } 701 702 static int 703 aw_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) 704 { 705 struct aw_gpio_softc *sc; 706 int ret; 707 708 sc = device_get_softc(dev); 709 710 AW_GPIO_LOCK(sc); 711 ret = aw_gpio_pin_get_locked(sc, pin, val); 712 AW_GPIO_UNLOCK(sc); 713 714 return (ret); 715 } 716 717 static int 718 aw_gpio_pin_toggle(device_t dev, uint32_t pin) 719 { 720 struct aw_gpio_softc *sc; 721 uint32_t bank, data; 722 723 sc = device_get_softc(dev); 724 if (pin > sc->conf->padconf->npins) 725 return (EINVAL); 726 727 bank = sc->conf->padconf->pins[pin].port; 728 pin = sc->conf->padconf->pins[pin].pin; 729 730 AW_GPIO_LOCK(sc); 731 data = AW_GPIO_READ(sc, AW_GPIO_GP_DAT(bank)); 732 if (data & (1 << pin)) 733 data &= ~(1 << pin); 734 else 735 data |= (1 << pin); 736 AW_GPIO_WRITE(sc, AW_GPIO_GP_DAT(bank), data); 737 AW_GPIO_UNLOCK(sc); 738 739 return (0); 740 } 741 742 static int 743 aw_gpio_pin_access_32(device_t dev, uint32_t first_pin, uint32_t clear_pins, 744 uint32_t change_pins, uint32_t *orig_pins) 745 { 746 struct aw_gpio_softc *sc; 747 uint32_t bank, data, pin; 748 749 sc = device_get_softc(dev); 750 if (first_pin > sc->conf->padconf->npins) 751 return (EINVAL); 752 753 /* 754 * We require that first_pin refers to the first pin in a bank, because 755 * this API is not about convenience, it's for making a set of pins 756 * change simultaneously (required) with reasonably high performance 757 * (desired); we need to do a read-modify-write on a single register. 758 */ 759 bank = sc->conf->padconf->pins[first_pin].port; 760 pin = sc->conf->padconf->pins[first_pin].pin; 761 if (pin != 0) 762 return (EINVAL); 763 764 AW_GPIO_LOCK(sc); 765 data = AW_GPIO_READ(sc, AW_GPIO_GP_DAT(bank)); 766 if ((clear_pins | change_pins) != 0) 767 AW_GPIO_WRITE(sc, AW_GPIO_GP_DAT(bank), 768 (data & ~clear_pins) ^ change_pins); 769 AW_GPIO_UNLOCK(sc); 770 771 if (orig_pins != NULL) 772 *orig_pins = data; 773 774 return (0); 775 } 776 777 static int 778 aw_gpio_pin_config_32(device_t dev, uint32_t first_pin, uint32_t num_pins, 779 uint32_t *pin_flags) 780 { 781 struct aw_gpio_softc *sc; 782 uint32_t bank, pin; 783 int err; 784 785 sc = device_get_softc(dev); 786 if (first_pin > sc->conf->padconf->npins) 787 return (EINVAL); 788 789 bank = sc->conf->padconf->pins[first_pin].port; 790 if (sc->conf->padconf->pins[first_pin].pin != 0) 791 return (EINVAL); 792 793 /* 794 * The configuration for a bank of pins is scattered among several 795 * registers; we cannot g'tee to simultaneously change the state of all 796 * the pins in the flags array. So just loop through the array 797 * configuring each pin for now. If there was a strong need, it might 798 * be possible to support some limited simultaneous config, such as 799 * adjacent groups of 8 pins that line up the same as the config regs. 800 */ 801 for (err = 0, pin = first_pin; err == 0 && pin < num_pins; ++pin) { 802 if (pin_flags[pin] & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) 803 err = aw_gpio_pin_configure(sc, pin, pin_flags[pin]); 804 } 805 806 return (err); 807 } 808 809 static int 810 aw_find_pinnum_by_name(struct aw_gpio_softc *sc, const char *pinname) 811 { 812 int i; 813 814 for (i = 0; i < sc->conf->padconf->npins; i++) 815 if (!strcmp(pinname, sc->conf->padconf->pins[i].name)) 816 return i; 817 818 return (-1); 819 } 820 821 static int 822 aw_find_pin_func(struct aw_gpio_softc *sc, int pin, const char *func) 823 { 824 int i; 825 826 for (i = 0; i < AW_MAX_FUNC_BY_PIN; i++) 827 if (sc->conf->padconf->pins[pin].functions[i] && 828 !strcmp(func, sc->conf->padconf->pins[pin].functions[i])) 829 return (i); 830 831 return (-1); 832 } 833 834 static int 835 aw_fdt_configure_pins(device_t dev, phandle_t cfgxref) 836 { 837 struct aw_gpio_softc *sc; 838 phandle_t node; 839 const char **pinlist = NULL; 840 char *pin_function = NULL; 841 uint32_t pin_drive, pin_pull; 842 int pins_nb, pin_num, pin_func, i, ret; 843 bool set_drive; 844 845 sc = device_get_softc(dev); 846 node = OF_node_from_xref(cfgxref); 847 ret = 0; 848 set_drive = false; 849 850 /* Getting all prop for configuring pins */ 851 pinlist = aw_gpio_parse_pins(node, &pins_nb); 852 if (pinlist == NULL) 853 return (ENOENT); 854 855 pin_function = aw_gpio_parse_function(node); 856 if (pin_function == NULL) { 857 ret = ENOENT; 858 goto out; 859 } 860 861 if (aw_gpio_parse_drive_strength(node, &pin_drive) == 0) 862 set_drive = true; 863 864 pin_pull = aw_gpio_parse_bias(node); 865 866 /* Configure each pin to the correct function, drive and pull */ 867 for (i = 0; i < pins_nb; i++) { 868 pin_num = aw_find_pinnum_by_name(sc, pinlist[i]); 869 if (pin_num == -1) { 870 ret = ENOENT; 871 goto out; 872 } 873 pin_func = aw_find_pin_func(sc, pin_num, pin_function); 874 if (pin_func == -1) { 875 ret = ENOENT; 876 goto out; 877 } 878 879 AW_GPIO_LOCK(sc); 880 881 if (aw_gpio_get_function(sc, pin_num) != pin_func) 882 aw_gpio_set_function(sc, pin_num, pin_func); 883 if (set_drive) 884 aw_gpio_set_drv(sc, pin_num, pin_drive); 885 if (pin_pull != AW_GPIO_NONE) 886 aw_gpio_set_pud(sc, pin_num, pin_pull); 887 888 AW_GPIO_UNLOCK(sc); 889 } 890 891 out: 892 OF_prop_free(pinlist); 893 OF_prop_free(pin_function); 894 return (ret); 895 } 896 897 static void 898 aw_gpio_enable_bank_supply(void *arg) 899 { 900 struct aw_gpio_softc *sc = arg; 901 regulator_t vcc_supply; 902 char bank_reg_name[16]; 903 int i, nbanks; 904 905 nbanks = strlen(sc->conf->banks); 906 for (i = 0; i < nbanks; i++) { 907 snprintf(bank_reg_name, sizeof(bank_reg_name), "vcc-p%c-supply", 908 sc->conf->banks[i]); 909 910 if (regulator_get_by_ofw_property(sc->sc_dev, 0, bank_reg_name, &vcc_supply) == 0) { 911 if (bootverbose) 912 device_printf(sc->sc_dev, 913 "Enabling regulator for gpio bank %c\n", 914 sc->conf->banks[i]); 915 if (regulator_enable(vcc_supply) != 0) { 916 device_printf(sc->sc_dev, 917 "Cannot enable regulator for bank %c\n", 918 sc->conf->banks[i]); 919 } 920 } 921 } 922 } 923 924 static int 925 aw_gpio_probe(device_t dev) 926 { 927 928 if (!ofw_bus_status_okay(dev)) 929 return (ENXIO); 930 931 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 932 return (ENXIO); 933 934 device_set_desc(dev, "Allwinner GPIO/Pinmux controller"); 935 return (BUS_PROBE_DEFAULT); 936 } 937 938 static int 939 aw_gpio_attach(device_t dev) 940 { 941 int rid, error; 942 phandle_t gpio; 943 struct aw_gpio_softc *sc; 944 struct clk_list *clkp, *clkp_tmp; 945 clk_t clk; 946 hwreset_t rst = NULL; 947 int off, err, clkret; 948 949 sc = device_get_softc(dev); 950 sc->sc_dev = dev; 951 952 mtx_init(&sc->sc_mtx, "aw gpio", "gpio", MTX_SPIN); 953 954 rid = 0; 955 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 956 RF_ACTIVE); 957 if (!sc->sc_mem_res) { 958 device_printf(dev, "cannot allocate memory window\n"); 959 goto fail; 960 } 961 962 sc->sc_bst = rman_get_bustag(sc->sc_mem_res); 963 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); 964 965 rid = 0; 966 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 967 RF_ACTIVE); 968 if (!sc->sc_irq_res) { 969 device_printf(dev, "cannot allocate interrupt\n"); 970 goto fail; 971 } 972 973 /* Find our node. */ 974 gpio = ofw_bus_get_node(sc->sc_dev); 975 if (!OF_hasprop(gpio, "gpio-controller")) 976 /* Node is not a GPIO controller. */ 977 goto fail; 978 979 /* Use the right pin data for the current SoC */ 980 sc->conf = (struct aw_gpio_conf *)ofw_bus_search_compatible(dev, 981 compat_data)->ocd_data; 982 983 if (hwreset_get_by_ofw_idx(dev, 0, 0, &rst) == 0) { 984 error = hwreset_deassert(rst); 985 if (error != 0) { 986 device_printf(dev, "cannot de-assert reset\n"); 987 goto fail; 988 } 989 } 990 991 TAILQ_INIT(&sc->clk_list); 992 for (off = 0, clkret = 0; clkret == 0; off++) { 993 clkret = clk_get_by_ofw_index(dev, 0, off, &clk); 994 if (clkret != 0) 995 break; 996 err = clk_enable(clk); 997 if (err != 0) { 998 device_printf(dev, "Could not enable clock %s\n", 999 clk_get_name(clk)); 1000 goto fail; 1001 } 1002 clkp = malloc(sizeof(*clkp), M_DEVBUF, M_WAITOK | M_ZERO); 1003 clkp->clk = clk; 1004 TAILQ_INSERT_TAIL(&sc->clk_list, clkp, next); 1005 } 1006 if (clkret != 0 && clkret != ENOENT) { 1007 device_printf(dev, "Could not find clock at offset %d (%d)\n", 1008 off, clkret); 1009 goto fail; 1010 } 1011 1012 sc->sc_busdev = gpiobus_attach_bus(dev); 1013 if (sc->sc_busdev == NULL) 1014 goto fail; 1015 1016 /* 1017 * Register as a pinctrl device 1018 */ 1019 fdt_pinctrl_register(dev, "pins"); 1020 fdt_pinctrl_configure_tree(dev); 1021 fdt_pinctrl_register(dev, "allwinner,pins"); 1022 fdt_pinctrl_configure_tree(dev); 1023 1024 config_intrhook_oneshot(aw_gpio_enable_bank_supply, sc); 1025 1026 return (0); 1027 1028 fail: 1029 if (sc->sc_irq_res) 1030 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 1031 if (sc->sc_mem_res) 1032 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 1033 mtx_destroy(&sc->sc_mtx); 1034 1035 /* Disable clock */ 1036 TAILQ_FOREACH_SAFE(clkp, &sc->clk_list, next, clkp_tmp) { 1037 err = clk_disable(clkp->clk); 1038 if (err != 0) 1039 device_printf(dev, "Could not disable clock %s\n", 1040 clk_get_name(clkp->clk)); 1041 err = clk_release(clkp->clk); 1042 if (err != 0) 1043 device_printf(dev, "Could not release clock %s\n", 1044 clk_get_name(clkp->clk)); 1045 TAILQ_REMOVE(&sc->clk_list, clkp, next); 1046 free(clkp, M_DEVBUF); 1047 } 1048 1049 /* Assert resets */ 1050 if (rst) { 1051 hwreset_assert(rst); 1052 hwreset_release(rst); 1053 } 1054 1055 return (ENXIO); 1056 } 1057 1058 static int 1059 aw_gpio_detach(device_t dev) 1060 { 1061 1062 return (EBUSY); 1063 } 1064 1065 static phandle_t 1066 aw_gpio_get_node(device_t dev, device_t bus) 1067 { 1068 1069 /* We only have one child, the GPIO bus, which needs our own node. */ 1070 return (ofw_bus_get_node(dev)); 1071 } 1072 1073 static int 1074 aw_gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, int gcells, 1075 pcell_t *gpios, uint32_t *pin, uint32_t *flags) 1076 { 1077 struct aw_gpio_softc *sc; 1078 int i; 1079 1080 sc = device_get_softc(bus); 1081 1082 /* The GPIO pins are mapped as: <gpio-phandle bank pin flags>. */ 1083 for (i = 0; i < sc->conf->padconf->npins; i++) 1084 if (sc->conf->padconf->pins[i].port == gpios[0] && 1085 sc->conf->padconf->pins[i].pin == gpios[1]) { 1086 *pin = i; 1087 break; 1088 } 1089 *flags = gpios[gcells - 1]; 1090 1091 return (0); 1092 } 1093 1094 static device_method_t aw_gpio_methods[] = { 1095 /* Device interface */ 1096 DEVMETHOD(device_probe, aw_gpio_probe), 1097 DEVMETHOD(device_attach, aw_gpio_attach), 1098 DEVMETHOD(device_detach, aw_gpio_detach), 1099 1100 /* GPIO protocol */ 1101 DEVMETHOD(gpio_get_bus, aw_gpio_get_bus), 1102 DEVMETHOD(gpio_pin_max, aw_gpio_pin_max), 1103 DEVMETHOD(gpio_pin_getname, aw_gpio_pin_getname), 1104 DEVMETHOD(gpio_pin_getflags, aw_gpio_pin_getflags), 1105 DEVMETHOD(gpio_pin_getcaps, aw_gpio_pin_getcaps), 1106 DEVMETHOD(gpio_pin_setflags, aw_gpio_pin_setflags), 1107 DEVMETHOD(gpio_pin_get, aw_gpio_pin_get), 1108 DEVMETHOD(gpio_pin_set, aw_gpio_pin_set), 1109 DEVMETHOD(gpio_pin_toggle, aw_gpio_pin_toggle), 1110 DEVMETHOD(gpio_pin_access_32, aw_gpio_pin_access_32), 1111 DEVMETHOD(gpio_pin_config_32, aw_gpio_pin_config_32), 1112 DEVMETHOD(gpio_map_gpios, aw_gpio_map_gpios), 1113 1114 /* ofw_bus interface */ 1115 DEVMETHOD(ofw_bus_get_node, aw_gpio_get_node), 1116 1117 /* fdt_pinctrl interface */ 1118 DEVMETHOD(fdt_pinctrl_configure,aw_fdt_configure_pins), 1119 1120 DEVMETHOD_END 1121 }; 1122 1123 static devclass_t aw_gpio_devclass; 1124 1125 static driver_t aw_gpio_driver = { 1126 "gpio", 1127 aw_gpio_methods, 1128 sizeof(struct aw_gpio_softc), 1129 }; 1130 1131 EARLY_DRIVER_MODULE(aw_gpio, simplebus, aw_gpio_driver, aw_gpio_devclass, 0, 0, 1132 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE); 1133