1 /*- 2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca> 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 18 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 19 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 20 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 21 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 /* 27 * Allwinner GMAC clock 28 */ 29 30 #include <sys/cdefs.h> 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 #include <sys/rman.h> 35 #include <sys/kernel.h> 36 #include <sys/module.h> 37 #include <machine/bus.h> 38 39 #include <dev/ofw/ofw_bus.h> 40 #include <dev/ofw/ofw_bus_subr.h> 41 #include <dev/ofw/ofw_subr.h> 42 43 #include <dev/extres/clk/clk_mux.h> 44 #include <dev/extres/clk/clk_gate.h> 45 46 #include "clkdev_if.h" 47 48 #define GMAC_CLK_PIT (0x1 << 2) 49 #define GMAC_CLK_PIT_SHIFT 2 50 #define GMAC_CLK_PIT_MII 0 51 #define GMAC_CLK_PIT_RGMII 1 52 #define GMAC_CLK_SRC (0x3 << 0) 53 #define GMAC_CLK_SRC_SHIFT 0 54 #define GMAC_CLK_SRC_MII 0 55 #define GMAC_CLK_SRC_EXT_RGMII 1 56 #define GMAC_CLK_SRC_RGMII 2 57 58 #define EMAC_TXC_DIV_CFG (1 << 15) 59 #define EMAC_TXC_DIV_CFG_SHIFT 15 60 #define EMAC_TXC_DIV_CFG_125MHZ 0 61 #define EMAC_TXC_DIV_CFG_25MHZ 1 62 #define EMAC_PHY_SELECT (1 << 16) 63 #define EMAC_PHY_SELECT_SHIFT 16 64 #define EMAC_PHY_SELECT_INT 0 65 #define EMAC_PHY_SELECT_EXT 1 66 #define EMAC_ETXDC (0x7 << 10) 67 #define EMAC_ETXDC_SHIFT 10 68 #define EMAC_ERXDC (0x1f << 5) 69 #define EMAC_ERXDC_SHIFT 5 70 71 #define CLK_IDX_MII 0 72 #define CLK_IDX_RGMII 1 73 #define CLK_IDX_COUNT 2 74 75 static struct ofw_compat_data compat_data[] = { 76 { "allwinner,sun7i-a20-gmac-clk", 1 }, 77 { NULL, 0 } 78 }; 79 80 struct aw_gmacclk_sc { 81 device_t clkdev; 82 bus_addr_t reg; 83 84 int rx_delay; 85 int tx_delay; 86 }; 87 88 #define GMACCLK_READ(sc, val) CLKDEV_READ_4((sc)->clkdev, (sc)->reg, (val)) 89 #define GMACCLK_WRITE(sc, val) CLKDEV_WRITE_4((sc)->clkdev, (sc)->reg, (val)) 90 #define DEVICE_LOCK(sc) CLKDEV_DEVICE_LOCK((sc)->clkdev) 91 #define DEVICE_UNLOCK(sc) CLKDEV_DEVICE_UNLOCK((sc)->clkdev) 92 93 static int 94 aw_gmacclk_init(struct clknode *clk, device_t dev) 95 { 96 struct aw_gmacclk_sc *sc; 97 uint32_t val, index; 98 99 sc = clknode_get_softc(clk); 100 101 DEVICE_LOCK(sc); 102 GMACCLK_READ(sc, &val); 103 DEVICE_UNLOCK(sc); 104 105 switch ((val & GMAC_CLK_SRC) >> GMAC_CLK_SRC_SHIFT) { 106 case GMAC_CLK_SRC_MII: 107 index = CLK_IDX_MII; 108 break; 109 case GMAC_CLK_SRC_RGMII: 110 index = CLK_IDX_RGMII; 111 break; 112 default: 113 return (ENXIO); 114 } 115 116 clknode_init_parent_idx(clk, index); 117 return (0); 118 } 119 120 static int 121 aw_gmacclk_set_mux(struct clknode *clk, int index) 122 { 123 struct aw_gmacclk_sc *sc; 124 uint32_t val, clk_src, pit; 125 126 sc = clknode_get_softc(clk); 127 128 switch (index) { 129 case CLK_IDX_MII: 130 clk_src = GMAC_CLK_SRC_MII; 131 pit = GMAC_CLK_PIT_MII; 132 break; 133 case CLK_IDX_RGMII: 134 clk_src = GMAC_CLK_SRC_RGMII; 135 pit = GMAC_CLK_PIT_RGMII; 136 break; 137 default: 138 return (ENXIO); 139 } 140 141 DEVICE_LOCK(sc); 142 GMACCLK_READ(sc, &val); 143 val &= ~(GMAC_CLK_SRC | GMAC_CLK_PIT); 144 val |= (clk_src << GMAC_CLK_SRC_SHIFT); 145 val |= (pit << GMAC_CLK_PIT_SHIFT); 146 GMACCLK_WRITE(sc, val); 147 DEVICE_UNLOCK(sc); 148 149 return (0); 150 } 151 152 static clknode_method_t aw_gmacclk_clknode_methods[] = { 153 /* Device interface */ 154 CLKNODEMETHOD(clknode_init, aw_gmacclk_init), 155 CLKNODEMETHOD(clknode_set_mux, aw_gmacclk_set_mux), 156 CLKNODEMETHOD_END 157 }; 158 DEFINE_CLASS_1(aw_gmacclk_clknode, aw_gmacclk_clknode_class, 159 aw_gmacclk_clknode_methods, sizeof(struct aw_gmacclk_sc), clknode_class); 160 161 static int 162 aw_gmacclk_probe(device_t dev) 163 { 164 if (!ofw_bus_status_okay(dev)) 165 return (ENXIO); 166 167 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 168 return (ENXIO); 169 170 device_set_desc(dev, "Allwinner GMAC Clock"); 171 return (BUS_PROBE_DEFAULT); 172 } 173 174 static int 175 aw_gmacclk_attach(device_t dev) 176 { 177 struct clknode_init_def def; 178 struct aw_gmacclk_sc *sc; 179 struct clkdom *clkdom; 180 struct clknode *clk; 181 clk_t clk_parent; 182 bus_addr_t paddr; 183 bus_size_t psize; 184 phandle_t node; 185 int error, ncells, i; 186 187 node = ofw_bus_get_node(dev); 188 189 if (ofw_reg_to_paddr(node, 0, &paddr, &psize, NULL) != 0) { 190 device_printf(dev, "cannot parse 'reg' property\n"); 191 return (ENXIO); 192 } 193 194 error = ofw_bus_parse_xref_list_get_length(node, "clocks", 195 "#clock-cells", &ncells); 196 if (error != 0 || ncells != CLK_IDX_COUNT) { 197 device_printf(dev, "couldn't find parent clocks\n"); 198 return (ENXIO); 199 } 200 201 clkdom = clkdom_create(dev); 202 203 memset(&def, 0, sizeof(def)); 204 error = clk_parse_ofw_clk_name(dev, node, &def.name); 205 if (error != 0) { 206 device_printf(dev, "cannot parse clock name\n"); 207 error = ENXIO; 208 goto fail; 209 } 210 def.id = 1; 211 def.parent_names = malloc(sizeof(char *) * ncells, M_OFWPROP, M_WAITOK); 212 for (i = 0; i < ncells; i++) { 213 error = clk_get_by_ofw_index(dev, 0, i, &clk_parent); 214 if (error != 0) { 215 device_printf(dev, "cannot get clock %d\n", error); 216 goto fail; 217 } 218 def.parent_names[i] = clk_get_name(clk_parent); 219 clk_release(clk_parent); 220 } 221 def.parent_cnt = ncells; 222 223 clk = clknode_create(clkdom, &aw_gmacclk_clknode_class, &def); 224 if (clk == NULL) { 225 device_printf(dev, "cannot create clknode\n"); 226 error = ENXIO; 227 goto fail; 228 } 229 230 sc = clknode_get_softc(clk); 231 sc->reg = paddr; 232 sc->clkdev = device_get_parent(dev); 233 sc->tx_delay = sc->rx_delay = -1; 234 OF_getencprop(node, "tx-delay", &sc->tx_delay, sizeof(sc->tx_delay)); 235 OF_getencprop(node, "rx-delay", &sc->rx_delay, sizeof(sc->rx_delay)); 236 237 clknode_register(clkdom, clk); 238 239 if (clkdom_finit(clkdom) != 0) { 240 device_printf(dev, "cannot finalize clkdom initialization\n"); 241 error = ENXIO; 242 goto fail; 243 } 244 245 if (bootverbose) 246 clkdom_dump(clkdom); 247 248 return (0); 249 250 fail: 251 return (error); 252 } 253 254 static device_method_t aw_gmacclk_methods[] = { 255 /* Device interface */ 256 DEVMETHOD(device_probe, aw_gmacclk_probe), 257 DEVMETHOD(device_attach, aw_gmacclk_attach), 258 259 DEVMETHOD_END 260 }; 261 262 static driver_t aw_gmacclk_driver = { 263 "aw_gmacclk", 264 aw_gmacclk_methods, 265 0 266 }; 267 268 EARLY_DRIVER_MODULE(aw_gmacclk, simplebus, aw_gmacclk_driver, 0, 0, 269 BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE); 270