1 /*- 2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca> 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 18 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 19 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 20 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 21 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 /* 27 * Allwinner GMAC clock 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/rman.h> 37 #include <sys/kernel.h> 38 #include <sys/module.h> 39 #include <machine/bus.h> 40 41 #include <dev/ofw/ofw_bus.h> 42 #include <dev/ofw/ofw_bus_subr.h> 43 #include <dev/ofw/ofw_subr.h> 44 45 #include <dev/extres/clk/clk_mux.h> 46 #include <dev/extres/clk/clk_gate.h> 47 48 #include "clkdev_if.h" 49 50 #define GMAC_CLK_PIT (0x1 << 2) 51 #define GMAC_CLK_PIT_SHIFT 2 52 #define GMAC_CLK_PIT_MII 0 53 #define GMAC_CLK_PIT_RGMII 1 54 #define GMAC_CLK_SRC (0x3 << 0) 55 #define GMAC_CLK_SRC_SHIFT 0 56 #define GMAC_CLK_SRC_MII 0 57 #define GMAC_CLK_SRC_EXT_RGMII 1 58 #define GMAC_CLK_SRC_RGMII 2 59 60 #define EMAC_TXC_DIV_CFG (1 << 15) 61 #define EMAC_TXC_DIV_CFG_SHIFT 15 62 #define EMAC_TXC_DIV_CFG_125MHZ 0 63 #define EMAC_TXC_DIV_CFG_25MHZ 1 64 #define EMAC_PHY_SELECT (1 << 16) 65 #define EMAC_PHY_SELECT_SHIFT 16 66 #define EMAC_PHY_SELECT_INT 0 67 #define EMAC_PHY_SELECT_EXT 1 68 #define EMAC_ETXDC (0x7 << 10) 69 #define EMAC_ETXDC_SHIFT 10 70 #define EMAC_ERXDC (0x1f << 5) 71 #define EMAC_ERXDC_SHIFT 5 72 73 #define CLK_IDX_MII 0 74 #define CLK_IDX_RGMII 1 75 #define CLK_IDX_COUNT 2 76 77 static struct ofw_compat_data compat_data[] = { 78 { "allwinner,sun7i-a20-gmac-clk", 1 }, 79 { NULL, 0 } 80 }; 81 82 struct aw_gmacclk_sc { 83 device_t clkdev; 84 bus_addr_t reg; 85 86 int rx_delay; 87 int tx_delay; 88 }; 89 90 #define GMACCLK_READ(sc, val) CLKDEV_READ_4((sc)->clkdev, (sc)->reg, (val)) 91 #define GMACCLK_WRITE(sc, val) CLKDEV_WRITE_4((sc)->clkdev, (sc)->reg, (val)) 92 #define DEVICE_LOCK(sc) CLKDEV_DEVICE_LOCK((sc)->clkdev) 93 #define DEVICE_UNLOCK(sc) CLKDEV_DEVICE_UNLOCK((sc)->clkdev) 94 95 static int 96 aw_gmacclk_init(struct clknode *clk, device_t dev) 97 { 98 struct aw_gmacclk_sc *sc; 99 uint32_t val, index; 100 101 sc = clknode_get_softc(clk); 102 103 DEVICE_LOCK(sc); 104 GMACCLK_READ(sc, &val); 105 DEVICE_UNLOCK(sc); 106 107 switch ((val & GMAC_CLK_SRC) >> GMAC_CLK_SRC_SHIFT) { 108 case GMAC_CLK_SRC_MII: 109 index = CLK_IDX_MII; 110 break; 111 case GMAC_CLK_SRC_RGMII: 112 index = CLK_IDX_RGMII; 113 break; 114 default: 115 return (ENXIO); 116 } 117 118 clknode_init_parent_idx(clk, index); 119 return (0); 120 } 121 122 static int 123 aw_gmacclk_set_mux(struct clknode *clk, int index) 124 { 125 struct aw_gmacclk_sc *sc; 126 uint32_t val, clk_src, pit; 127 128 sc = clknode_get_softc(clk); 129 130 switch (index) { 131 case CLK_IDX_MII: 132 clk_src = GMAC_CLK_SRC_MII; 133 pit = GMAC_CLK_PIT_MII; 134 break; 135 case CLK_IDX_RGMII: 136 clk_src = GMAC_CLK_SRC_RGMII; 137 pit = GMAC_CLK_PIT_RGMII; 138 break; 139 default: 140 return (ENXIO); 141 } 142 143 DEVICE_LOCK(sc); 144 GMACCLK_READ(sc, &val); 145 val &= ~(GMAC_CLK_SRC | GMAC_CLK_PIT); 146 val |= (clk_src << GMAC_CLK_SRC_SHIFT); 147 val |= (pit << GMAC_CLK_PIT_SHIFT); 148 GMACCLK_WRITE(sc, val); 149 DEVICE_UNLOCK(sc); 150 151 return (0); 152 } 153 154 static clknode_method_t aw_gmacclk_clknode_methods[] = { 155 /* Device interface */ 156 CLKNODEMETHOD(clknode_init, aw_gmacclk_init), 157 CLKNODEMETHOD(clknode_set_mux, aw_gmacclk_set_mux), 158 CLKNODEMETHOD_END 159 }; 160 DEFINE_CLASS_1(aw_gmacclk_clknode, aw_gmacclk_clknode_class, 161 aw_gmacclk_clknode_methods, sizeof(struct aw_gmacclk_sc), clknode_class); 162 163 static int 164 aw_gmacclk_probe(device_t dev) 165 { 166 if (!ofw_bus_status_okay(dev)) 167 return (ENXIO); 168 169 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 170 return (ENXIO); 171 172 device_set_desc(dev, "Allwinner GMAC Clock"); 173 return (BUS_PROBE_DEFAULT); 174 } 175 176 static int 177 aw_gmacclk_attach(device_t dev) 178 { 179 struct clknode_init_def def; 180 struct aw_gmacclk_sc *sc; 181 struct clkdom *clkdom; 182 struct clknode *clk; 183 clk_t clk_parent; 184 bus_addr_t paddr; 185 bus_size_t psize; 186 phandle_t node; 187 int error, ncells, i; 188 189 node = ofw_bus_get_node(dev); 190 191 if (ofw_reg_to_paddr(node, 0, &paddr, &psize, NULL) != 0) { 192 device_printf(dev, "cannot parse 'reg' property\n"); 193 return (ENXIO); 194 } 195 196 error = ofw_bus_parse_xref_list_get_length(node, "clocks", 197 "#clock-cells", &ncells); 198 if (error != 0 || ncells != CLK_IDX_COUNT) { 199 device_printf(dev, "couldn't find parent clocks\n"); 200 return (ENXIO); 201 } 202 203 clkdom = clkdom_create(dev); 204 205 memset(&def, 0, sizeof(def)); 206 error = clk_parse_ofw_clk_name(dev, node, &def.name); 207 if (error != 0) { 208 device_printf(dev, "cannot parse clock name\n"); 209 error = ENXIO; 210 goto fail; 211 } 212 def.id = 1; 213 def.parent_names = malloc(sizeof(char *) * ncells, M_OFWPROP, M_WAITOK); 214 for (i = 0; i < ncells; i++) { 215 error = clk_get_by_ofw_index(dev, 0, i, &clk_parent); 216 if (error != 0) { 217 device_printf(dev, "cannot get clock %d\n", error); 218 goto fail; 219 } 220 def.parent_names[i] = clk_get_name(clk_parent); 221 clk_release(clk_parent); 222 } 223 def.parent_cnt = ncells; 224 225 clk = clknode_create(clkdom, &aw_gmacclk_clknode_class, &def); 226 if (clk == NULL) { 227 device_printf(dev, "cannot create clknode\n"); 228 error = ENXIO; 229 goto fail; 230 } 231 232 sc = clknode_get_softc(clk); 233 sc->reg = paddr; 234 sc->clkdev = device_get_parent(dev); 235 sc->tx_delay = sc->rx_delay = -1; 236 OF_getencprop(node, "tx-delay", &sc->tx_delay, sizeof(sc->tx_delay)); 237 OF_getencprop(node, "rx-delay", &sc->rx_delay, sizeof(sc->rx_delay)); 238 239 clknode_register(clkdom, clk); 240 241 if (clkdom_finit(clkdom) != 0) { 242 device_printf(dev, "cannot finalize clkdom initialization\n"); 243 error = ENXIO; 244 goto fail; 245 } 246 247 if (bootverbose) 248 clkdom_dump(clkdom); 249 250 return (0); 251 252 fail: 253 return (error); 254 } 255 256 static device_method_t aw_gmacclk_methods[] = { 257 /* Device interface */ 258 DEVMETHOD(device_probe, aw_gmacclk_probe), 259 DEVMETHOD(device_attach, aw_gmacclk_attach), 260 261 DEVMETHOD_END 262 }; 263 264 static driver_t aw_gmacclk_driver = { 265 "aw_gmacclk", 266 aw_gmacclk_methods, 267 0 268 }; 269 270 EARLY_DRIVER_MODULE(aw_gmacclk, simplebus, aw_gmacclk_driver, 0, 0, 271 BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE); 272