1 /*- 2 * Copyright (c) 2016 Ganbold Tsagaankhuu <ganbold@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * Allwinner Consumer IR controller 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/kernel.h> 38 #include <sys/module.h> 39 #include <sys/rman.h> 40 #include <sys/sysctl.h> 41 #include <machine/bus.h> 42 43 #include <dev/fdt/fdt_common.h> 44 #include <dev/ofw/openfirm.h> 45 #include <dev/ofw/ofw_bus.h> 46 #include <dev/ofw/ofw_bus_subr.h> 47 #include <dev/extres/clk/clk.h> 48 #include <dev/extres/hwreset/hwreset.h> 49 50 #include <dev/evdev/input.h> 51 #include <dev/evdev/evdev.h> 52 53 #define READ(_sc, _r) bus_read_4((_sc)->res[0], (_r)) 54 #define WRITE(_sc, _r, _v) bus_write_4((_sc)->res[0], (_r), (_v)) 55 56 /* IR Control */ 57 #define AW_IR_CTL 0x00 58 /* Global Enable */ 59 #define AW_IR_CTL_GEN (1 << 0) 60 /* RX enable */ 61 #define AW_IR_CTL_RXEN (1 << 1) 62 /* CIR mode enable */ 63 #define AW_IR_CTL_MD (1 << 4) | (1 << 5) 64 65 /* RX Config Reg */ 66 #define AW_IR_RXCTL 0x10 67 /* Pulse Polarity Invert flag */ 68 #define AW_IR_RXCTL_RPPI (1 << 2) 69 70 /* RX Data */ 71 #define AW_IR_RXFIFO 0x20 72 73 /* RX Interrupt Control */ 74 #define AW_IR_RXINT 0x2C 75 /* RX FIFO Overflow */ 76 #define AW_IR_RXINT_ROI_EN (1 << 0) 77 /* RX Packet End */ 78 #define AW_IR_RXINT_RPEI_EN (1 << 1) 79 /* RX FIFO Data Available */ 80 #define AW_IR_RXINT_RAI_EN (1 << 4) 81 /* RX FIFO available byte level */ 82 #define AW_IR_RXINT_RAL(val) ((val) << 8) 83 84 /* RX Interrupt Status Reg */ 85 #define AW_IR_RXSTA 0x30 86 /* RX FIFO Get Available Counter */ 87 #define AW_IR_RXSTA_COUNTER(val) (((val) >> 8) & (sc->fifo_size * 2 - 1)) 88 /* Clear all interrupt status */ 89 #define AW_IR_RXSTA_CLEARALL 0xff 90 91 /* IR Sample Configure Reg */ 92 #define AW_IR_CIR 0x34 93 /* Filter Threshold = 8 * 21.3 = ~128us < 200us */ 94 #define AW_IR_RXFILT_VAL (((8) & 0x3f) << 2) 95 /* Idle Threshold = (2 + 1) * 128 * 42.7 = ~16.4ms > 9ms */ 96 #define AW_IR_RXIDLE_VAL (((2) & 0xff) << 8) 97 98 /* Bit 15 - value (pulse/space) */ 99 #define VAL_MASK 0x80 100 /* Bits 0:14 - sample duration */ 101 #define PERIOD_MASK 0x7f 102 103 /* Clock rate for IR0 or IR1 clock in CIR mode */ 104 #define AW_IR_BASE_CLK 3000000 105 /* Frequency sample 3MHz/64 = 46875Hz (21.3us) */ 106 #define AW_IR_SAMPLE_64 (0 << 0) 107 /* Frequency sample 3MHz/128 = 23437.5Hz (42.7us) */ 108 #define AW_IR_SAMPLE_128 (1 << 0) 109 110 #define AW_IR_ERROR_CODE 0xffffffff 111 #define AW_IR_REPEAT_CODE 0x0 112 113 /* 80 * 42.7 = ~3.4ms, Lead1(4.5ms) > AW_IR_L1_MIN */ 114 #define AW_IR_L1_MIN 80 115 /* 40 * 42.7 = ~1.7ms, Lead0(4.5ms) Lead0R(2.25ms) > AW_IR_L0_MIN */ 116 #define AW_IR_L0_MIN 40 117 /* 26 * 42.7 = ~1109us ~= 561 * 2, Pulse < AW_IR_PMAX */ 118 #define AW_IR_PMAX 26 119 /* 26 * 42.7 = ~1109us ~= 561 * 2, D1 > AW_IR_DMID, D0 <= AW_IR_DMID */ 120 #define AW_IR_DMID 26 121 /* 53 * 42.7 = ~2263us ~= 561 * 4, D < AW_IR_DMAX */ 122 #define AW_IR_DMAX 53 123 124 /* Active Thresholds */ 125 #define AW_IR_ACTIVE_T ((0 & 0xff) << 16) 126 #define AW_IR_ACTIVE_T_C ((1 & 0xff) << 23) 127 128 /* Code masks */ 129 #define CODE_MASK 0x00ff00ff 130 #define INV_CODE_MASK 0xff00ff00 131 #define VALID_CODE_MASK 0x00ff0000 132 133 #define A10_IR 1 134 #define A13_IR 2 135 136 #define AW_IR_RAW_BUF_SIZE 128 137 138 struct aw_ir_softc { 139 device_t dev; 140 struct resource *res[2]; 141 void * intrhand; 142 int fifo_size; 143 int dcnt; /* Packet Count */ 144 unsigned char buf[AW_IR_RAW_BUF_SIZE]; 145 struct evdev_dev *sc_evdev; 146 }; 147 148 static struct resource_spec aw_ir_spec[] = { 149 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 150 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 151 { -1, 0 } 152 }; 153 154 static struct ofw_compat_data compat_data[] = { 155 { "allwinner,sun4i-a10-ir", A10_IR }, 156 { "allwinner,sun5i-a13-ir", A13_IR }, 157 { NULL, 0 } 158 }; 159 160 static void 161 aw_ir_buf_reset(struct aw_ir_softc *sc) 162 { 163 164 sc->dcnt = 0; 165 } 166 167 static void 168 aw_ir_buf_write(struct aw_ir_softc *sc, unsigned char data) 169 { 170 171 if (sc->dcnt < AW_IR_RAW_BUF_SIZE) 172 sc->buf[sc->dcnt++] = data; 173 else 174 if (bootverbose) 175 device_printf(sc->dev, "IR RX Buffer Full!\n"); 176 } 177 178 static int 179 aw_ir_buf_full(struct aw_ir_softc *sc) 180 { 181 182 return (sc->dcnt >= AW_IR_RAW_BUF_SIZE); 183 } 184 185 static unsigned char 186 aw_ir_read_data(struct aw_ir_softc *sc) 187 { 188 189 return (unsigned char)(READ(sc, AW_IR_RXFIFO) & 0xff); 190 } 191 192 static unsigned long 193 aw_ir_decode_packets(struct aw_ir_softc *sc) 194 { 195 unsigned long len, code; 196 unsigned char val, last; 197 unsigned int active_delay; 198 int i, bitcount; 199 200 if (bootverbose) 201 device_printf(sc->dev, "sc->dcnt = %d\n", sc->dcnt); 202 203 /* Find Lead 1 (bit separator) */ 204 active_delay = (AW_IR_ACTIVE_T + 1) * (AW_IR_ACTIVE_T_C ? 128 : 1); 205 len = 0; 206 len += (active_delay >> 1); 207 if (bootverbose) 208 device_printf(sc->dev, "Initial len: %ld\n", len); 209 for (i = 0; i < sc->dcnt; i++) { 210 val = sc->buf[i]; 211 if (val & VAL_MASK) 212 len += val & PERIOD_MASK; 213 else { 214 if (len > AW_IR_L1_MIN) 215 break; 216 len = 0; 217 } 218 } 219 if (bootverbose) 220 device_printf(sc->dev, "len = %ld\n", len); 221 if ((val & VAL_MASK) || (len <= AW_IR_L1_MIN)) { 222 if (bootverbose) 223 device_printf(sc->dev, "Bit separator error\n"); 224 goto error_code; 225 } 226 227 /* Find Lead 0 (bit length) */ 228 len = 0; 229 for (; i < sc->dcnt; i++) { 230 val = sc->buf[i]; 231 if (val & VAL_MASK) { 232 if(len > AW_IR_L0_MIN) 233 break; 234 len = 0; 235 } else 236 len += val & PERIOD_MASK; 237 } 238 if ((!(val & VAL_MASK)) || (len <= AW_IR_L0_MIN)) { 239 if (bootverbose) 240 device_printf(sc->dev, "Bit length error\n"); 241 goto error_code; 242 } 243 244 /* Start decoding */ 245 code = 0; 246 bitcount = 0; 247 last = 1; 248 len = 0; 249 for (; i < sc->dcnt; i++) { 250 val = sc->buf[i]; 251 if (last) { 252 if (val & VAL_MASK) 253 len += val & PERIOD_MASK; 254 else { 255 if (len > AW_IR_PMAX) { 256 if (bootverbose) 257 device_printf(sc->dev, 258 "Pulse error\n"); 259 goto error_code; 260 } 261 last = 0; 262 len = val & PERIOD_MASK; 263 } 264 } else { 265 if (val & VAL_MASK) { 266 if (len > AW_IR_DMAX) { 267 if (bootverbose) 268 device_printf(sc->dev, 269 "Distant error\n"); 270 goto error_code; 271 } else { 272 if (len > AW_IR_DMID) { 273 /* Decode */ 274 code |= 1 << bitcount; 275 } 276 bitcount++; 277 if (bitcount == 32) 278 break; /* Finish decoding */ 279 } 280 last = 1; 281 len = val & PERIOD_MASK; 282 } else 283 len += val & PERIOD_MASK; 284 } 285 } 286 return (code); 287 288 error_code: 289 290 return (AW_IR_ERROR_CODE); 291 } 292 293 static int 294 aw_ir_validate_code(unsigned long code) 295 { 296 unsigned long v1, v2; 297 298 /* Don't check address */ 299 v1 = code & CODE_MASK; 300 v2 = (code & INV_CODE_MASK) >> 8; 301 302 if (((v1 ^ v2) & VALID_CODE_MASK) == VALID_CODE_MASK) 303 return (0); /* valid */ 304 else 305 return (1); /* invalid */ 306 } 307 308 static void 309 aw_ir_intr(void *arg) 310 { 311 struct aw_ir_softc *sc; 312 uint32_t val; 313 int i, dcnt; 314 unsigned long ir_code; 315 int stat; 316 317 sc = (struct aw_ir_softc *)arg; 318 319 /* Read RX interrupt status */ 320 val = READ(sc, AW_IR_RXSTA); 321 322 /* Clean all pending interrupt statuses */ 323 WRITE(sc, AW_IR_RXSTA, val | AW_IR_RXSTA_CLEARALL); 324 325 /* When Rx FIFO Data available or Packet end */ 326 if (val & (AW_IR_RXINT_RAI_EN | AW_IR_RXINT_RPEI_EN)) { 327 /* Get available message count in RX FIFO */ 328 dcnt = AW_IR_RXSTA_COUNTER(val); 329 /* Read FIFO */ 330 for (i = 0; i < dcnt; i++) { 331 if (aw_ir_buf_full(sc)) { 332 if (bootverbose) 333 device_printf(sc->dev, 334 "raw buffer full\n"); 335 break; 336 } else 337 aw_ir_buf_write(sc, aw_ir_read_data(sc)); 338 } 339 } 340 341 if (val & AW_IR_RXINT_RPEI_EN) { 342 /* RX Packet end */ 343 if (bootverbose) 344 device_printf(sc->dev, "RX Packet end\n"); 345 ir_code = aw_ir_decode_packets(sc); 346 stat = aw_ir_validate_code(ir_code); 347 if (stat == 0) { 348 evdev_push_event(sc->sc_evdev, 349 EV_MSC, MSC_SCAN, ir_code); 350 evdev_sync(sc->sc_evdev); 351 } 352 if (bootverbose) { 353 device_printf(sc->dev, "Final IR code: %lx\n", 354 ir_code); 355 device_printf(sc->dev, "IR code status: %d\n", 356 stat); 357 } 358 sc->dcnt = 0; 359 } 360 if (val & AW_IR_RXINT_ROI_EN) { 361 /* RX FIFO overflow */ 362 if (bootverbose) 363 device_printf(sc->dev, "RX FIFO overflow\n"); 364 /* Flush raw buffer */ 365 aw_ir_buf_reset(sc); 366 } 367 } 368 369 static int 370 aw_ir_probe(device_t dev) 371 { 372 373 if (!ofw_bus_status_okay(dev)) 374 return (ENXIO); 375 376 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 377 return (ENXIO); 378 379 device_set_desc(dev, "Allwinner CIR controller"); 380 return (BUS_PROBE_DEFAULT); 381 } 382 383 static int 384 aw_ir_attach(device_t dev) 385 { 386 struct aw_ir_softc *sc; 387 hwreset_t rst_apb; 388 clk_t clk_ir, clk_gate; 389 int err; 390 uint32_t val = 0; 391 392 clk_ir = clk_gate = NULL; 393 rst_apb = NULL; 394 395 sc = device_get_softc(dev); 396 sc->dev = dev; 397 398 if (bus_alloc_resources(dev, aw_ir_spec, sc->res) != 0) { 399 device_printf(dev, "could not allocate memory resource\n"); 400 return (ENXIO); 401 } 402 403 switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) { 404 case A10_IR: 405 sc->fifo_size = 16; 406 break; 407 case A13_IR: 408 sc->fifo_size = 64; 409 break; 410 } 411 412 /* De-assert reset */ 413 if (hwreset_get_by_ofw_name(dev, 0, "apb", &rst_apb) == 0) { 414 err = hwreset_deassert(rst_apb); 415 if (err != 0) { 416 device_printf(dev, "cannot de-assert reset\n"); 417 goto error; 418 } 419 } 420 421 /* Reset buffer */ 422 aw_ir_buf_reset(sc); 423 424 /* Get clocks and enable them */ 425 err = clk_get_by_ofw_name(dev, 0, "apb", &clk_gate); 426 if (err != 0) { 427 device_printf(dev, "Cannot get gate clock\n"); 428 goto error; 429 } 430 err = clk_get_by_ofw_name(dev, 0, "ir", &clk_ir); 431 if (err != 0) { 432 device_printf(dev, "Cannot get IR clock\n"); 433 goto error; 434 } 435 /* Set clock rate */ 436 err = clk_set_freq(clk_ir, AW_IR_BASE_CLK, 0); 437 if (err != 0) { 438 device_printf(dev, "cannot set IR clock rate\n"); 439 goto error; 440 } 441 /* Enable clocks */ 442 err = clk_enable(clk_gate); 443 if (err != 0) { 444 device_printf(dev, "Cannot enable clk gate\n"); 445 goto error; 446 } 447 err = clk_enable(clk_ir); 448 if (err != 0) { 449 device_printf(dev, "Cannot enable IR clock\n"); 450 goto error; 451 } 452 453 if (bus_setup_intr(dev, sc->res[1], 454 INTR_TYPE_MISC | INTR_MPSAFE, NULL, aw_ir_intr, sc, 455 &sc->intrhand)) { 456 bus_release_resources(dev, aw_ir_spec, sc->res); 457 device_printf(dev, "cannot setup interrupt handler\n"); 458 return (ENXIO); 459 } 460 461 /* Enable CIR Mode */ 462 WRITE(sc, AW_IR_CTL, AW_IR_CTL_MD); 463 464 /* 465 * Set clock sample, filter, idle thresholds. 466 * Frequency sample = 3MHz/128 = 23437.5Hz (42.7us) 467 */ 468 val = AW_IR_SAMPLE_128; 469 val |= (AW_IR_RXFILT_VAL | AW_IR_RXIDLE_VAL); 470 val |= (AW_IR_ACTIVE_T | AW_IR_ACTIVE_T_C); 471 WRITE(sc, AW_IR_CIR, val); 472 473 /* Invert Input Signal */ 474 WRITE(sc, AW_IR_RXCTL, AW_IR_RXCTL_RPPI); 475 476 /* Clear All RX Interrupt Status */ 477 WRITE(sc, AW_IR_RXSTA, AW_IR_RXSTA_CLEARALL); 478 479 /* 480 * Enable RX interrupt in case of overflow, packet end 481 * and FIFO available. 482 * RX FIFO Threshold = FIFO size / 2 483 */ 484 WRITE(sc, AW_IR_RXINT, AW_IR_RXINT_ROI_EN | AW_IR_RXINT_RPEI_EN | 485 AW_IR_RXINT_RAI_EN | AW_IR_RXINT_RAL((sc->fifo_size >> 1) - 1)); 486 487 /* Enable IR Module */ 488 val = READ(sc, AW_IR_CTL); 489 WRITE(sc, AW_IR_CTL, val | AW_IR_CTL_GEN | AW_IR_CTL_RXEN); 490 491 sc->sc_evdev = evdev_alloc(); 492 evdev_set_name(sc->sc_evdev, device_get_desc(sc->dev)); 493 evdev_set_phys(sc->sc_evdev, device_get_nameunit(sc->dev)); 494 evdev_set_id(sc->sc_evdev, BUS_HOST, 0, 0, 0); 495 evdev_support_event(sc->sc_evdev, EV_SYN); 496 evdev_support_event(sc->sc_evdev, EV_MSC); 497 evdev_support_msc(sc->sc_evdev, MSC_SCAN); 498 499 err = evdev_register(sc->sc_evdev); 500 if (err) { 501 device_printf(dev, 502 "failed to register evdev: error=%d\n", err); 503 goto error; 504 } 505 506 return (0); 507 error: 508 if (clk_gate != NULL) 509 clk_release(clk_gate); 510 if (clk_ir != NULL) 511 clk_release(clk_ir); 512 if (rst_apb != NULL) 513 hwreset_release(rst_apb); 514 evdev_free(sc->sc_evdev); 515 sc->sc_evdev = NULL; /* Avoid double free */ 516 517 bus_release_resources(dev, aw_ir_spec, sc->res); 518 return (ENXIO); 519 } 520 521 static device_method_t aw_ir_methods[] = { 522 DEVMETHOD(device_probe, aw_ir_probe), 523 DEVMETHOD(device_attach, aw_ir_attach), 524 525 DEVMETHOD_END 526 }; 527 528 static driver_t aw_ir_driver = { 529 "aw_ir", 530 aw_ir_methods, 531 sizeof(struct aw_ir_softc), 532 }; 533 static devclass_t aw_ir_devclass; 534 535 DRIVER_MODULE(aw_ir, simplebus, aw_ir_driver, aw_ir_devclass, 0, 0); 536 MODULE_DEPEND(aw_ir, evdev, 1, 1, 1); 537