1 /*- 2 * Copyright (c) 2016 Ganbold Tsagaankhuu <ganbold@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * Allwinner Consumer IR controller 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/kernel.h> 38 #include <sys/module.h> 39 #include <sys/rman.h> 40 #include <sys/sysctl.h> 41 #include <machine/bus.h> 42 43 #include <dev/ofw/openfirm.h> 44 #include <dev/ofw/ofw_bus.h> 45 #include <dev/ofw/ofw_bus_subr.h> 46 #include <dev/extres/clk/clk.h> 47 #include <dev/extres/hwreset/hwreset.h> 48 49 #include <dev/evdev/input.h> 50 #include <dev/evdev/evdev.h> 51 52 #define READ(_sc, _r) bus_read_4((_sc)->res[0], (_r)) 53 #define WRITE(_sc, _r, _v) bus_write_4((_sc)->res[0], (_r), (_v)) 54 55 /* IR Control */ 56 #define AW_IR_CTL 0x00 57 /* Global Enable */ 58 #define AW_IR_CTL_GEN (1 << 0) 59 /* RX enable */ 60 #define AW_IR_CTL_RXEN (1 << 1) 61 /* CIR mode enable */ 62 #define AW_IR_CTL_MD (1 << 4) | (1 << 5) 63 64 /* RX Config Reg */ 65 #define AW_IR_RXCTL 0x10 66 /* Pulse Polarity Invert flag */ 67 #define AW_IR_RXCTL_RPPI (1 << 2) 68 69 /* RX Data */ 70 #define AW_IR_RXFIFO 0x20 71 72 /* RX Interrupt Control */ 73 #define AW_IR_RXINT 0x2C 74 /* RX FIFO Overflow */ 75 #define AW_IR_RXINT_ROI_EN (1 << 0) 76 /* RX Packet End */ 77 #define AW_IR_RXINT_RPEI_EN (1 << 1) 78 /* RX FIFO Data Available */ 79 #define AW_IR_RXINT_RAI_EN (1 << 4) 80 /* RX FIFO available byte level */ 81 #define AW_IR_RXINT_RAL(val) ((val) << 8) 82 83 /* RX Interrupt Status Reg */ 84 #define AW_IR_RXSTA 0x30 85 /* RX FIFO Get Available Counter */ 86 #define AW_IR_RXSTA_COUNTER(val) (((val) >> 8) & (sc->fifo_size * 2 - 1)) 87 /* Clear all interrupt status */ 88 #define AW_IR_RXSTA_CLEARALL 0xff 89 90 /* IR Sample Configure Reg */ 91 #define AW_IR_CIR 0x34 92 93 /* 94 * Frequency sample: 23437.5Hz (Cycle: 42.7us) 95 * Pulse of NEC Remote > 560us 96 */ 97 /* Filter Threshold = 8 * 42.7 = ~341us < 500us */ 98 #define AW_IR_RXFILT_VAL (((8) & 0x3f) << 2) 99 /* Idle Threshold = (2 + 1) * 128 * 42.7 = ~16.4ms > 9ms */ 100 #define AW_IR_RXIDLE_VAL (((2) & 0xff) << 8) 101 102 /* Bit 15 - value (pulse/space) */ 103 #define VAL_MASK 0x80 104 /* Bits 0:14 - sample duration */ 105 #define PERIOD_MASK 0x7f 106 107 /* Clock rate for IR0 or IR1 clock in CIR mode */ 108 #define AW_IR_BASE_CLK 3000000 109 /* Frequency sample 3MHz/64 = 46875Hz (21.3us) */ 110 #define AW_IR_SAMPLE_64 (0 << 0) 111 /* Frequency sample 3MHz/128 = 23437.5Hz (42.7us) */ 112 #define AW_IR_SAMPLE_128 (1 << 0) 113 114 #define AW_IR_ERROR_CODE 0xffffffff 115 #define AW_IR_REPEAT_CODE 0x0 116 117 /* 80 * 42.7 = ~3.4ms, Lead1(4.5ms) > AW_IR_L1_MIN */ 118 #define AW_IR_L1_MIN 80 119 /* 40 * 42.7 = ~1.7ms, Lead0(4.5ms) Lead0R(2.25ms) > AW_IR_L0_MIN */ 120 #define AW_IR_L0_MIN 40 121 /* 26 * 42.7 = ~1109us ~= 561 * 2, Pulse < AW_IR_PMAX */ 122 #define AW_IR_PMAX 26 123 /* 26 * 42.7 = ~1109us ~= 561 * 2, D1 > AW_IR_DMID, D0 <= AW_IR_DMID */ 124 #define AW_IR_DMID 26 125 /* 53 * 42.7 = ~2263us ~= 561 * 4, D < AW_IR_DMAX */ 126 #define AW_IR_DMAX 53 127 128 /* Active Thresholds */ 129 #define AW_IR_ACTIVE_T ((0 & 0xff) << 16) 130 #define AW_IR_ACTIVE_T_C ((1 & 0xff) << 23) 131 132 /* Code masks */ 133 #define CODE_MASK 0x00ff00ff 134 #define INV_CODE_MASK 0xff00ff00 135 #define VALID_CODE_MASK 0x00ff0000 136 137 #define A10_IR 1 138 #define A13_IR 2 139 140 #define AW_IR_RAW_BUF_SIZE 128 141 142 struct aw_ir_softc { 143 device_t dev; 144 struct resource *res[2]; 145 void * intrhand; 146 int fifo_size; 147 int dcnt; /* Packet Count */ 148 unsigned char buf[AW_IR_RAW_BUF_SIZE]; 149 struct evdev_dev *sc_evdev; 150 }; 151 152 static struct resource_spec aw_ir_spec[] = { 153 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 154 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 155 { -1, 0 } 156 }; 157 158 static struct ofw_compat_data compat_data[] = { 159 { "allwinner,sun4i-a10-ir", A10_IR }, 160 { "allwinner,sun5i-a13-ir", A13_IR }, 161 { NULL, 0 } 162 }; 163 164 static void 165 aw_ir_buf_reset(struct aw_ir_softc *sc) 166 { 167 168 sc->dcnt = 0; 169 } 170 171 static void 172 aw_ir_buf_write(struct aw_ir_softc *sc, unsigned char data) 173 { 174 175 if (sc->dcnt < AW_IR_RAW_BUF_SIZE) 176 sc->buf[sc->dcnt++] = data; 177 else 178 if (bootverbose) 179 device_printf(sc->dev, "IR RX Buffer Full!\n"); 180 } 181 182 static int 183 aw_ir_buf_full(struct aw_ir_softc *sc) 184 { 185 186 return (sc->dcnt >= AW_IR_RAW_BUF_SIZE); 187 } 188 189 static unsigned char 190 aw_ir_read_data(struct aw_ir_softc *sc) 191 { 192 193 return (unsigned char)(READ(sc, AW_IR_RXFIFO) & 0xff); 194 } 195 196 static unsigned long 197 aw_ir_decode_packets(struct aw_ir_softc *sc) 198 { 199 unsigned long len, code; 200 unsigned char val, last; 201 unsigned int active_delay; 202 int i, bitcount; 203 204 if (bootverbose) 205 device_printf(sc->dev, "sc->dcnt = %d\n", sc->dcnt); 206 207 /* Find Lead 1 (bit separator) */ 208 active_delay = (AW_IR_ACTIVE_T + 1) * (AW_IR_ACTIVE_T_C ? 128 : 1); 209 len = 0; 210 len += (active_delay >> 1); 211 if (bootverbose) 212 device_printf(sc->dev, "Initial len: %ld\n", len); 213 for (i = 0; i < sc->dcnt; i++) { 214 val = sc->buf[i]; 215 if (val & VAL_MASK) 216 len += val & PERIOD_MASK; 217 else { 218 if (len > AW_IR_L1_MIN) 219 break; 220 len = 0; 221 } 222 } 223 if (bootverbose) 224 device_printf(sc->dev, "len = %ld\n", len); 225 if ((val & VAL_MASK) || (len <= AW_IR_L1_MIN)) { 226 if (bootverbose) 227 device_printf(sc->dev, "Bit separator error\n"); 228 goto error_code; 229 } 230 231 /* Find Lead 0 (bit length) */ 232 len = 0; 233 for (; i < sc->dcnt; i++) { 234 val = sc->buf[i]; 235 if (val & VAL_MASK) { 236 if(len > AW_IR_L0_MIN) 237 break; 238 len = 0; 239 } else 240 len += val & PERIOD_MASK; 241 } 242 if ((!(val & VAL_MASK)) || (len <= AW_IR_L0_MIN)) { 243 if (bootverbose) 244 device_printf(sc->dev, "Bit length error\n"); 245 goto error_code; 246 } 247 248 /* Start decoding */ 249 code = 0; 250 bitcount = 0; 251 last = 1; 252 len = 0; 253 for (; i < sc->dcnt; i++) { 254 val = sc->buf[i]; 255 if (last) { 256 if (val & VAL_MASK) 257 len += val & PERIOD_MASK; 258 else { 259 if (len > AW_IR_PMAX) { 260 if (bootverbose) 261 device_printf(sc->dev, 262 "Pulse error\n"); 263 goto error_code; 264 } 265 last = 0; 266 len = val & PERIOD_MASK; 267 } 268 } else { 269 if (val & VAL_MASK) { 270 if (len > AW_IR_DMAX) { 271 if (bootverbose) 272 device_printf(sc->dev, 273 "Distant error\n"); 274 goto error_code; 275 } else { 276 if (len > AW_IR_DMID) { 277 /* Decode */ 278 code |= 1 << bitcount; 279 } 280 bitcount++; 281 if (bitcount == 32) 282 break; /* Finish decoding */ 283 } 284 last = 1; 285 len = val & PERIOD_MASK; 286 } else 287 len += val & PERIOD_MASK; 288 } 289 } 290 return (code); 291 292 error_code: 293 294 return (AW_IR_ERROR_CODE); 295 } 296 297 static int 298 aw_ir_validate_code(unsigned long code) 299 { 300 unsigned long v1, v2; 301 302 /* Don't check address */ 303 v1 = code & CODE_MASK; 304 v2 = (code & INV_CODE_MASK) >> 8; 305 306 if (((v1 ^ v2) & VALID_CODE_MASK) == VALID_CODE_MASK) 307 return (0); /* valid */ 308 else 309 return (1); /* invalid */ 310 } 311 312 static void 313 aw_ir_intr(void *arg) 314 { 315 struct aw_ir_softc *sc; 316 uint32_t val; 317 int i, dcnt; 318 unsigned long ir_code; 319 int stat; 320 321 sc = (struct aw_ir_softc *)arg; 322 323 /* Read RX interrupt status */ 324 val = READ(sc, AW_IR_RXSTA); 325 if (bootverbose) 326 device_printf(sc->dev, "RX interrupt status: %x\n", val); 327 328 /* Clean all pending interrupt statuses */ 329 WRITE(sc, AW_IR_RXSTA, val | AW_IR_RXSTA_CLEARALL); 330 331 /* When Rx FIFO Data available or Packet end */ 332 if (val & (AW_IR_RXINT_RAI_EN | AW_IR_RXINT_RPEI_EN)) { 333 if (bootverbose) 334 device_printf(sc->dev, 335 "RX FIFO Data available or Packet end\n"); 336 /* Get available message count in RX FIFO */ 337 dcnt = AW_IR_RXSTA_COUNTER(val); 338 /* Read FIFO */ 339 for (i = 0; i < dcnt; i++) { 340 if (aw_ir_buf_full(sc)) { 341 if (bootverbose) 342 device_printf(sc->dev, 343 "raw buffer full\n"); 344 break; 345 } else 346 aw_ir_buf_write(sc, aw_ir_read_data(sc)); 347 } 348 } 349 350 if (val & AW_IR_RXINT_RPEI_EN) { 351 /* RX Packet end */ 352 if (bootverbose) 353 device_printf(sc->dev, "RX Packet end\n"); 354 ir_code = aw_ir_decode_packets(sc); 355 stat = aw_ir_validate_code(ir_code); 356 if (stat == 0) { 357 evdev_push_event(sc->sc_evdev, 358 EV_MSC, MSC_SCAN, ir_code); 359 evdev_sync(sc->sc_evdev); 360 } 361 if (bootverbose) { 362 device_printf(sc->dev, "Final IR code: %lx\n", 363 ir_code); 364 device_printf(sc->dev, "IR code status: %d\n", 365 stat); 366 } 367 sc->dcnt = 0; 368 } 369 if (val & AW_IR_RXINT_ROI_EN) { 370 /* RX FIFO overflow */ 371 if (bootverbose) 372 device_printf(sc->dev, "RX FIFO overflow\n"); 373 /* Flush raw buffer */ 374 aw_ir_buf_reset(sc); 375 } 376 } 377 378 static int 379 aw_ir_probe(device_t dev) 380 { 381 382 if (!ofw_bus_status_okay(dev)) 383 return (ENXIO); 384 385 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 386 return (ENXIO); 387 388 device_set_desc(dev, "Allwinner CIR controller"); 389 return (BUS_PROBE_DEFAULT); 390 } 391 392 static int 393 aw_ir_attach(device_t dev) 394 { 395 struct aw_ir_softc *sc; 396 hwreset_t rst_apb; 397 clk_t clk_ir, clk_gate; 398 int err; 399 uint32_t val = 0; 400 401 clk_ir = clk_gate = NULL; 402 rst_apb = NULL; 403 404 sc = device_get_softc(dev); 405 sc->dev = dev; 406 407 if (bus_alloc_resources(dev, aw_ir_spec, sc->res) != 0) { 408 device_printf(dev, "could not allocate memory resource\n"); 409 return (ENXIO); 410 } 411 412 switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) { 413 case A10_IR: 414 sc->fifo_size = 16; 415 break; 416 case A13_IR: 417 sc->fifo_size = 64; 418 break; 419 } 420 421 /* De-assert reset */ 422 if (hwreset_get_by_ofw_idx(dev, 0, 0, &rst_apb) == 0) { 423 err = hwreset_deassert(rst_apb); 424 if (err != 0) { 425 device_printf(dev, "cannot de-assert reset\n"); 426 goto error; 427 } 428 } 429 430 /* Reset buffer */ 431 aw_ir_buf_reset(sc); 432 433 /* Get clocks and enable them */ 434 err = clk_get_by_ofw_name(dev, 0, "apb", &clk_gate); 435 if (err != 0) { 436 device_printf(dev, "Cannot get gate clock\n"); 437 goto error; 438 } 439 err = clk_get_by_ofw_name(dev, 0, "ir", &clk_ir); 440 if (err != 0) { 441 device_printf(dev, "Cannot get IR clock\n"); 442 goto error; 443 } 444 /* Set clock rate */ 445 err = clk_set_freq(clk_ir, AW_IR_BASE_CLK, 0); 446 if (err != 0) { 447 device_printf(dev, "cannot set IR clock rate\n"); 448 goto error; 449 } 450 /* Enable clocks */ 451 err = clk_enable(clk_gate); 452 if (err != 0) { 453 device_printf(dev, "Cannot enable clk gate\n"); 454 goto error; 455 } 456 err = clk_enable(clk_ir); 457 if (err != 0) { 458 device_printf(dev, "Cannot enable IR clock\n"); 459 goto error; 460 } 461 462 if (bus_setup_intr(dev, sc->res[1], 463 INTR_TYPE_MISC | INTR_MPSAFE, NULL, aw_ir_intr, sc, 464 &sc->intrhand)) { 465 bus_release_resources(dev, aw_ir_spec, sc->res); 466 device_printf(dev, "cannot setup interrupt handler\n"); 467 return (ENXIO); 468 } 469 470 /* Enable CIR Mode */ 471 WRITE(sc, AW_IR_CTL, AW_IR_CTL_MD); 472 473 /* 474 * Set clock sample, filter, idle thresholds. 475 * Frequency sample = 3MHz/128 = 23437.5Hz (42.7us) 476 */ 477 val = AW_IR_SAMPLE_128; 478 val |= (AW_IR_RXFILT_VAL | AW_IR_RXIDLE_VAL); 479 val |= (AW_IR_ACTIVE_T | AW_IR_ACTIVE_T_C); 480 WRITE(sc, AW_IR_CIR, val); 481 482 /* Invert Input Signal */ 483 WRITE(sc, AW_IR_RXCTL, AW_IR_RXCTL_RPPI); 484 485 /* Clear All RX Interrupt Status */ 486 WRITE(sc, AW_IR_RXSTA, AW_IR_RXSTA_CLEARALL); 487 488 /* 489 * Enable RX interrupt in case of overflow, packet end 490 * and FIFO available. 491 * RX FIFO Threshold = FIFO size / 2 492 */ 493 WRITE(sc, AW_IR_RXINT, AW_IR_RXINT_ROI_EN | AW_IR_RXINT_RPEI_EN | 494 AW_IR_RXINT_RAI_EN | AW_IR_RXINT_RAL((sc->fifo_size >> 1) - 1)); 495 496 /* Enable IR Module */ 497 val = READ(sc, AW_IR_CTL); 498 WRITE(sc, AW_IR_CTL, val | AW_IR_CTL_GEN | AW_IR_CTL_RXEN); 499 500 sc->sc_evdev = evdev_alloc(); 501 evdev_set_name(sc->sc_evdev, device_get_desc(sc->dev)); 502 evdev_set_phys(sc->sc_evdev, device_get_nameunit(sc->dev)); 503 evdev_set_id(sc->sc_evdev, BUS_HOST, 0, 0, 0); 504 evdev_support_event(sc->sc_evdev, EV_SYN); 505 evdev_support_event(sc->sc_evdev, EV_MSC); 506 evdev_support_msc(sc->sc_evdev, MSC_SCAN); 507 508 err = evdev_register(sc->sc_evdev); 509 if (err) { 510 device_printf(dev, 511 "failed to register evdev: error=%d\n", err); 512 goto error; 513 } 514 515 return (0); 516 error: 517 if (clk_gate != NULL) 518 clk_release(clk_gate); 519 if (clk_ir != NULL) 520 clk_release(clk_ir); 521 if (rst_apb != NULL) 522 hwreset_release(rst_apb); 523 evdev_free(sc->sc_evdev); 524 sc->sc_evdev = NULL; /* Avoid double free */ 525 526 bus_release_resources(dev, aw_ir_spec, sc->res); 527 return (ENXIO); 528 } 529 530 static device_method_t aw_ir_methods[] = { 531 DEVMETHOD(device_probe, aw_ir_probe), 532 DEVMETHOD(device_attach, aw_ir_attach), 533 534 DEVMETHOD_END 535 }; 536 537 static driver_t aw_ir_driver = { 538 "aw_ir", 539 aw_ir_methods, 540 sizeof(struct aw_ir_softc), 541 }; 542 static devclass_t aw_ir_devclass; 543 544 DRIVER_MODULE(aw_ir, simplebus, aw_ir_driver, aw_ir_devclass, 0, 0); 545 MODULE_DEPEND(aw_ir, evdev, 1, 1, 1); 546