1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2020 Oleksandr Tymoshenko <gonzo@FreeBSD.org> 5 * Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/kernel.h> 36 #include <sys/lock.h> 37 #include <sys/module.h> 38 #include <sys/mutex.h> 39 #include <sys/rman.h> 40 #include <sys/resource.h> 41 #include <machine/bus.h> 42 #include <sys/gpio.h> 43 44 #include <dev/ofw/ofw_bus.h> 45 #include <dev/ofw/ofw_bus_subr.h> 46 47 #include <dev/extres/clk/clk.h> 48 #include <dev/extres/hwreset/hwreset.h> 49 50 #include <dev/gpio/gpiobusvar.h> 51 52 #include "opt_snd.h" 53 #include <dev/sound/pcm/sound.h> 54 #include <dev/sound/fdt/audio_dai.h> 55 #include "audio_dai_if.h" 56 57 #define SYSCLK_CTL 0x00c 58 #define AIF1CLK_ENA (1 << 11) 59 #define AIF1CLK_SRC_MASK (3 << 8) 60 #define AIF1CLK_SRC_PLL (2 << 8) 61 #define SYSCLK_ENA (1 << 3) 62 #define SYSCLK_SRC (1 << 0) 63 64 #define MOD_CLK_ENA 0x010 65 #define MOD_RST_CTL 0x014 66 #define MOD_AIF1 (1 << 15) 67 #define MOD_ADC (1 << 3) 68 #define MOD_DAC (1 << 2) 69 70 #define SYS_SR_CTRL 0x018 71 #define AIF1_FS_MASK (0xf << 12) 72 #define AIF_FS_48KHZ (8 << 12) 73 74 #define AIF1CLK_CTRL 0x040 75 #define AIF1_MSTR_MOD (1 << 15) 76 #define AIF1_BCLK_INV (1 << 14) 77 #define AIF1_LRCK_INV (1 << 13) 78 #define AIF1_BCLK_DIV_MASK (0xf << 9) 79 #define AIF1_BCLK_DIV_16 (6 << 9) 80 #define AIF1_LRCK_DIV_MASK (7 << 6) 81 #define AIF1_LRCK_DIV_16 (0 << 6) 82 #define AIF1_LRCK_DIV_64 (2 << 6) 83 #define AIF1_WORD_SIZ_MASK (3 << 4) 84 #define AIF1_WORD_SIZ_16 (1 << 4) 85 #define AIF1_DATA_FMT_MASK (3 << 2) 86 #define AIF1_DATA_FMT_I2S (0 << 2) 87 #define AIF1_DATA_FMT_LJ (1 << 2) 88 #define AIF1_DATA_FMT_RJ (2 << 2) 89 #define AIF1_DATA_FMT_DSP (3 << 2) 90 91 #define AIF1_ADCDAT_CTRL 0x044 92 #define AIF1_ADC0L_ENA (1 << 15) 93 #define AIF1_ADC0R_ENA (1 << 14) 94 95 #define AIF1_DACDAT_CTRL 0x048 96 #define AIF1_DAC0L_ENA (1 << 15) 97 #define AIF1_DAC0R_ENA (1 << 14) 98 99 #define AIF1_MXR_SRC 0x04c 100 #define AIF1L_MXR_SRC_MASK (0xf << 12) 101 #define AIF1L_MXR_SRC_AIF1 (0x8 << 12) 102 #define AIF1L_MXR_SRC_ADC (0x2 << 12) 103 #define AIF1R_MXR_SRC_MASK (0xf << 8) 104 #define AIF1R_MXR_SRC_AIF1 (0x8 << 8) 105 #define AIF1R_MXR_SRC_ADC (0x2 << 8) 106 107 #define ADC_DIG_CTRL 0x100 108 #define ADC_DIG_CTRL_ENAD (1 << 15) 109 110 #define HMIC_CTRL1 0x110 111 #define HMIC_CTRL1_N_MASK (0xf << 8) 112 #define HMIC_CTRL1_N(n) (((n) & 0xf) << 8) 113 #define HMIC_CTRL1_JACK_IN_IRQ_EN (1 << 4) 114 #define HMIC_CTRL1_JACK_OUT_IRQ_EN (1 << 3) 115 #define HMIC_CTRL1_MIC_DET_IRQ_EN (1 << 0) 116 117 #define HMIC_CTRL2 0x114 118 #define HMIC_CTRL2_MDATA_THRES __BITS(12,8) 119 120 #define HMIC_STS 0x118 121 #define HMIC_STS_MIC_PRESENT (1 << 6) 122 #define HMIC_STS_JACK_DET_OIRQ (1 << 4) 123 #define HMIC_STS_JACK_DET_IIRQ (1 << 3) 124 #define HMIC_STS_MIC_DET_ST (1 << 0) 125 126 #define DAC_DIG_CTRL 0x120 127 #define DAC_DIG_CTRL_ENDA (1 << 15) 128 129 #define DAC_MXR_SRC 0x130 130 #define DACL_MXR_SRC_MASK (0xf << 12) 131 #define DACL_MXR_SRC_AIF1_DAC0L (0x8 << 12) 132 #define DACR_MXR_SRC_MASK (0xf << 8) 133 #define DACR_MXR_SRC_AIF1_DAC0R (0x8 << 8) 134 135 static struct ofw_compat_data compat_data[] = { 136 { "allwinner,sun8i-a33-codec", 1}, 137 { NULL, 0 } 138 }; 139 140 static struct resource_spec sun8i_codec_spec[] = { 141 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 142 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 143 { -1, 0 } 144 }; 145 146 struct sun8i_codec_softc { 147 device_t dev; 148 struct resource *res[2]; 149 struct mtx mtx; 150 clk_t clk_gate; 151 clk_t clk_mod; 152 void * intrhand; 153 }; 154 155 #define CODEC_LOCK(sc) mtx_lock(&(sc)->mtx) 156 #define CODEC_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 157 #define CODEC_READ(sc, reg) bus_read_4((sc)->res[0], (reg)) 158 #define CODEC_WRITE(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val)) 159 160 static int sun8i_codec_probe(device_t dev); 161 static int sun8i_codec_attach(device_t dev); 162 static int sun8i_codec_detach(device_t dev); 163 164 static int 165 sun8i_codec_probe(device_t dev) 166 { 167 if (!ofw_bus_status_okay(dev)) 168 return (ENXIO); 169 170 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) 171 return (ENXIO); 172 173 device_set_desc(dev, "Allwinner Codec"); 174 return (BUS_PROBE_DEFAULT); 175 } 176 177 static int 178 sun8i_codec_attach(device_t dev) 179 { 180 struct sun8i_codec_softc *sc; 181 int error; 182 uint32_t val; 183 struct gpiobus_pin *pa_pin; 184 phandle_t node; 185 186 sc = device_get_softc(dev); 187 sc->dev = dev; 188 node = ofw_bus_get_node(dev); 189 190 mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); 191 192 if (bus_alloc_resources(dev, sun8i_codec_spec, sc->res) != 0) { 193 device_printf(dev, "cannot allocate resources for device\n"); 194 error = ENXIO; 195 goto fail; 196 } 197 198 error = clk_get_by_ofw_name(dev, 0, "mod", &sc->clk_mod); 199 if (error != 0) { 200 device_printf(dev, "cannot get \"mod\" clock\n"); 201 goto fail; 202 } 203 204 error = clk_get_by_ofw_name(dev, 0, "bus", &sc->clk_gate); 205 if (error != 0) { 206 device_printf(dev, "cannot get \"bus\" clock\n"); 207 goto fail; 208 } 209 210 error = clk_enable(sc->clk_gate); 211 if (error != 0) { 212 device_printf(dev, "cannot enable \"bus\" clock\n"); 213 goto fail; 214 } 215 216 /* Enable clocks */ 217 val = CODEC_READ(sc, SYSCLK_CTL); 218 val |= AIF1CLK_ENA; 219 val &= ~AIF1CLK_SRC_MASK; 220 val |= AIF1CLK_SRC_PLL; 221 val |= SYSCLK_ENA; 222 val &= ~SYSCLK_SRC; 223 CODEC_WRITE(sc, SYSCLK_CTL, val); 224 CODEC_WRITE(sc, MOD_CLK_ENA, MOD_AIF1 | MOD_ADC | MOD_DAC); 225 CODEC_WRITE(sc, MOD_RST_CTL, MOD_AIF1 | MOD_ADC | MOD_DAC); 226 227 /* Enable digital parts */ 228 CODEC_WRITE(sc, DAC_DIG_CTRL, DAC_DIG_CTRL_ENDA); 229 CODEC_WRITE(sc, ADC_DIG_CTRL, ADC_DIG_CTRL_ENAD); 230 231 /* Set AIF1 to 48 kHz */ 232 val = CODEC_READ(sc, SYS_SR_CTRL); 233 val &= ~AIF1_FS_MASK; 234 val |= AIF_FS_48KHZ; 235 CODEC_WRITE(sc, SYS_SR_CTRL, val); 236 237 /* Set AIF1 to 16-bit */ 238 val = CODEC_READ(sc, AIF1CLK_CTRL); 239 val &= ~AIF1_WORD_SIZ_MASK; 240 val |= AIF1_WORD_SIZ_16; 241 CODEC_WRITE(sc, AIF1CLK_CTRL, val); 242 243 /* Enable AIF1 DAC timelot 0 */ 244 val = CODEC_READ(sc, AIF1_DACDAT_CTRL); 245 val |= AIF1_DAC0L_ENA; 246 val |= AIF1_DAC0R_ENA; 247 CODEC_WRITE(sc, AIF1_DACDAT_CTRL, val); 248 249 /* Enable AIF1 ADC timelot 0 */ 250 val = CODEC_READ(sc, AIF1_ADCDAT_CTRL); 251 val |= AIF1_ADC0L_ENA; 252 val |= AIF1_ADC0R_ENA; 253 CODEC_WRITE(sc, AIF1_ADCDAT_CTRL, val); 254 255 /* DAC mixer source select */ 256 val = CODEC_READ(sc, DAC_MXR_SRC); 257 val &= ~DACL_MXR_SRC_MASK; 258 val |= DACL_MXR_SRC_AIF1_DAC0L; 259 val &= ~DACR_MXR_SRC_MASK; 260 val |= DACR_MXR_SRC_AIF1_DAC0R; 261 CODEC_WRITE(sc, DAC_MXR_SRC, val); 262 263 /* ADC mixer source select */ 264 val = CODEC_READ(sc, AIF1_MXR_SRC); 265 val &= ~AIF1L_MXR_SRC_MASK; 266 val |= AIF1L_MXR_SRC_ADC; 267 val &= ~AIF1R_MXR_SRC_MASK; 268 val |= AIF1R_MXR_SRC_ADC; 269 CODEC_WRITE(sc, AIF1_MXR_SRC, val); 270 271 /* Enable PA power */ 272 /* Unmute PA */ 273 if (gpio_pin_get_by_ofw_property(dev, node, "allwinner,pa-gpios", 274 &pa_pin) == 0) { 275 error = gpio_pin_set_active(pa_pin, 1); 276 if (error != 0) 277 device_printf(dev, "failed to unmute PA\n"); 278 } 279 280 OF_device_register_xref(OF_xref_from_node(node), dev); 281 282 return (0); 283 284 fail: 285 sun8i_codec_detach(dev); 286 return (error); 287 } 288 289 static int 290 sun8i_codec_detach(device_t dev) 291 { 292 struct sun8i_codec_softc *sc; 293 294 sc = device_get_softc(dev); 295 296 if (sc->clk_gate) 297 clk_release(sc->clk_gate); 298 299 if (sc->clk_mod) 300 clk_release(sc->clk_mod); 301 302 if (sc->intrhand != NULL) 303 bus_teardown_intr(sc->dev, sc->res[1], sc->intrhand); 304 305 bus_release_resources(dev, sun8i_codec_spec, sc->res); 306 mtx_destroy(&sc->mtx); 307 308 return (0); 309 } 310 311 static int 312 sun8i_codec_dai_init(device_t dev, uint32_t format) 313 { 314 struct sun8i_codec_softc *sc; 315 int fmt, pol, clk; 316 uint32_t val; 317 318 sc = device_get_softc(dev); 319 320 fmt = AUDIO_DAI_FORMAT_FORMAT(format); 321 pol = AUDIO_DAI_FORMAT_POLARITY(format); 322 clk = AUDIO_DAI_FORMAT_CLOCK(format); 323 324 val = CODEC_READ(sc, AIF1CLK_CTRL); 325 326 val &= ~AIF1_DATA_FMT_MASK; 327 switch (fmt) { 328 case AUDIO_DAI_FORMAT_I2S: 329 val |= AIF1_DATA_FMT_I2S; 330 break; 331 case AUDIO_DAI_FORMAT_RJ: 332 val |= AIF1_DATA_FMT_RJ; 333 break; 334 case AUDIO_DAI_FORMAT_LJ: 335 val |= AIF1_DATA_FMT_LJ; 336 break; 337 case AUDIO_DAI_FORMAT_DSPA: 338 case AUDIO_DAI_FORMAT_DSPB: 339 val |= AIF1_DATA_FMT_DSP; 340 break; 341 default: 342 return EINVAL; 343 } 344 345 val &= ~(AIF1_BCLK_INV|AIF1_LRCK_INV); 346 /* Codec LRCK polarity is inverted (datasheet is wrong) */ 347 if (!AUDIO_DAI_POLARITY_INVERTED_FRAME(pol)) 348 val |= AIF1_LRCK_INV; 349 if (AUDIO_DAI_POLARITY_INVERTED_BCLK(pol)) 350 val |= AIF1_BCLK_INV; 351 352 switch (clk) { 353 case AUDIO_DAI_CLOCK_CBM_CFM: 354 val &= ~AIF1_MSTR_MOD; /* codec is master */ 355 break; 356 case AUDIO_DAI_CLOCK_CBS_CFS: 357 val |= AIF1_MSTR_MOD; /* codec is slave */ 358 break; 359 default: 360 return EINVAL; 361 } 362 363 val &= ~AIF1_LRCK_DIV_MASK; 364 val |= AIF1_LRCK_DIV_64; 365 366 val &= ~AIF1_BCLK_DIV_MASK; 367 val |= AIF1_BCLK_DIV_16; 368 369 CODEC_WRITE(sc, AIF1CLK_CTRL, val); 370 371 return (0); 372 } 373 374 static int 375 sun8i_codec_dai_trigger(device_t dev, int go, int pcm_dir) 376 { 377 378 return (0); 379 } 380 381 static int 382 sun8i_codec_dai_setup_mixer(device_t dev, device_t pcmdev) 383 { 384 385 /* Do nothing for now */ 386 return (0); 387 } 388 389 390 static device_method_t sun8i_codec_methods[] = { 391 /* Device interface */ 392 DEVMETHOD(device_probe, sun8i_codec_probe), 393 DEVMETHOD(device_attach, sun8i_codec_attach), 394 DEVMETHOD(device_detach, sun8i_codec_detach), 395 396 DEVMETHOD(audio_dai_init, sun8i_codec_dai_init), 397 DEVMETHOD(audio_dai_setup_mixer, sun8i_codec_dai_setup_mixer), 398 DEVMETHOD(audio_dai_trigger, sun8i_codec_dai_trigger), 399 400 DEVMETHOD_END 401 }; 402 403 static driver_t sun8i_codec_driver = { 404 "sun8icodec", 405 sun8i_codec_methods, 406 sizeof(struct sun8i_codec_softc), 407 }; 408 409 DRIVER_MODULE(sun8i_codec, simplebus, sun8i_codec_driver, 0, 0); 410 SIMPLEBUS_PNP_INFO(compat_data); 411