xref: /freebsd/sys/arm/allwinner/a20/a20_cpu_cfg.h (revision 95ee2897e98f5d444f26ed2334cc7c439f9c16c6)
1696ec285SGanbold Tsagaankhuu /*-
2*4d846d26SWarner Losh  * SPDX-License-Identifier: BSD-2-Clause
3af3dc4a7SPedro F. Giffuni  *
4fe47fb7bSGanbold Tsagaankhuu  * Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold@freebsd.org>
5696ec285SGanbold Tsagaankhuu  * All rights reserved.
6696ec285SGanbold Tsagaankhuu  *
7696ec285SGanbold Tsagaankhuu  * Redistribution and use in source and binary forms, with or without
8696ec285SGanbold Tsagaankhuu  * modification, are permitted provided that the following conditions
9696ec285SGanbold Tsagaankhuu  * are met:
10696ec285SGanbold Tsagaankhuu  * 1. Redistributions of source code must retain the above copyright
11696ec285SGanbold Tsagaankhuu  *    notice, this list of conditions and the following disclaimer.
12696ec285SGanbold Tsagaankhuu  * 2. Redistributions in binary form must reproduce the above copyright
13696ec285SGanbold Tsagaankhuu  *    notice, this list of conditions and the following disclaimer in the
14696ec285SGanbold Tsagaankhuu  *    documentation and/or other materials provided with the distribution.
15696ec285SGanbold Tsagaankhuu  *
16696ec285SGanbold Tsagaankhuu  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17696ec285SGanbold Tsagaankhuu  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18696ec285SGanbold Tsagaankhuu  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19696ec285SGanbold Tsagaankhuu  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20696ec285SGanbold Tsagaankhuu  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21696ec285SGanbold Tsagaankhuu  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22696ec285SGanbold Tsagaankhuu  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION
23696ec285SGanbold Tsagaankhuu  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24696ec285SGanbold Tsagaankhuu  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY
25696ec285SGanbold Tsagaankhuu  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26696ec285SGanbold Tsagaankhuu  * SUCH DAMAGE.
27696ec285SGanbold Tsagaankhuu  */
28696ec285SGanbold Tsagaankhuu 
29696ec285SGanbold Tsagaankhuu #ifndef _A20_CPU_CFG_H_
30696ec285SGanbold Tsagaankhuu #define _A20_CPU_CFG_H_
31696ec285SGanbold Tsagaankhuu 
32696ec285SGanbold Tsagaankhuu #define CPU_CFG_BASE		0xe1c25c00
33696ec285SGanbold Tsagaankhuu 
34696ec285SGanbold Tsagaankhuu #define CPU0_RST_CTRL		0x0040
35696ec285SGanbold Tsagaankhuu #define CPU0_CTRL_REG		0x0044
36696ec285SGanbold Tsagaankhuu #define CPU0_STATUS_REG 	0x0048
37696ec285SGanbold Tsagaankhuu 
38696ec285SGanbold Tsagaankhuu #define CPU1_RST_CTRL		0x0080
39696ec285SGanbold Tsagaankhuu #define CPU1_CTRL_REG		0x0084
40696ec285SGanbold Tsagaankhuu #define CPU1_STATUS_REG 	0x0088
41696ec285SGanbold Tsagaankhuu 
42696ec285SGanbold Tsagaankhuu #define GENER_CTRL_REG		0x0184
43696ec285SGanbold Tsagaankhuu 
44696ec285SGanbold Tsagaankhuu #define EVENT_IN_REG		0x0190
45696ec285SGanbold Tsagaankhuu #define PRIVATE_REG		0x01a4
46696ec285SGanbold Tsagaankhuu 
47696ec285SGanbold Tsagaankhuu #define IDLE_CNT0_LOW_REG	0x0200
48696ec285SGanbold Tsagaankhuu #define IDLE_CNT0_HIGH_REG	0x0204
49696ec285SGanbold Tsagaankhuu #define IDLE_CNT0_CTRL_REG	0x0208
50696ec285SGanbold Tsagaankhuu 
51696ec285SGanbold Tsagaankhuu #define IDLE_CNT1_LOW_REG	0x0210
52696ec285SGanbold Tsagaankhuu #define IDLE_CNT1_HIGH_REG	0x0214
53696ec285SGanbold Tsagaankhuu #define IDLE_CNT1_CTRL_REG	0x0218
54696ec285SGanbold Tsagaankhuu 
55696ec285SGanbold Tsagaankhuu #define OSC24M_CNT64_CTRL_REG	0x0280
56696ec285SGanbold Tsagaankhuu #define OSC24M_CNT64_LOW_REG	0x0284
57696ec285SGanbold Tsagaankhuu #define OSC24M_CNT64_HIGH_REG	0x0288
58696ec285SGanbold Tsagaankhuu 
59696ec285SGanbold Tsagaankhuu #define LOSC_CNT64_CTRL_REG	0x0290
60696ec285SGanbold Tsagaankhuu #define LOSC_CNT64_LOW_REG	0x0294
61696ec285SGanbold Tsagaankhuu #define LOSC_CNT64_HIGH_REG	0x0298
62696ec285SGanbold Tsagaankhuu 
63696ec285SGanbold Tsagaankhuu #define CNT64_RL_EN		0x02 /* read latch enable */
64696ec285SGanbold Tsagaankhuu 
65696ec285SGanbold Tsagaankhuu uint64_t a20_read_counter64(void);
66696ec285SGanbold Tsagaankhuu 
67696ec285SGanbold Tsagaankhuu #endif /* _A20_CPU_CFG_H_ */
68