1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold@freebsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 #include <sys/kernel.h> 33 #include <sys/module.h> 34 #include <sys/malloc.h> 35 #include <sys/rman.h> 36 #include <sys/timeet.h> 37 #include <sys/timetc.h> 38 #include <sys/watchdog.h> 39 #include <machine/bus.h> 40 #include <machine/cpu.h> 41 #include <machine/frame.h> 42 #include <machine/intr.h> 43 44 #include <dev/ofw/openfirm.h> 45 #include <dev/ofw/ofw_bus.h> 46 #include <dev/ofw/ofw_bus_subr.h> 47 48 #include "a10_sramc.h" 49 50 #define SRAM_CTL1_CFG 0x04 51 #define CTL1_CFG_SRAMD_MAP_USB0 (1 << 0) 52 53 struct a10_sramc_softc { 54 struct resource *res; 55 bus_space_tag_t bst; 56 bus_space_handle_t bsh; 57 }; 58 59 static struct a10_sramc_softc *a10_sramc_sc; 60 61 #define sramc_read_4(sc, reg) \ 62 bus_space_read_4((sc)->bst, (sc)->bsh, (reg)) 63 #define sramc_write_4(sc, reg, val) \ 64 bus_space_write_4((sc)->bst, (sc)->bsh, (reg), (val)) 65 66 static int 67 a10_sramc_probe(device_t dev) 68 { 69 70 if (ofw_bus_is_compatible(dev, "allwinner,sun4i-a10-sram-controller")) { 71 device_set_desc(dev, "Allwinner sramc module"); 72 return (BUS_PROBE_DEFAULT); 73 } 74 75 return (ENXIO); 76 } 77 78 static int 79 a10_sramc_attach(device_t dev) 80 { 81 struct a10_sramc_softc *sc = device_get_softc(dev); 82 int rid = 0; 83 84 sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); 85 if (!sc->res) { 86 device_printf(dev, "could not allocate resource\n"); 87 return (ENXIO); 88 } 89 90 sc->bst = rman_get_bustag(sc->res); 91 sc->bsh = rman_get_bushandle(sc->res); 92 93 a10_sramc_sc = sc; 94 95 return (0); 96 } 97 98 static device_method_t a10_sramc_methods[] = { 99 DEVMETHOD(device_probe, a10_sramc_probe), 100 DEVMETHOD(device_attach, a10_sramc_attach), 101 { 0, 0 } 102 }; 103 104 static driver_t a10_sramc_driver = { 105 "a10_sramc", 106 a10_sramc_methods, 107 sizeof(struct a10_sramc_softc), 108 }; 109 110 EARLY_DRIVER_MODULE(a10_sramc, simplebus, a10_sramc_driver, 0, 0, 111 BUS_PASS_SUPPORTDEV + BUS_PASS_ORDER_FIRST); 112 113 int 114 a10_map_to_emac(void) 115 { 116 struct a10_sramc_softc *sc = a10_sramc_sc; 117 uint32_t reg_value; 118 119 if (sc == NULL) 120 return (ENXIO); 121 122 /* Map SRAM to EMAC, set bit 2 and 4. */ 123 reg_value = sramc_read_4(sc, SRAM_CTL1_CFG); 124 reg_value |= 0x5 << 2; 125 sramc_write_4(sc, SRAM_CTL1_CFG, reg_value); 126 127 return (0); 128 } 129 130 int 131 a10_map_to_otg(void) 132 { 133 struct a10_sramc_softc *sc = a10_sramc_sc; 134 uint32_t reg_value; 135 136 if (sc == NULL) 137 return (ENXIO); 138 139 /* Map SRAM to OTG */ 140 reg_value = sramc_read_4(sc, SRAM_CTL1_CFG); 141 reg_value |= CTL1_CFG_SRAMD_MAP_USB0; 142 sramc_write_4(sc, SRAM_CTL1_CFG, reg_value); 143 144 return (0); 145 } 146