1 /*- 2 * Copyright (c) 2014-2016 Jared D. McNeill <jmcneill@invisible.ca> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27 28 /* 29 * Allwinner A10/A20 DMA controller 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/rman.h> 39 #include <sys/condvar.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/module.h> 43 #include <sys/mutex.h> 44 45 #include <machine/bus.h> 46 47 #include <dev/ofw/ofw_bus.h> 48 #include <dev/ofw/ofw_bus_subr.h> 49 50 #include <arm/allwinner/a10_dmac.h> 51 #include <dev/extres/clk/clk.h> 52 53 #include "sunxi_dma_if.h" 54 55 #define NDMA_CHANNELS 8 56 #define DDMA_CHANNELS 8 57 58 enum a10dmac_type { 59 CH_NDMA, 60 CH_DDMA 61 }; 62 63 struct a10dmac_softc; 64 65 struct a10dmac_channel { 66 struct a10dmac_softc * ch_sc; 67 uint8_t ch_index; 68 enum a10dmac_type ch_type; 69 void (*ch_callback)(void *); 70 void * ch_callbackarg; 71 uint32_t ch_regoff; 72 }; 73 74 struct a10dmac_softc { 75 struct resource * sc_res[2]; 76 struct mtx sc_mtx; 77 void * sc_ih; 78 79 struct a10dmac_channel sc_ndma_channels[NDMA_CHANNELS]; 80 struct a10dmac_channel sc_ddma_channels[DDMA_CHANNELS]; 81 }; 82 83 static struct resource_spec a10dmac_spec[] = { 84 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 85 { SYS_RES_IRQ, 0, RF_ACTIVE }, 86 { -1, 0 } 87 }; 88 89 #define DMA_READ(sc, reg) bus_read_4((sc)->sc_res[0], (reg)) 90 #define DMA_WRITE(sc, reg, val) bus_write_4((sc)->sc_res[0], (reg), (val)) 91 #define DMACH_READ(ch, reg) \ 92 DMA_READ((ch)->ch_sc, (reg) + (ch)->ch_regoff) 93 #define DMACH_WRITE(ch, reg, val) \ 94 DMA_WRITE((ch)->ch_sc, (reg) + (ch)->ch_regoff, (val)) 95 96 static void a10dmac_intr(void *); 97 98 static int 99 a10dmac_probe(device_t dev) 100 { 101 if (!ofw_bus_status_okay(dev)) 102 return (ENXIO); 103 104 if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-a10-dma")) 105 return (ENXIO); 106 107 device_set_desc(dev, "Allwinner DMA controller"); 108 return (BUS_PROBE_DEFAULT); 109 } 110 111 static int 112 a10dmac_attach(device_t dev) 113 { 114 struct a10dmac_softc *sc; 115 unsigned int index; 116 clk_t clk; 117 int error; 118 119 sc = device_get_softc(dev); 120 121 if (bus_alloc_resources(dev, a10dmac_spec, sc->sc_res)) { 122 device_printf(dev, "cannot allocate resources for device\n"); 123 return (ENXIO); 124 } 125 126 mtx_init(&sc->sc_mtx, "a10 dmac", NULL, MTX_SPIN); 127 128 /* Activate DMA controller clock */ 129 error = clk_get_by_ofw_index(dev, 0, 0, &clk); 130 if (error != 0) { 131 device_printf(dev, "cannot get clock\n"); 132 return (error); 133 } 134 error = clk_enable(clk); 135 if (error != 0) { 136 device_printf(dev, "cannot enable clock\n"); 137 return (error); 138 } 139 140 /* Disable all interrupts and clear pending status */ 141 DMA_WRITE(sc, AWIN_DMA_IRQ_EN_REG, 0); 142 DMA_WRITE(sc, AWIN_DMA_IRQ_PEND_STA_REG, ~0); 143 144 /* Initialize channels */ 145 for (index = 0; index < NDMA_CHANNELS; index++) { 146 sc->sc_ndma_channels[index].ch_sc = sc; 147 sc->sc_ndma_channels[index].ch_index = index; 148 sc->sc_ndma_channels[index].ch_type = CH_NDMA; 149 sc->sc_ndma_channels[index].ch_callback = NULL; 150 sc->sc_ndma_channels[index].ch_callbackarg = NULL; 151 sc->sc_ndma_channels[index].ch_regoff = AWIN_NDMA_REG(index); 152 DMACH_WRITE(&sc->sc_ndma_channels[index], AWIN_NDMA_CTL_REG, 0); 153 } 154 for (index = 0; index < DDMA_CHANNELS; index++) { 155 sc->sc_ddma_channels[index].ch_sc = sc; 156 sc->sc_ddma_channels[index].ch_index = index; 157 sc->sc_ddma_channels[index].ch_type = CH_DDMA; 158 sc->sc_ddma_channels[index].ch_callback = NULL; 159 sc->sc_ddma_channels[index].ch_callbackarg = NULL; 160 sc->sc_ddma_channels[index].ch_regoff = AWIN_DDMA_REG(index); 161 DMACH_WRITE(&sc->sc_ddma_channels[index], AWIN_DDMA_CTL_REG, 0); 162 } 163 164 error = bus_setup_intr(dev, sc->sc_res[1], INTR_MPSAFE | INTR_TYPE_MISC, 165 NULL, a10dmac_intr, sc, &sc->sc_ih); 166 if (error != 0) { 167 device_printf(dev, "could not setup interrupt handler\n"); 168 bus_release_resources(dev, a10dmac_spec, sc->sc_res); 169 mtx_destroy(&sc->sc_mtx); 170 return (ENXIO); 171 } 172 173 OF_device_register_xref(OF_xref_from_node(ofw_bus_get_node(dev)), dev); 174 return (0); 175 } 176 177 static void 178 a10dmac_intr(void *priv) 179 { 180 struct a10dmac_softc *sc = priv; 181 uint32_t sta, bit, mask; 182 uint8_t index; 183 184 sta = DMA_READ(sc, AWIN_DMA_IRQ_PEND_STA_REG); 185 DMA_WRITE(sc, AWIN_DMA_IRQ_PEND_STA_REG, sta); 186 187 while ((bit = ffs(sta & AWIN_DMA_IRQ_END_MASK)) != 0) { 188 mask = (1U << (bit - 1)); 189 sta &= ~mask; 190 /* 191 * Map status bit to channel number. The status register is 192 * encoded with two bits of status per channel (lowest bit 193 * is half transfer pending, highest bit is end transfer 194 * pending). The 8 normal DMA channel status are in the lower 195 * 16 bits and the 8 dedicated DMA channel status are in 196 * the upper 16 bits. The output is a channel number from 0-7. 197 */ 198 index = ((bit - 1) / 2) & 7; 199 if (mask & AWIN_DMA_IRQ_NDMA) { 200 if (sc->sc_ndma_channels[index].ch_callback == NULL) 201 continue; 202 sc->sc_ndma_channels[index].ch_callback( 203 sc->sc_ndma_channels[index].ch_callbackarg); 204 } else { 205 if (sc->sc_ddma_channels[index].ch_callback == NULL) 206 continue; 207 sc->sc_ddma_channels[index].ch_callback( 208 sc->sc_ddma_channels[index].ch_callbackarg); 209 } 210 } 211 } 212 213 static uint32_t 214 a10dmac_read_ctl(struct a10dmac_channel *ch) 215 { 216 if (ch->ch_type == CH_NDMA) { 217 return (DMACH_READ(ch, AWIN_NDMA_CTL_REG)); 218 } else { 219 return (DMACH_READ(ch, AWIN_DDMA_CTL_REG)); 220 } 221 } 222 223 static void 224 a10dmac_write_ctl(struct a10dmac_channel *ch, uint32_t val) 225 { 226 if (ch->ch_type == CH_NDMA) { 227 DMACH_WRITE(ch, AWIN_NDMA_CTL_REG, val); 228 } else { 229 DMACH_WRITE(ch, AWIN_DDMA_CTL_REG, val); 230 } 231 } 232 233 static int 234 a10dmac_set_config(device_t dev, void *priv, const struct sunxi_dma_config *cfg) 235 { 236 struct a10dmac_channel *ch = priv; 237 uint32_t val; 238 unsigned int dst_dw, dst_bl, dst_bs, dst_wc, dst_am; 239 unsigned int src_dw, src_bl, src_bs, src_wc, src_am; 240 241 switch (cfg->dst_width) { 242 case 8: 243 dst_dw = AWIN_DMA_CTL_DATA_WIDTH_8; 244 break; 245 case 16: 246 dst_dw = AWIN_DMA_CTL_DATA_WIDTH_16; 247 break; 248 case 32: 249 dst_dw = AWIN_DMA_CTL_DATA_WIDTH_32; 250 break; 251 default: 252 return (EINVAL); 253 } 254 switch (cfg->dst_burst_len) { 255 case 1: 256 dst_bl = AWIN_DMA_CTL_BURST_LEN_1; 257 break; 258 case 4: 259 dst_bl = AWIN_DMA_CTL_BURST_LEN_4; 260 break; 261 case 8: 262 dst_bl = AWIN_DMA_CTL_BURST_LEN_8; 263 break; 264 default: 265 return (EINVAL); 266 } 267 switch (cfg->src_width) { 268 case 8: 269 src_dw = AWIN_DMA_CTL_DATA_WIDTH_8; 270 break; 271 case 16: 272 src_dw = AWIN_DMA_CTL_DATA_WIDTH_16; 273 break; 274 case 32: 275 src_dw = AWIN_DMA_CTL_DATA_WIDTH_32; 276 break; 277 default: 278 return (EINVAL); 279 } 280 switch (cfg->src_burst_len) { 281 case 1: 282 src_bl = AWIN_DMA_CTL_BURST_LEN_1; 283 break; 284 case 4: 285 src_bl = AWIN_DMA_CTL_BURST_LEN_4; 286 break; 287 case 8: 288 src_bl = AWIN_DMA_CTL_BURST_LEN_8; 289 break; 290 default: 291 return (EINVAL); 292 } 293 294 val = (dst_dw << AWIN_DMA_CTL_DST_DATA_WIDTH_SHIFT) | 295 (dst_bl << AWIN_DMA_CTL_DST_BURST_LEN_SHIFT) | 296 (cfg->dst_drqtype << AWIN_DMA_CTL_DST_DRQ_TYPE_SHIFT) | 297 (src_dw << AWIN_DMA_CTL_SRC_DATA_WIDTH_SHIFT) | 298 (src_bl << AWIN_DMA_CTL_SRC_BURST_LEN_SHIFT) | 299 (cfg->src_drqtype << AWIN_DMA_CTL_SRC_DRQ_TYPE_SHIFT); 300 301 if (ch->ch_type == CH_NDMA) { 302 if (cfg->dst_noincr) 303 val |= AWIN_NDMA_CTL_DST_ADDR_NOINCR; 304 if (cfg->src_noincr) 305 val |= AWIN_NDMA_CTL_SRC_ADDR_NOINCR; 306 307 DMACH_WRITE(ch, AWIN_NDMA_CTL_REG, val); 308 } else { 309 dst_am = cfg->dst_noincr ? AWIN_DDMA_CTL_DMA_ADDR_IO : 310 AWIN_DDMA_CTL_DMA_ADDR_LINEAR; 311 src_am = cfg->src_noincr ? AWIN_DDMA_CTL_DMA_ADDR_IO : 312 AWIN_DDMA_CTL_DMA_ADDR_LINEAR; 313 314 val |= (dst_am << AWIN_DDMA_CTL_DST_ADDR_MODE_SHIFT); 315 val |= (src_am << AWIN_DDMA_CTL_SRC_ADDR_MODE_SHIFT); 316 317 DMACH_WRITE(ch, AWIN_DDMA_CTL_REG, val); 318 319 dst_bs = cfg->dst_blksize - 1; 320 dst_wc = cfg->dst_wait_cyc - 1; 321 src_bs = cfg->src_blksize - 1; 322 src_wc = cfg->src_wait_cyc - 1; 323 324 DMACH_WRITE(ch, AWIN_DDMA_PARA_REG, 325 (dst_bs << AWIN_DDMA_PARA_DST_DATA_BLK_SIZ_SHIFT) | 326 (dst_wc << AWIN_DDMA_PARA_DST_WAIT_CYC_SHIFT) | 327 (src_bs << AWIN_DDMA_PARA_SRC_DATA_BLK_SIZ_SHIFT) | 328 (src_wc << AWIN_DDMA_PARA_SRC_WAIT_CYC_SHIFT)); 329 } 330 331 return (0); 332 } 333 334 static void * 335 a10dmac_alloc(device_t dev, bool dedicated, void (*cb)(void *), void *cbarg) 336 { 337 struct a10dmac_softc *sc = device_get_softc(dev); 338 struct a10dmac_channel *ch_list; 339 struct a10dmac_channel *ch = NULL; 340 uint32_t irqen; 341 uint8_t ch_count, index; 342 343 if (dedicated) { 344 ch_list = sc->sc_ddma_channels; 345 ch_count = DDMA_CHANNELS; 346 } else { 347 ch_list = sc->sc_ndma_channels; 348 ch_count = NDMA_CHANNELS; 349 } 350 351 mtx_lock_spin(&sc->sc_mtx); 352 for (index = 0; index < ch_count; index++) { 353 if (ch_list[index].ch_callback == NULL) { 354 ch = &ch_list[index]; 355 ch->ch_callback = cb; 356 ch->ch_callbackarg = cbarg; 357 358 irqen = DMA_READ(sc, AWIN_DMA_IRQ_EN_REG); 359 if (ch->ch_type == CH_NDMA) 360 irqen |= AWIN_DMA_IRQ_NDMA_END(index); 361 else 362 irqen |= AWIN_DMA_IRQ_DDMA_END(index); 363 DMA_WRITE(sc, AWIN_DMA_IRQ_EN_REG, irqen); 364 365 break; 366 } 367 } 368 mtx_unlock_spin(&sc->sc_mtx); 369 370 return (ch); 371 } 372 373 static void 374 a10dmac_free(device_t dev, void *priv) 375 { 376 struct a10dmac_channel *ch = priv; 377 struct a10dmac_softc *sc = ch->ch_sc; 378 uint32_t irqen, sta, cfg; 379 380 mtx_lock_spin(&sc->sc_mtx); 381 382 irqen = DMA_READ(sc, AWIN_DMA_IRQ_EN_REG); 383 cfg = a10dmac_read_ctl(ch); 384 if (ch->ch_type == CH_NDMA) { 385 sta = AWIN_DMA_IRQ_NDMA_END(ch->ch_index); 386 cfg &= ~AWIN_NDMA_CTL_DMA_LOADING; 387 } else { 388 sta = AWIN_DMA_IRQ_DDMA_END(ch->ch_index); 389 cfg &= ~AWIN_DDMA_CTL_DMA_LOADING; 390 } 391 irqen &= ~sta; 392 a10dmac_write_ctl(ch, cfg); 393 DMA_WRITE(sc, AWIN_DMA_IRQ_EN_REG, irqen); 394 DMA_WRITE(sc, AWIN_DMA_IRQ_PEND_STA_REG, sta); 395 396 ch->ch_callback = NULL; 397 ch->ch_callbackarg = NULL; 398 399 mtx_unlock_spin(&sc->sc_mtx); 400 } 401 402 static int 403 a10dmac_transfer(device_t dev, void *priv, bus_addr_t src, bus_addr_t dst, 404 size_t nbytes) 405 { 406 struct a10dmac_channel *ch = priv; 407 uint32_t cfg; 408 409 cfg = a10dmac_read_ctl(ch); 410 if (ch->ch_type == CH_NDMA) { 411 if (cfg & AWIN_NDMA_CTL_DMA_LOADING) 412 return (EBUSY); 413 414 DMACH_WRITE(ch, AWIN_NDMA_SRC_ADDR_REG, src); 415 DMACH_WRITE(ch, AWIN_NDMA_DEST_ADDR_REG, dst); 416 DMACH_WRITE(ch, AWIN_NDMA_BC_REG, nbytes); 417 418 cfg |= AWIN_NDMA_CTL_DMA_LOADING; 419 a10dmac_write_ctl(ch, cfg); 420 } else { 421 if (cfg & AWIN_DDMA_CTL_DMA_LOADING) 422 return (EBUSY); 423 424 DMACH_WRITE(ch, AWIN_DDMA_SRC_START_ADDR_REG, src); 425 DMACH_WRITE(ch, AWIN_DDMA_DEST_START_ADDR_REG, dst); 426 DMACH_WRITE(ch, AWIN_DDMA_BC_REG, nbytes); 427 428 cfg |= AWIN_DDMA_CTL_DMA_LOADING; 429 a10dmac_write_ctl(ch, cfg); 430 } 431 432 return (0); 433 } 434 435 static void 436 a10dmac_halt(device_t dev, void *priv) 437 { 438 struct a10dmac_channel *ch = priv; 439 uint32_t cfg; 440 441 cfg = a10dmac_read_ctl(ch); 442 if (ch->ch_type == CH_NDMA) { 443 cfg &= ~AWIN_NDMA_CTL_DMA_LOADING; 444 } else { 445 cfg &= ~AWIN_DDMA_CTL_DMA_LOADING; 446 } 447 a10dmac_write_ctl(ch, cfg); 448 } 449 450 static device_method_t a10dmac_methods[] = { 451 /* Device interface */ 452 DEVMETHOD(device_probe, a10dmac_probe), 453 DEVMETHOD(device_attach, a10dmac_attach), 454 455 /* sunxi DMA interface */ 456 DEVMETHOD(sunxi_dma_alloc, a10dmac_alloc), 457 DEVMETHOD(sunxi_dma_free, a10dmac_free), 458 DEVMETHOD(sunxi_dma_set_config, a10dmac_set_config), 459 DEVMETHOD(sunxi_dma_transfer, a10dmac_transfer), 460 DEVMETHOD(sunxi_dma_halt, a10dmac_halt), 461 462 DEVMETHOD_END 463 }; 464 465 static driver_t a10dmac_driver = { 466 "a10dmac", 467 a10dmac_methods, 468 sizeof(struct a10dmac_softc) 469 }; 470 471 DRIVER_MODULE(a10dmac, simplebus, a10dmac_driver, 0, 0); 472