1 /*- 2 * Copyright (c) 2014-2016 Jared D. McNeill <jmcneill@invisible.ca> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * Allwinner A10/A20 and H3 Audio Codec 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/rman.h> 38 #include <sys/condvar.h> 39 #include <sys/kernel.h> 40 #include <sys/module.h> 41 #include <sys/gpio.h> 42 43 #include <machine/bus.h> 44 45 #include <dev/sound/pcm/sound.h> 46 #include <dev/sound/chip.h> 47 48 #include <dev/ofw/ofw_bus.h> 49 #include <dev/ofw/ofw_bus_subr.h> 50 51 #include <dev/gpio/gpiobusvar.h> 52 53 #include <dev/extres/clk/clk.h> 54 #include <dev/extres/hwreset/hwreset.h> 55 56 #include "sunxi_dma_if.h" 57 #include "mixer_if.h" 58 59 struct a10codec_info; 60 61 struct a10codec_config { 62 /* mixer class */ 63 struct kobj_class *mixer_class; 64 65 /* toggle DAC/ADC mute */ 66 void (*mute)(struct a10codec_info *, int, int); 67 68 /* DRQ types */ 69 u_int drqtype_codec; 70 u_int drqtype_sdram; 71 72 /* register map */ 73 bus_size_t DPC, 74 DAC_FIFOC, 75 DAC_FIFOS, 76 DAC_TXDATA, 77 ADC_FIFOC, 78 ADC_FIFOS, 79 ADC_RXDATA, 80 DAC_CNT, 81 ADC_CNT; 82 }; 83 84 #define TX_TRIG_LEVEL 0xf 85 #define RX_TRIG_LEVEL 0x7 86 #define DRQ_CLR_CNT 0x3 87 88 #define AC_DAC_DPC(_sc) ((_sc)->cfg->DPC) 89 #define DAC_DPC_EN_DA 0x80000000 90 #define AC_DAC_FIFOC(_sc) ((_sc)->cfg->DAC_FIFOC) 91 #define DAC_FIFOC_FS_SHIFT 29 92 #define DAC_FIFOC_FS_MASK (7U << DAC_FIFOC_FS_SHIFT) 93 #define DAC_FS_48KHZ 0 94 #define DAC_FS_32KHZ 1 95 #define DAC_FS_24KHZ 2 96 #define DAC_FS_16KHZ 3 97 #define DAC_FS_12KHZ 4 98 #define DAC_FS_8KHZ 5 99 #define DAC_FS_192KHZ 6 100 #define DAC_FS_96KHZ 7 101 #define DAC_FIFOC_FIFO_MODE_SHIFT 24 102 #define DAC_FIFOC_FIFO_MODE_MASK (3U << DAC_FIFOC_FIFO_MODE_SHIFT) 103 #define FIFO_MODE_24_31_8 0 104 #define FIFO_MODE_16_31_16 0 105 #define FIFO_MODE_16_15_0 1 106 #define DAC_FIFOC_DRQ_CLR_CNT_SHIFT 21 107 #define DAC_FIFOC_DRQ_CLR_CNT_MASK (3U << DAC_FIFOC_DRQ_CLR_CNT_SHIFT) 108 #define DAC_FIFOC_TX_TRIG_LEVEL_SHIFT 8 109 #define DAC_FIFOC_TX_TRIG_LEVEL_MASK (0x7f << DAC_FIFOC_TX_TRIG_LEVEL_SHIFT) 110 #define DAC_FIFOC_MONO_EN (1U << 6) 111 #define DAC_FIFOC_TX_BITS (1U << 5) 112 #define DAC_FIFOC_DRQ_EN (1U << 4) 113 #define DAC_FIFOC_FIFO_FLUSH (1U << 0) 114 #define AC_DAC_FIFOS(_sc) ((_sc)->cfg->DAC_FIFOS) 115 #define AC_DAC_TXDATA(_sc) ((_sc)->cfg->DAC_TXDATA) 116 #define AC_ADC_FIFOC(_sc) ((_sc)->cfg->ADC_FIFOC) 117 #define ADC_FIFOC_FS_SHIFT 29 118 #define ADC_FIFOC_FS_MASK (7U << ADC_FIFOC_FS_SHIFT) 119 #define ADC_FS_48KHZ 0 120 #define ADC_FIFOC_EN_AD (1U << 28) 121 #define ADC_FIFOC_RX_FIFO_MODE (1U << 24) 122 #define ADC_FIFOC_RX_TRIG_LEVEL_SHIFT 8 123 #define ADC_FIFOC_RX_TRIG_LEVEL_MASK (0x1f << ADC_FIFOC_RX_TRIG_LEVEL_SHIFT) 124 #define ADC_FIFOC_MONO_EN (1U << 7) 125 #define ADC_FIFOC_RX_BITS (1U << 6) 126 #define ADC_FIFOC_DRQ_EN (1U << 4) 127 #define ADC_FIFOC_FIFO_FLUSH (1U << 1) 128 #define AC_ADC_FIFOS(_sc) ((_sc)->cfg->ADC_FIFOS) 129 #define AC_ADC_RXDATA(_sc) ((_sc)->cfg->ADC_RXDATA) 130 #define AC_DAC_CNT(_sc) ((_sc)->cfg->DAC_CNT) 131 #define AC_ADC_CNT(_sc) ((_sc)->cfg->ADC_CNT) 132 133 static uint32_t a10codec_fmt[] = { 134 SND_FORMAT(AFMT_S16_LE, 1, 0), 135 SND_FORMAT(AFMT_S16_LE, 2, 0), 136 0 137 }; 138 139 static struct pcmchan_caps a10codec_pcaps = { 8000, 192000, a10codec_fmt, 0 }; 140 static struct pcmchan_caps a10codec_rcaps = { 8000, 48000, a10codec_fmt, 0 }; 141 142 struct a10codec_info; 143 144 struct a10codec_chinfo { 145 struct snd_dbuf *buffer; 146 struct pcm_channel *channel; 147 struct a10codec_info *parent; 148 bus_dmamap_t dmamap; 149 void *dmaaddr; 150 bus_addr_t physaddr; 151 bus_size_t fifo; 152 device_t dmac; 153 void *dmachan; 154 155 int dir; 156 int run; 157 uint32_t pos; 158 uint32_t format; 159 uint32_t blocksize; 160 uint32_t speed; 161 }; 162 163 struct a10codec_info { 164 device_t dev; 165 struct resource *res[2]; 166 struct mtx *lock; 167 bus_dma_tag_t dmat; 168 unsigned dmasize; 169 void *ih; 170 171 struct a10codec_config *cfg; 172 173 struct a10codec_chinfo play; 174 struct a10codec_chinfo rec; 175 }; 176 177 static struct resource_spec a10codec_spec[] = { 178 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 179 { -1, 0 } 180 }; 181 182 #define CODEC_ANALOG_READ(sc, reg) bus_read_4((sc)->res[1], (reg)) 183 #define CODEC_ANALOG_WRITE(sc, reg, val) bus_write_4((sc)->res[1], (reg), (val)) 184 185 #define CODEC_READ(sc, reg) bus_read_4((sc)->res[0], (reg)) 186 #define CODEC_WRITE(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val)) 187 188 /* 189 * A10/A20 mixer interface 190 */ 191 192 #define A10_DAC_ACTL 0x10 193 #define A10_DACAREN (1U << 31) 194 #define A10_DACALEN (1U << 30) 195 #define A10_MIXEN (1U << 29) 196 #define A10_DACPAS (1U << 8) 197 #define A10_PAMUTE (1U << 6) 198 #define A10_PAVOL_SHIFT 0 199 #define A10_PAVOL_MASK (0x3f << A10_PAVOL_SHIFT) 200 #define A10_ADC_ACTL 0x28 201 #define A10_ADCREN (1U << 31) 202 #define A10_ADCLEN (1U << 30) 203 #define A10_PREG1EN (1U << 29) 204 #define A10_PREG2EN (1U << 28) 205 #define A10_VMICEN (1U << 27) 206 #define A10_ADCG_SHIFT 20 207 #define A10_ADCG_MASK (7U << A10_ADCG_SHIFT) 208 #define A10_ADCIS_SHIFT 17 209 #define A10_ADCIS_MASK (7U << A10_ADCIS_SHIFT) 210 #define A10_ADC_IS_LINEIN 0 211 #define A10_ADC_IS_FMIN 1 212 #define A10_ADC_IS_MIC1 2 213 #define A10_ADC_IS_MIC2 3 214 #define A10_ADC_IS_MIC1_L_MIC2_R 4 215 #define A10_ADC_IS_MIC1_LR_MIC2_LR 5 216 #define A10_ADC_IS_OMIX 6 217 #define A10_ADC_IS_LINEIN_L_MIC1_R 7 218 #define A10_LNRDF (1U << 16) 219 #define A10_LNPREG_SHIFT 13 220 #define A10_LNPREG_MASK (7U << A10_LNPREG_SHIFT) 221 #define A10_PA_EN (1U << 4) 222 #define A10_DDE (1U << 3) 223 224 static int 225 a10_mixer_init(struct snd_mixer *m) 226 { 227 struct a10codec_info *sc = mix_getdevinfo(m); 228 uint32_t val; 229 230 mix_setdevs(m, SOUND_MASK_VOLUME | SOUND_MASK_LINE | SOUND_MASK_RECLEV); 231 mix_setrecdevs(m, SOUND_MASK_LINE | SOUND_MASK_LINE1 | SOUND_MASK_MIC); 232 233 /* Unmute input source to PA */ 234 val = CODEC_READ(sc, A10_DAC_ACTL); 235 val |= A10_PAMUTE; 236 CODEC_WRITE(sc, A10_DAC_ACTL, val); 237 238 /* Enable PA */ 239 val = CODEC_READ(sc, A10_ADC_ACTL); 240 val |= A10_PA_EN; 241 CODEC_WRITE(sc, A10_ADC_ACTL, val); 242 243 return (0); 244 } 245 246 static const struct a10_mixer { 247 unsigned reg; 248 unsigned mask; 249 unsigned shift; 250 } a10_mixers[SOUND_MIXER_NRDEVICES] = { 251 [SOUND_MIXER_VOLUME] = { A10_DAC_ACTL, A10_PAVOL_MASK, 252 A10_PAVOL_SHIFT }, 253 [SOUND_MIXER_LINE] = { A10_ADC_ACTL, A10_LNPREG_MASK, 254 A10_LNPREG_SHIFT }, 255 [SOUND_MIXER_RECLEV] = { A10_ADC_ACTL, A10_ADCG_MASK, 256 A10_ADCG_SHIFT }, 257 }; 258 259 static int 260 a10_mixer_set(struct snd_mixer *m, unsigned dev, unsigned left, 261 unsigned right) 262 { 263 struct a10codec_info *sc = mix_getdevinfo(m); 264 uint32_t val; 265 unsigned nvol, max; 266 267 max = a10_mixers[dev].mask >> a10_mixers[dev].shift; 268 nvol = (left * max) / 100; 269 270 val = CODEC_READ(sc, a10_mixers[dev].reg); 271 val &= ~a10_mixers[dev].mask; 272 val |= (nvol << a10_mixers[dev].shift); 273 CODEC_WRITE(sc, a10_mixers[dev].reg, val); 274 275 left = right = (left * 100) / max; 276 return (left | (right << 8)); 277 } 278 279 static uint32_t 280 a10_mixer_setrecsrc(struct snd_mixer *m, uint32_t src) 281 { 282 struct a10codec_info *sc = mix_getdevinfo(m); 283 uint32_t val; 284 285 val = CODEC_READ(sc, A10_ADC_ACTL); 286 287 switch (src) { 288 case SOUND_MASK_LINE: /* line-in */ 289 val &= ~A10_ADCIS_MASK; 290 val |= (A10_ADC_IS_LINEIN << A10_ADCIS_SHIFT); 291 break; 292 case SOUND_MASK_MIC: /* MIC1 */ 293 val &= ~A10_ADCIS_MASK; 294 val |= (A10_ADC_IS_MIC1 << A10_ADCIS_SHIFT); 295 break; 296 case SOUND_MASK_LINE1: /* MIC2 */ 297 val &= ~A10_ADCIS_MASK; 298 val |= (A10_ADC_IS_MIC2 << A10_ADCIS_SHIFT); 299 break; 300 default: 301 break; 302 } 303 304 CODEC_WRITE(sc, A10_ADC_ACTL, val); 305 306 switch ((val & A10_ADCIS_MASK) >> A10_ADCIS_SHIFT) { 307 case A10_ADC_IS_LINEIN: 308 return (SOUND_MASK_LINE); 309 case A10_ADC_IS_MIC1: 310 return (SOUND_MASK_MIC); 311 case A10_ADC_IS_MIC2: 312 return (SOUND_MASK_LINE1); 313 default: 314 return (0); 315 } 316 } 317 318 static void 319 a10_mute(struct a10codec_info *sc, int mute, int dir) 320 { 321 uint32_t val; 322 323 if (dir == PCMDIR_PLAY) { 324 val = CODEC_READ(sc, A10_DAC_ACTL); 325 if (mute) { 326 /* Disable DAC analog l/r channels and output mixer */ 327 val &= ~A10_DACAREN; 328 val &= ~A10_DACALEN; 329 val &= ~A10_DACPAS; 330 } else { 331 /* Enable DAC analog l/r channels and output mixer */ 332 val |= A10_DACAREN; 333 val |= A10_DACALEN; 334 val |= A10_DACPAS; 335 } 336 CODEC_WRITE(sc, A10_DAC_ACTL, val); 337 } else { 338 val = CODEC_READ(sc, A10_ADC_ACTL); 339 if (mute) { 340 /* Disable ADC analog l/r channels, MIC1 preamp, 341 * and VMIC pin voltage 342 */ 343 val &= ~A10_ADCREN; 344 val &= ~A10_ADCLEN; 345 val &= ~A10_PREG1EN; 346 val &= ~A10_VMICEN; 347 } else { 348 /* Enable ADC analog l/r channels, MIC1 preamp, 349 * and VMIC pin voltage 350 */ 351 val |= A10_ADCREN; 352 val |= A10_ADCLEN; 353 val |= A10_PREG1EN; 354 val |= A10_VMICEN; 355 } 356 CODEC_WRITE(sc, A10_ADC_ACTL, val); 357 } 358 } 359 360 static kobj_method_t a10_mixer_methods[] = { 361 KOBJMETHOD(mixer_init, a10_mixer_init), 362 KOBJMETHOD(mixer_set, a10_mixer_set), 363 KOBJMETHOD(mixer_setrecsrc, a10_mixer_setrecsrc), 364 KOBJMETHOD_END 365 }; 366 MIXER_DECLARE(a10_mixer); 367 368 /* 369 * H3 mixer interface 370 */ 371 372 #define H3_PR_CFG 0x00 373 #define H3_AC_PR_RST (1 << 28) 374 #define H3_AC_PR_RW (1 << 24) 375 #define H3_AC_PR_ADDR_SHIFT 16 376 #define H3_AC_PR_ADDR_MASK (0x1f << H3_AC_PR_ADDR_SHIFT) 377 #define H3_ACDA_PR_WDAT_SHIFT 8 378 #define H3_ACDA_PR_WDAT_MASK (0xff << H3_ACDA_PR_WDAT_SHIFT) 379 #define H3_ACDA_PR_RDAT_SHIFT 0 380 #define H3_ACDA_PR_RDAT_MASK (0xff << H3_ACDA_PR_RDAT_SHIFT) 381 382 #define H3_LOMIXSC 0x01 383 #define H3_LOMIXSC_LDAC (1 << 1) 384 #define H3_ROMIXSC 0x02 385 #define H3_ROMIXSC_RDAC (1 << 1) 386 #define H3_DAC_PA_SRC 0x03 387 #define H3_DACAREN (1 << 7) 388 #define H3_DACALEN (1 << 6) 389 #define H3_RMIXEN (1 << 5) 390 #define H3_LMIXEN (1 << 4) 391 #define H3_LINEIN_GCTR 0x05 392 #define H3_LINEING_SHIFT 4 393 #define H3_LINEING_MASK (0x7 << H3_LINEING_SHIFT) 394 #define H3_MIC_GCTR 0x06 395 #define H3_MIC1_GAIN_SHIFT 4 396 #define H3_MIC1_GAIN_MASK (0x7 << H3_MIC1_GAIN_SHIFT) 397 #define H3_MIC2_GAIN_SHIFT 0 398 #define H3_MIC2_GAIN_MASK (0x7 << H3_MIC2_GAIN_SHIFT) 399 #define H3_PAEN_CTR 0x07 400 #define H3_LINEOUTEN (1 << 7) 401 #define H3_LINEOUT_VOLC 0x09 402 #define H3_LINEOUTVOL_SHIFT 3 403 #define H3_LINEOUTVOL_MASK (0x1f << H3_LINEOUTVOL_SHIFT) 404 #define H3_MIC2G_LINEOUT_CTR 0x0a 405 #define H3_LINEOUT_LSEL (1 << 3) 406 #define H3_LINEOUT_RSEL (1 << 2) 407 #define H3_LADCMIXSC 0x0c 408 #define H3_RADCMIXSC 0x0d 409 #define H3_ADCMIXSC_MIC1 (1 << 6) 410 #define H3_ADCMIXSC_MIC2 (1 << 5) 411 #define H3_ADCMIXSC_LINEIN (1 << 2) 412 #define H3_ADCMIXSC_OMIXER (3 << 0) 413 #define H3_ADC_AP_EN 0x0f 414 #define H3_ADCREN (1 << 7) 415 #define H3_ADCLEN (1 << 6) 416 #define H3_ADCG_SHIFT 0 417 #define H3_ADCG_MASK (0x7 << H3_ADCG_SHIFT) 418 419 static u_int 420 h3_pr_read(struct a10codec_info *sc, u_int addr) 421 { 422 uint32_t val; 423 424 /* Read current value */ 425 val = CODEC_ANALOG_READ(sc, H3_PR_CFG); 426 427 /* De-assert reset */ 428 val |= H3_AC_PR_RST; 429 CODEC_ANALOG_WRITE(sc, H3_PR_CFG, val); 430 431 /* Read mode */ 432 val &= ~H3_AC_PR_RW; 433 CODEC_ANALOG_WRITE(sc, H3_PR_CFG, val); 434 435 /* Set address */ 436 val &= ~H3_AC_PR_ADDR_MASK; 437 val |= (addr << H3_AC_PR_ADDR_SHIFT); 438 CODEC_ANALOG_WRITE(sc, H3_PR_CFG, val); 439 440 /* Read data */ 441 return (CODEC_ANALOG_READ(sc , H3_PR_CFG) & H3_ACDA_PR_RDAT_MASK); 442 } 443 444 static void 445 h3_pr_write(struct a10codec_info *sc, u_int addr, u_int data) 446 { 447 uint32_t val; 448 449 /* Read current value */ 450 val = CODEC_ANALOG_READ(sc, H3_PR_CFG); 451 452 /* De-assert reset */ 453 val |= H3_AC_PR_RST; 454 CODEC_ANALOG_WRITE(sc, H3_PR_CFG, val); 455 456 /* Set address */ 457 val &= ~H3_AC_PR_ADDR_MASK; 458 val |= (addr << H3_AC_PR_ADDR_SHIFT); 459 CODEC_ANALOG_WRITE(sc, H3_PR_CFG, val); 460 461 /* Write data */ 462 val &= ~H3_ACDA_PR_WDAT_MASK; 463 val |= (data << H3_ACDA_PR_WDAT_SHIFT); 464 CODEC_ANALOG_WRITE(sc, H3_PR_CFG, val); 465 466 /* Write mode */ 467 val |= H3_AC_PR_RW; 468 CODEC_ANALOG_WRITE(sc, H3_PR_CFG, val); 469 } 470 471 static void 472 h3_pr_set_clear(struct a10codec_info *sc, u_int addr, u_int set, u_int clr) 473 { 474 u_int old, new; 475 476 old = h3_pr_read(sc, addr); 477 new = set | (old & ~clr); 478 h3_pr_write(sc, addr, new); 479 } 480 481 static int 482 h3_mixer_init(struct snd_mixer *m) 483 { 484 int rid=1; 485 pcell_t reg[2]; 486 phandle_t analogref; 487 struct a10codec_info *sc = mix_getdevinfo(m); 488 489 if (OF_getencprop(ofw_bus_get_node(sc->dev), "allwinner,codec-analog-controls", 490 &analogref, sizeof(analogref)) <= 0) { 491 return (ENXIO); 492 } 493 494 if (OF_getencprop(OF_node_from_xref(analogref), "reg", 495 reg, sizeof(reg)) <= 0) { 496 return (ENXIO); 497 } 498 499 sc->res[1] = bus_alloc_resource(sc->dev, SYS_RES_MEMORY, &rid, reg[0], 500 reg[0]+reg[1], reg[1], RF_ACTIVE ); 501 502 if (sc->res[1] == NULL) { 503 return (ENXIO); 504 } 505 506 mix_setdevs(m, SOUND_MASK_PCM | SOUND_MASK_VOLUME | SOUND_MASK_RECLEV | 507 SOUND_MASK_MIC | SOUND_MASK_LINE | SOUND_MASK_LINE1); 508 mix_setrecdevs(m, SOUND_MASK_MIC | SOUND_MASK_LINE | SOUND_MASK_LINE1 | 509 SOUND_MASK_IMIX); 510 511 pcm_setflags(sc->dev, pcm_getflags(sc->dev) | SD_F_SOFTPCMVOL); 512 513 /* Right & Left LINEOUT enable */ 514 h3_pr_set_clear(sc, H3_PAEN_CTR, H3_LINEOUTEN, 0); 515 h3_pr_set_clear(sc, H3_MIC2G_LINEOUT_CTR, 516 H3_LINEOUT_LSEL | H3_LINEOUT_RSEL, 0); 517 518 return (0); 519 } 520 521 static const struct h3_mixer { 522 unsigned reg; 523 unsigned mask; 524 unsigned shift; 525 } h3_mixers[SOUND_MIXER_NRDEVICES] = { 526 [SOUND_MIXER_VOLUME] = { H3_LINEOUT_VOLC, H3_LINEOUTVOL_MASK, 527 H3_LINEOUTVOL_SHIFT }, 528 [SOUND_MIXER_RECLEV] = { H3_ADC_AP_EN, H3_ADCG_MASK, 529 H3_ADCG_SHIFT }, 530 [SOUND_MIXER_LINE] = { H3_LINEIN_GCTR, H3_LINEING_MASK, 531 H3_LINEING_SHIFT }, 532 [SOUND_MIXER_MIC] = { H3_MIC_GCTR, H3_MIC1_GAIN_MASK, 533 H3_MIC1_GAIN_SHIFT }, 534 [SOUND_MIXER_LINE1] = { H3_MIC_GCTR, H3_MIC2_GAIN_MASK, 535 H3_MIC2_GAIN_SHIFT }, 536 }; 537 538 static int 539 h3_mixer_set(struct snd_mixer *m, unsigned dev, unsigned left, 540 unsigned right) 541 { 542 struct a10codec_info *sc = mix_getdevinfo(m); 543 unsigned nvol, max; 544 545 max = h3_mixers[dev].mask >> h3_mixers[dev].shift; 546 nvol = (left * max) / 100; 547 548 h3_pr_set_clear(sc, h3_mixers[dev].reg, 549 nvol << h3_mixers[dev].shift, h3_mixers[dev].mask); 550 551 left = right = (left * 100) / max; 552 return (left | (right << 8)); 553 } 554 555 static uint32_t 556 h3_mixer_setrecsrc(struct snd_mixer *m, uint32_t src) 557 { 558 struct a10codec_info *sc = mix_getdevinfo(m); 559 uint32_t val; 560 561 val = 0; 562 src &= (SOUND_MASK_LINE | SOUND_MASK_MIC | 563 SOUND_MASK_LINE1 | SOUND_MASK_IMIX); 564 565 if ((src & SOUND_MASK_LINE) != 0) /* line-in */ 566 val |= H3_ADCMIXSC_LINEIN; 567 if ((src & SOUND_MASK_MIC) != 0) /* MIC1 */ 568 val |= H3_ADCMIXSC_MIC1; 569 if ((src & SOUND_MASK_LINE1) != 0) /* MIC2 */ 570 val |= H3_ADCMIXSC_MIC2; 571 if ((src & SOUND_MASK_IMIX) != 0) /* l/r output mixer */ 572 val |= H3_ADCMIXSC_OMIXER; 573 574 h3_pr_write(sc, H3_LADCMIXSC, val); 575 h3_pr_write(sc, H3_RADCMIXSC, val); 576 577 return (src); 578 } 579 580 static void 581 h3_mute(struct a10codec_info *sc, int mute, int dir) 582 { 583 if (dir == PCMDIR_PLAY) { 584 if (mute) { 585 /* Mute DAC l/r channels to output mixer */ 586 h3_pr_set_clear(sc, H3_LOMIXSC, 0, H3_LOMIXSC_LDAC); 587 h3_pr_set_clear(sc, H3_ROMIXSC, 0, H3_ROMIXSC_RDAC); 588 /* Disable DAC analog l/r channels and output mixer */ 589 h3_pr_set_clear(sc, H3_DAC_PA_SRC, 590 0, H3_DACAREN | H3_DACALEN | H3_RMIXEN | H3_LMIXEN); 591 } else { 592 /* Enable DAC analog l/r channels and output mixer */ 593 h3_pr_set_clear(sc, H3_DAC_PA_SRC, 594 H3_DACAREN | H3_DACALEN | H3_RMIXEN | H3_LMIXEN, 0); 595 /* Unmute DAC l/r channels to output mixer */ 596 h3_pr_set_clear(sc, H3_LOMIXSC, H3_LOMIXSC_LDAC, 0); 597 h3_pr_set_clear(sc, H3_ROMIXSC, H3_ROMIXSC_RDAC, 0); 598 } 599 } else { 600 if (mute) { 601 /* Disable ADC analog l/r channels */ 602 h3_pr_set_clear(sc, H3_ADC_AP_EN, 603 0, H3_ADCREN | H3_ADCLEN); 604 } else { 605 /* Enable ADC analog l/r channels */ 606 h3_pr_set_clear(sc, H3_ADC_AP_EN, 607 H3_ADCREN | H3_ADCLEN, 0); 608 } 609 } 610 } 611 612 static kobj_method_t h3_mixer_methods[] = { 613 KOBJMETHOD(mixer_init, h3_mixer_init), 614 KOBJMETHOD(mixer_set, h3_mixer_set), 615 KOBJMETHOD(mixer_setrecsrc, h3_mixer_setrecsrc), 616 KOBJMETHOD_END 617 }; 618 MIXER_DECLARE(h3_mixer); 619 620 /* 621 * Channel interface 622 */ 623 624 static void 625 a10codec_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 626 { 627 struct a10codec_chinfo *ch = arg; 628 629 if (error != 0) 630 return; 631 632 ch->physaddr = segs[0].ds_addr; 633 } 634 635 static void 636 a10codec_transfer(struct a10codec_chinfo *ch) 637 { 638 bus_addr_t src, dst; 639 int error; 640 641 if (ch->dir == PCMDIR_PLAY) { 642 src = ch->physaddr + ch->pos; 643 dst = ch->fifo; 644 } else { 645 src = ch->fifo; 646 dst = ch->physaddr + ch->pos; 647 } 648 649 error = SUNXI_DMA_TRANSFER(ch->dmac, ch->dmachan, src, dst, 650 ch->blocksize); 651 if (error) { 652 ch->run = 0; 653 device_printf(ch->parent->dev, "DMA transfer failed: %d\n", 654 error); 655 } 656 } 657 658 static void 659 a10codec_dmaconfig(struct a10codec_chinfo *ch) 660 { 661 struct a10codec_info *sc = ch->parent; 662 struct sunxi_dma_config conf; 663 664 memset(&conf, 0, sizeof(conf)); 665 conf.src_width = conf.dst_width = 16; 666 conf.src_burst_len = conf.dst_burst_len = 4; 667 668 if (ch->dir == PCMDIR_PLAY) { 669 conf.dst_noincr = true; 670 conf.src_drqtype = sc->cfg->drqtype_sdram; 671 conf.dst_drqtype = sc->cfg->drqtype_codec; 672 } else { 673 conf.src_noincr = true; 674 conf.src_drqtype = sc->cfg->drqtype_codec; 675 conf.dst_drqtype = sc->cfg->drqtype_sdram; 676 } 677 678 SUNXI_DMA_SET_CONFIG(ch->dmac, ch->dmachan, &conf); 679 } 680 681 static void 682 a10codec_dmaintr(void *priv) 683 { 684 struct a10codec_chinfo *ch = priv; 685 unsigned bufsize; 686 687 bufsize = sndbuf_getsize(ch->buffer); 688 689 ch->pos += ch->blocksize; 690 if (ch->pos >= bufsize) 691 ch->pos -= bufsize; 692 693 if (ch->run) { 694 chn_intr(ch->channel); 695 a10codec_transfer(ch); 696 } 697 } 698 699 static unsigned 700 a10codec_fs(struct a10codec_chinfo *ch) 701 { 702 switch (ch->speed) { 703 case 48000: 704 return (DAC_FS_48KHZ); 705 case 24000: 706 return (DAC_FS_24KHZ); 707 case 12000: 708 return (DAC_FS_12KHZ); 709 case 192000: 710 return (DAC_FS_192KHZ); 711 case 32000: 712 return (DAC_FS_32KHZ); 713 case 16000: 714 return (DAC_FS_16KHZ); 715 case 8000: 716 return (DAC_FS_8KHZ); 717 case 96000: 718 return (DAC_FS_96KHZ); 719 default: 720 return (DAC_FS_48KHZ); 721 } 722 } 723 724 static void 725 a10codec_start(struct a10codec_chinfo *ch) 726 { 727 struct a10codec_info *sc = ch->parent; 728 uint32_t val; 729 730 ch->pos = 0; 731 732 if (ch->dir == PCMDIR_PLAY) { 733 /* Flush DAC FIFO */ 734 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), DAC_FIFOC_FIFO_FLUSH); 735 736 /* Clear DAC FIFO status */ 737 CODEC_WRITE(sc, AC_DAC_FIFOS(sc), 738 CODEC_READ(sc, AC_DAC_FIFOS(sc))); 739 740 /* Unmute output */ 741 sc->cfg->mute(sc, 0, ch->dir); 742 743 /* Configure DAC DMA channel */ 744 a10codec_dmaconfig(ch); 745 746 /* Configure DAC FIFO */ 747 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), 748 (AFMT_CHANNEL(ch->format) == 1 ? DAC_FIFOC_MONO_EN : 0) | 749 (a10codec_fs(ch) << DAC_FIFOC_FS_SHIFT) | 750 (FIFO_MODE_16_15_0 << DAC_FIFOC_FIFO_MODE_SHIFT) | 751 (DRQ_CLR_CNT << DAC_FIFOC_DRQ_CLR_CNT_SHIFT) | 752 (TX_TRIG_LEVEL << DAC_FIFOC_TX_TRIG_LEVEL_SHIFT)); 753 754 /* Enable DAC DRQ */ 755 val = CODEC_READ(sc, AC_DAC_FIFOC(sc)); 756 val |= DAC_FIFOC_DRQ_EN; 757 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), val); 758 } else { 759 /* Flush ADC FIFO */ 760 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), ADC_FIFOC_FIFO_FLUSH); 761 762 /* Clear ADC FIFO status */ 763 CODEC_WRITE(sc, AC_ADC_FIFOS(sc), 764 CODEC_READ(sc, AC_ADC_FIFOS(sc))); 765 766 /* Unmute input */ 767 sc->cfg->mute(sc, 0, ch->dir); 768 769 /* Configure ADC DMA channel */ 770 a10codec_dmaconfig(ch); 771 772 /* Configure ADC FIFO */ 773 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), 774 ADC_FIFOC_EN_AD | 775 ADC_FIFOC_RX_FIFO_MODE | 776 (AFMT_CHANNEL(ch->format) == 1 ? ADC_FIFOC_MONO_EN : 0) | 777 (a10codec_fs(ch) << ADC_FIFOC_FS_SHIFT) | 778 (RX_TRIG_LEVEL << ADC_FIFOC_RX_TRIG_LEVEL_SHIFT)); 779 780 /* Enable ADC DRQ */ 781 val = CODEC_READ(sc, AC_ADC_FIFOC(sc)); 782 val |= ADC_FIFOC_DRQ_EN; 783 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), val); 784 } 785 786 /* Start DMA transfer */ 787 a10codec_transfer(ch); 788 } 789 790 static void 791 a10codec_stop(struct a10codec_chinfo *ch) 792 { 793 struct a10codec_info *sc = ch->parent; 794 795 /* Disable DMA channel */ 796 SUNXI_DMA_HALT(ch->dmac, ch->dmachan); 797 798 sc->cfg->mute(sc, 1, ch->dir); 799 800 if (ch->dir == PCMDIR_PLAY) { 801 /* Disable DAC DRQ */ 802 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), 0); 803 } else { 804 /* Disable ADC DRQ */ 805 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), 0); 806 } 807 } 808 809 static void * 810 a10codec_chan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, 811 struct pcm_channel *c, int dir) 812 { 813 struct a10codec_info *sc = devinfo; 814 struct a10codec_chinfo *ch = dir == PCMDIR_PLAY ? &sc->play : &sc->rec; 815 phandle_t xref; 816 pcell_t *cells; 817 int ncells, error; 818 819 error = ofw_bus_parse_xref_list_alloc(ofw_bus_get_node(sc->dev), 820 "dmas", "#dma-cells", dir == PCMDIR_PLAY ? 1 : 0, 821 &xref, &ncells, &cells); 822 if (error != 0) { 823 device_printf(sc->dev, "cannot parse 'dmas' property\n"); 824 return (NULL); 825 } 826 OF_prop_free(cells); 827 828 ch->parent = sc; 829 ch->channel = c; 830 ch->buffer = b; 831 ch->dir = dir; 832 ch->fifo = rman_get_start(sc->res[0]) + 833 (dir == PCMDIR_REC ? AC_ADC_RXDATA(sc) : AC_DAC_TXDATA(sc)); 834 835 ch->dmac = OF_device_from_xref(xref); 836 if (ch->dmac == NULL) { 837 device_printf(sc->dev, "cannot find DMA controller\n"); 838 device_printf(sc->dev, "xref = 0x%x\n", (u_int)xref); 839 return (NULL); 840 } 841 ch->dmachan = SUNXI_DMA_ALLOC(ch->dmac, false, a10codec_dmaintr, ch); 842 if (ch->dmachan == NULL) { 843 device_printf(sc->dev, "cannot allocate DMA channel\n"); 844 return (NULL); 845 } 846 847 error = bus_dmamem_alloc(sc->dmat, &ch->dmaaddr, 848 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &ch->dmamap); 849 if (error != 0) { 850 device_printf(sc->dev, "cannot allocate channel buffer\n"); 851 return (NULL); 852 } 853 error = bus_dmamap_load(sc->dmat, ch->dmamap, ch->dmaaddr, 854 sc->dmasize, a10codec_dmamap_cb, ch, BUS_DMA_NOWAIT); 855 if (error != 0) { 856 device_printf(sc->dev, "cannot load DMA map\n"); 857 return (NULL); 858 } 859 memset(ch->dmaaddr, 0, sc->dmasize); 860 861 if (sndbuf_setup(ch->buffer, ch->dmaaddr, sc->dmasize) != 0) { 862 device_printf(sc->dev, "cannot setup sndbuf\n"); 863 return (NULL); 864 } 865 866 return (ch); 867 } 868 869 static int 870 a10codec_chan_free(kobj_t obj, void *data) 871 { 872 struct a10codec_chinfo *ch = data; 873 struct a10codec_info *sc = ch->parent; 874 875 SUNXI_DMA_FREE(ch->dmac, ch->dmachan); 876 bus_dmamap_unload(sc->dmat, ch->dmamap); 877 bus_dmamem_free(sc->dmat, ch->dmaaddr, ch->dmamap); 878 879 return (0); 880 } 881 882 static int 883 a10codec_chan_setformat(kobj_t obj, void *data, uint32_t format) 884 { 885 struct a10codec_chinfo *ch = data; 886 887 ch->format = format; 888 889 return (0); 890 } 891 892 static uint32_t 893 a10codec_chan_setspeed(kobj_t obj, void *data, uint32_t speed) 894 { 895 struct a10codec_chinfo *ch = data; 896 897 /* 898 * The codec supports full duplex operation but both DAC and ADC 899 * use the same source clock (PLL2). Limit the available speeds to 900 * those supported by a 24576000 Hz input. 901 */ 902 switch (speed) { 903 case 8000: 904 case 12000: 905 case 16000: 906 case 24000: 907 case 32000: 908 case 48000: 909 ch->speed = speed; 910 break; 911 case 96000: 912 case 192000: 913 /* 96 KHz / 192 KHz mode only supported for playback */ 914 if (ch->dir == PCMDIR_PLAY) { 915 ch->speed = speed; 916 } else { 917 ch->speed = 48000; 918 } 919 break; 920 case 44100: 921 ch->speed = 48000; 922 break; 923 case 22050: 924 ch->speed = 24000; 925 break; 926 case 11025: 927 ch->speed = 12000; 928 break; 929 default: 930 ch->speed = 48000; 931 break; 932 } 933 934 return (ch->speed); 935 } 936 937 static uint32_t 938 a10codec_chan_setblocksize(kobj_t obj, void *data, uint32_t blocksize) 939 { 940 struct a10codec_chinfo *ch = data; 941 942 ch->blocksize = blocksize & ~3; 943 944 return (ch->blocksize); 945 } 946 947 static int 948 a10codec_chan_trigger(kobj_t obj, void *data, int go) 949 { 950 struct a10codec_chinfo *ch = data; 951 struct a10codec_info *sc = ch->parent; 952 953 if (!PCMTRIG_COMMON(go)) 954 return (0); 955 956 snd_mtxlock(sc->lock); 957 switch (go) { 958 case PCMTRIG_START: 959 ch->run = 1; 960 a10codec_stop(ch); 961 a10codec_start(ch); 962 break; 963 case PCMTRIG_STOP: 964 case PCMTRIG_ABORT: 965 ch->run = 0; 966 a10codec_stop(ch); 967 break; 968 default: 969 break; 970 } 971 snd_mtxunlock(sc->lock); 972 973 return (0); 974 } 975 976 static uint32_t 977 a10codec_chan_getptr(kobj_t obj, void *data) 978 { 979 struct a10codec_chinfo *ch = data; 980 981 return (ch->pos); 982 } 983 984 static struct pcmchan_caps * 985 a10codec_chan_getcaps(kobj_t obj, void *data) 986 { 987 struct a10codec_chinfo *ch = data; 988 989 if (ch->dir == PCMDIR_PLAY) { 990 return (&a10codec_pcaps); 991 } else { 992 return (&a10codec_rcaps); 993 } 994 } 995 996 static kobj_method_t a10codec_chan_methods[] = { 997 KOBJMETHOD(channel_init, a10codec_chan_init), 998 KOBJMETHOD(channel_free, a10codec_chan_free), 999 KOBJMETHOD(channel_setformat, a10codec_chan_setformat), 1000 KOBJMETHOD(channel_setspeed, a10codec_chan_setspeed), 1001 KOBJMETHOD(channel_setblocksize, a10codec_chan_setblocksize), 1002 KOBJMETHOD(channel_trigger, a10codec_chan_trigger), 1003 KOBJMETHOD(channel_getptr, a10codec_chan_getptr), 1004 KOBJMETHOD(channel_getcaps, a10codec_chan_getcaps), 1005 KOBJMETHOD_END 1006 }; 1007 CHANNEL_DECLARE(a10codec_chan); 1008 1009 /* 1010 * Device interface 1011 */ 1012 1013 static const struct a10codec_config a10_config = { 1014 .mixer_class = &a10_mixer_class, 1015 .mute = a10_mute, 1016 .drqtype_codec = 19, 1017 .drqtype_sdram = 22, 1018 .DPC = 0x00, 1019 .DAC_FIFOC = 0x04, 1020 .DAC_FIFOS = 0x08, 1021 .DAC_TXDATA = 0x0c, 1022 .ADC_FIFOC = 0x1c, 1023 .ADC_FIFOS = 0x20, 1024 .ADC_RXDATA = 0x24, 1025 .DAC_CNT = 0x30, 1026 .ADC_CNT = 0x34, 1027 }; 1028 1029 static const struct a10codec_config h3_config = { 1030 .mixer_class = &h3_mixer_class, 1031 .mute = h3_mute, 1032 .drqtype_codec = 15, 1033 .drqtype_sdram = 1, 1034 .DPC = 0x00, 1035 .DAC_FIFOC = 0x04, 1036 .DAC_FIFOS = 0x08, 1037 .DAC_TXDATA = 0x20, 1038 .ADC_FIFOC = 0x10, 1039 .ADC_FIFOS = 0x14, 1040 .ADC_RXDATA = 0x18, 1041 .DAC_CNT = 0x40, 1042 .ADC_CNT = 0x44, 1043 }; 1044 1045 static struct ofw_compat_data compat_data[] = { 1046 { "allwinner,sun4i-a10-codec", (uintptr_t)&a10_config }, 1047 { "allwinner,sun7i-a20-codec", (uintptr_t)&a10_config }, 1048 { "allwinner,sun8i-h3-codec", (uintptr_t)&h3_config }, 1049 { NULL, 0 } 1050 }; 1051 1052 static int 1053 a10codec_probe(device_t dev) 1054 { 1055 if (!ofw_bus_status_okay(dev)) 1056 return (ENXIO); 1057 1058 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 1059 return (ENXIO); 1060 1061 device_set_desc(dev, "Allwinner Audio Codec"); 1062 return (BUS_PROBE_DEFAULT); 1063 } 1064 1065 static int 1066 a10codec_attach(device_t dev) 1067 { 1068 struct a10codec_info *sc; 1069 char status[SND_STATUSLEN]; 1070 struct gpiobus_pin *pa_pin; 1071 phandle_t node; 1072 clk_t clk_bus, clk_codec; 1073 hwreset_t rst; 1074 uint32_t val; 1075 int error; 1076 1077 node = ofw_bus_get_node(dev); 1078 1079 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); 1080 sc->cfg = (void *)ofw_bus_search_compatible(dev, compat_data)->ocd_data; 1081 sc->dev = dev; 1082 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "a10codec softc"); 1083 1084 if (bus_alloc_resources(dev, a10codec_spec, sc->res)) { 1085 device_printf(dev, "cannot allocate resources for device\n"); 1086 error = ENXIO; 1087 goto fail; 1088 } 1089 1090 sc->dmasize = 131072; 1091 error = bus_dma_tag_create( 1092 bus_get_dma_tag(dev), 1093 4, sc->dmasize, /* alignment, boundary */ 1094 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1095 BUS_SPACE_MAXADDR, /* highaddr */ 1096 NULL, NULL, /* filter, filterarg */ 1097 sc->dmasize, 1, /* maxsize, nsegs */ 1098 sc->dmasize, 0, /* maxsegsize, flags */ 1099 NULL, NULL, /* lockfunc, lockarg */ 1100 &sc->dmat); 1101 if (error != 0) { 1102 device_printf(dev, "cannot create DMA tag\n"); 1103 goto fail; 1104 } 1105 1106 /* Get clocks */ 1107 if (clk_get_by_ofw_name(dev, 0, "apb", &clk_bus) != 0 && 1108 clk_get_by_ofw_name(dev, 0, "ahb", &clk_bus) != 0) { 1109 device_printf(dev, "cannot find bus clock\n"); 1110 goto fail; 1111 } 1112 if (clk_get_by_ofw_name(dev, 0, "codec", &clk_codec) != 0) { 1113 device_printf(dev, "cannot find codec clock\n"); 1114 goto fail; 1115 } 1116 1117 /* Gating bus clock for codec */ 1118 if (clk_enable(clk_bus) != 0) { 1119 device_printf(dev, "cannot enable bus clock\n"); 1120 goto fail; 1121 } 1122 /* Activate audio codec clock. According to the A10 and A20 user 1123 * manuals, Audio_pll can be either 24.576MHz or 22.5792MHz. Most 1124 * audio sampling rates require an 24.576MHz input clock with the 1125 * exception of 44.1kHz, 22.05kHz, and 11.025kHz. Unfortunately, 1126 * both capture and playback use the same clock source so to 1127 * safely support independent full duplex operation, we use a fixed 1128 * 24.576MHz clock source and don't advertise native support for 1129 * the three sampling rates that require a 22.5792MHz input. 1130 */ 1131 error = clk_set_freq(clk_codec, 24576000, CLK_SET_ROUND_DOWN); 1132 if (error != 0) { 1133 device_printf(dev, "cannot set codec clock frequency\n"); 1134 goto fail; 1135 } 1136 /* Enable audio codec clock */ 1137 error = clk_enable(clk_codec); 1138 if (error != 0) { 1139 device_printf(dev, "cannot enable codec clock\n"); 1140 goto fail; 1141 } 1142 1143 /* De-assert hwreset */ 1144 if (hwreset_get_by_ofw_idx(dev, 0, 0, &rst) == 0) { 1145 error = hwreset_deassert(rst); 1146 if (error != 0) { 1147 device_printf(dev, "cannot de-assert reset\n"); 1148 goto fail; 1149 } 1150 } 1151 1152 /* Enable DAC */ 1153 val = CODEC_READ(sc, AC_DAC_DPC(sc)); 1154 val |= DAC_DPC_EN_DA; 1155 CODEC_WRITE(sc, AC_DAC_DPC(sc), val); 1156 1157 if (mixer_init(dev, sc->cfg->mixer_class, sc)) { 1158 device_printf(dev, "mixer_init failed\n"); 1159 goto fail; 1160 } 1161 1162 /* Unmute PA */ 1163 if (gpio_pin_get_by_ofw_property(dev, node, "allwinner,pa-gpios", 1164 &pa_pin) == 0) { 1165 error = gpio_pin_set_active(pa_pin, 1); 1166 if (error != 0) 1167 device_printf(dev, "failed to unmute PA\n"); 1168 } 1169 1170 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE); 1171 1172 if (pcm_register(dev, sc, 1, 1)) { 1173 device_printf(dev, "pcm_register failed\n"); 1174 goto fail; 1175 } 1176 1177 pcm_addchan(dev, PCMDIR_PLAY, &a10codec_chan_class, sc); 1178 pcm_addchan(dev, PCMDIR_REC, &a10codec_chan_class, sc); 1179 1180 snprintf(status, SND_STATUSLEN, "at %s", ofw_bus_get_name(dev)); 1181 pcm_setstatus(dev, status); 1182 1183 return (0); 1184 1185 fail: 1186 bus_release_resources(dev, a10codec_spec, sc->res); 1187 snd_mtxfree(sc->lock); 1188 free(sc, M_DEVBUF); 1189 1190 return (ENXIO); 1191 } 1192 1193 static device_method_t a10codec_pcm_methods[] = { 1194 /* Device interface */ 1195 DEVMETHOD(device_probe, a10codec_probe), 1196 DEVMETHOD(device_attach, a10codec_attach), 1197 1198 DEVMETHOD_END 1199 }; 1200 1201 static driver_t a10codec_pcm_driver = { 1202 "pcm", 1203 a10codec_pcm_methods, 1204 PCM_SOFTC_SIZE, 1205 }; 1206 1207 DRIVER_MODULE(a10codec, simplebus, a10codec_pcm_driver, 0, 0); 1208 MODULE_DEPEND(a10codec, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1209 MODULE_VERSION(a10codec, 1); 1210