1 /*- 2 * Copyright (c) 2014-2016 Jared D. McNeill <jmcneill@invisible.ca> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * Allwinner A10/A20 and H3 Audio Codec 29 */ 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 #include <sys/rman.h> 35 #include <sys/condvar.h> 36 #include <sys/kernel.h> 37 #include <sys/module.h> 38 #include <sys/gpio.h> 39 40 #include <machine/bus.h> 41 42 #include <dev/sound/pcm/sound.h> 43 44 #include <dev/ofw/ofw_bus.h> 45 #include <dev/ofw/ofw_bus_subr.h> 46 47 #include <dev/gpio/gpiobusvar.h> 48 49 #include <dev/clk/clk.h> 50 #include <dev/hwreset/hwreset.h> 51 52 #include "sunxi_dma_if.h" 53 #include "mixer_if.h" 54 55 struct a10codec_info; 56 57 struct a10codec_config { 58 /* mixer class */ 59 struct kobj_class *mixer_class; 60 61 /* toggle DAC/ADC mute */ 62 void (*mute)(struct a10codec_info *, int, int); 63 64 /* DRQ types */ 65 u_int drqtype_codec; 66 u_int drqtype_sdram; 67 68 /* register map */ 69 bus_size_t DPC, 70 DAC_FIFOC, 71 DAC_FIFOS, 72 DAC_TXDATA, 73 ADC_FIFOC, 74 ADC_FIFOS, 75 ADC_RXDATA, 76 DAC_CNT, 77 ADC_CNT; 78 }; 79 80 #define TX_TRIG_LEVEL 0xf 81 #define RX_TRIG_LEVEL 0x7 82 #define DRQ_CLR_CNT 0x3 83 84 #define AC_DAC_DPC(_sc) ((_sc)->cfg->DPC) 85 #define DAC_DPC_EN_DA 0x80000000 86 #define AC_DAC_FIFOC(_sc) ((_sc)->cfg->DAC_FIFOC) 87 #define DAC_FIFOC_FS_SHIFT 29 88 #define DAC_FIFOC_FS_MASK (7U << DAC_FIFOC_FS_SHIFT) 89 #define DAC_FS_48KHZ 0 90 #define DAC_FS_32KHZ 1 91 #define DAC_FS_24KHZ 2 92 #define DAC_FS_16KHZ 3 93 #define DAC_FS_12KHZ 4 94 #define DAC_FS_8KHZ 5 95 #define DAC_FS_192KHZ 6 96 #define DAC_FS_96KHZ 7 97 #define DAC_FIFOC_FIFO_MODE_SHIFT 24 98 #define DAC_FIFOC_FIFO_MODE_MASK (3U << DAC_FIFOC_FIFO_MODE_SHIFT) 99 #define FIFO_MODE_24_31_8 0 100 #define FIFO_MODE_16_31_16 0 101 #define FIFO_MODE_16_15_0 1 102 #define DAC_FIFOC_DRQ_CLR_CNT_SHIFT 21 103 #define DAC_FIFOC_DRQ_CLR_CNT_MASK (3U << DAC_FIFOC_DRQ_CLR_CNT_SHIFT) 104 #define DAC_FIFOC_TX_TRIG_LEVEL_SHIFT 8 105 #define DAC_FIFOC_TX_TRIG_LEVEL_MASK (0x7f << DAC_FIFOC_TX_TRIG_LEVEL_SHIFT) 106 #define DAC_FIFOC_MONO_EN (1U << 6) 107 #define DAC_FIFOC_TX_BITS (1U << 5) 108 #define DAC_FIFOC_DRQ_EN (1U << 4) 109 #define DAC_FIFOC_FIFO_FLUSH (1U << 0) 110 #define AC_DAC_FIFOS(_sc) ((_sc)->cfg->DAC_FIFOS) 111 #define AC_DAC_TXDATA(_sc) ((_sc)->cfg->DAC_TXDATA) 112 #define AC_ADC_FIFOC(_sc) ((_sc)->cfg->ADC_FIFOC) 113 #define ADC_FIFOC_FS_SHIFT 29 114 #define ADC_FIFOC_FS_MASK (7U << ADC_FIFOC_FS_SHIFT) 115 #define ADC_FS_48KHZ 0 116 #define ADC_FIFOC_EN_AD (1U << 28) 117 #define ADC_FIFOC_RX_FIFO_MODE (1U << 24) 118 #define ADC_FIFOC_RX_TRIG_LEVEL_SHIFT 8 119 #define ADC_FIFOC_RX_TRIG_LEVEL_MASK (0x1f << ADC_FIFOC_RX_TRIG_LEVEL_SHIFT) 120 #define ADC_FIFOC_MONO_EN (1U << 7) 121 #define ADC_FIFOC_RX_BITS (1U << 6) 122 #define ADC_FIFOC_DRQ_EN (1U << 4) 123 #define ADC_FIFOC_FIFO_FLUSH (1U << 1) 124 #define AC_ADC_FIFOS(_sc) ((_sc)->cfg->ADC_FIFOS) 125 #define AC_ADC_RXDATA(_sc) ((_sc)->cfg->ADC_RXDATA) 126 #define AC_DAC_CNT(_sc) ((_sc)->cfg->DAC_CNT) 127 #define AC_ADC_CNT(_sc) ((_sc)->cfg->ADC_CNT) 128 129 static uint32_t a10codec_fmt[] = { 130 SND_FORMAT(AFMT_S16_LE, 1, 0), 131 SND_FORMAT(AFMT_S16_LE, 2, 0), 132 0 133 }; 134 135 static struct pcmchan_caps a10codec_pcaps = { 8000, 192000, a10codec_fmt, 0 }; 136 static struct pcmchan_caps a10codec_rcaps = { 8000, 48000, a10codec_fmt, 0 }; 137 138 struct a10codec_info; 139 140 struct a10codec_chinfo { 141 struct snd_dbuf *buffer; 142 struct pcm_channel *channel; 143 struct a10codec_info *parent; 144 bus_dmamap_t dmamap; 145 void *dmaaddr; 146 bus_addr_t physaddr; 147 bus_size_t fifo; 148 device_t dmac; 149 void *dmachan; 150 151 int dir; 152 int run; 153 uint32_t pos; 154 uint32_t format; 155 uint32_t blocksize; 156 uint32_t speed; 157 }; 158 159 struct a10codec_info { 160 device_t dev; 161 struct resource *res[2]; 162 struct mtx *lock; 163 bus_dma_tag_t dmat; 164 unsigned dmasize; 165 void *ih; 166 167 struct a10codec_config *cfg; 168 169 struct a10codec_chinfo play; 170 struct a10codec_chinfo rec; 171 }; 172 173 static struct resource_spec a10codec_spec[] = { 174 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 175 { -1, 0 } 176 }; 177 178 #define CODEC_ANALOG_READ(sc, reg) bus_read_4((sc)->res[1], (reg)) 179 #define CODEC_ANALOG_WRITE(sc, reg, val) bus_write_4((sc)->res[1], (reg), (val)) 180 181 #define CODEC_READ(sc, reg) bus_read_4((sc)->res[0], (reg)) 182 #define CODEC_WRITE(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val)) 183 184 /* 185 * A10/A20 mixer interface 186 */ 187 188 #define A10_DAC_ACTL 0x10 189 #define A10_DACAREN (1U << 31) 190 #define A10_DACALEN (1U << 30) 191 #define A10_MIXEN (1U << 29) 192 #define A10_DACPAS (1U << 8) 193 #define A10_PAMUTE (1U << 6) 194 #define A10_PAVOL_SHIFT 0 195 #define A10_PAVOL_MASK (0x3f << A10_PAVOL_SHIFT) 196 #define A10_ADC_ACTL 0x28 197 #define A10_ADCREN (1U << 31) 198 #define A10_ADCLEN (1U << 30) 199 #define A10_PREG1EN (1U << 29) 200 #define A10_PREG2EN (1U << 28) 201 #define A10_VMICEN (1U << 27) 202 #define A10_ADCG_SHIFT 20 203 #define A10_ADCG_MASK (7U << A10_ADCG_SHIFT) 204 #define A10_ADCIS_SHIFT 17 205 #define A10_ADCIS_MASK (7U << A10_ADCIS_SHIFT) 206 #define A10_ADC_IS_LINEIN 0 207 #define A10_ADC_IS_FMIN 1 208 #define A10_ADC_IS_MIC1 2 209 #define A10_ADC_IS_MIC2 3 210 #define A10_ADC_IS_MIC1_L_MIC2_R 4 211 #define A10_ADC_IS_MIC1_LR_MIC2_LR 5 212 #define A10_ADC_IS_OMIX 6 213 #define A10_ADC_IS_LINEIN_L_MIC1_R 7 214 #define A10_LNRDF (1U << 16) 215 #define A10_LNPREG_SHIFT 13 216 #define A10_LNPREG_MASK (7U << A10_LNPREG_SHIFT) 217 #define A10_PA_EN (1U << 4) 218 #define A10_DDE (1U << 3) 219 220 static int 221 a10_mixer_init(struct snd_mixer *m) 222 { 223 struct a10codec_info *sc = mix_getdevinfo(m); 224 uint32_t val; 225 226 mix_setdevs(m, SOUND_MASK_VOLUME | SOUND_MASK_LINE | SOUND_MASK_RECLEV); 227 mix_setrecdevs(m, SOUND_MASK_LINE | SOUND_MASK_LINE1 | SOUND_MASK_MIC); 228 229 /* Unmute input source to PA */ 230 val = CODEC_READ(sc, A10_DAC_ACTL); 231 val |= A10_PAMUTE; 232 CODEC_WRITE(sc, A10_DAC_ACTL, val); 233 234 /* Enable PA */ 235 val = CODEC_READ(sc, A10_ADC_ACTL); 236 val |= A10_PA_EN; 237 CODEC_WRITE(sc, A10_ADC_ACTL, val); 238 239 return (0); 240 } 241 242 static const struct a10_mixer { 243 unsigned reg; 244 unsigned mask; 245 unsigned shift; 246 } a10_mixers[SOUND_MIXER_NRDEVICES] = { 247 [SOUND_MIXER_VOLUME] = { A10_DAC_ACTL, A10_PAVOL_MASK, 248 A10_PAVOL_SHIFT }, 249 [SOUND_MIXER_LINE] = { A10_ADC_ACTL, A10_LNPREG_MASK, 250 A10_LNPREG_SHIFT }, 251 [SOUND_MIXER_RECLEV] = { A10_ADC_ACTL, A10_ADCG_MASK, 252 A10_ADCG_SHIFT }, 253 }; 254 255 static int 256 a10_mixer_set(struct snd_mixer *m, unsigned dev, unsigned left, 257 unsigned right) 258 { 259 struct a10codec_info *sc = mix_getdevinfo(m); 260 uint32_t val; 261 unsigned nvol, max; 262 263 max = a10_mixers[dev].mask >> a10_mixers[dev].shift; 264 nvol = (left * max) / 100; 265 266 val = CODEC_READ(sc, a10_mixers[dev].reg); 267 val &= ~a10_mixers[dev].mask; 268 val |= (nvol << a10_mixers[dev].shift); 269 CODEC_WRITE(sc, a10_mixers[dev].reg, val); 270 271 left = right = (left * 100) / max; 272 return (left | (right << 8)); 273 } 274 275 static uint32_t 276 a10_mixer_setrecsrc(struct snd_mixer *m, uint32_t src) 277 { 278 struct a10codec_info *sc = mix_getdevinfo(m); 279 uint32_t val; 280 281 val = CODEC_READ(sc, A10_ADC_ACTL); 282 283 switch (src) { 284 case SOUND_MASK_LINE: /* line-in */ 285 val &= ~A10_ADCIS_MASK; 286 val |= (A10_ADC_IS_LINEIN << A10_ADCIS_SHIFT); 287 break; 288 case SOUND_MASK_MIC: /* MIC1 */ 289 val &= ~A10_ADCIS_MASK; 290 val |= (A10_ADC_IS_MIC1 << A10_ADCIS_SHIFT); 291 break; 292 case SOUND_MASK_LINE1: /* MIC2 */ 293 val &= ~A10_ADCIS_MASK; 294 val |= (A10_ADC_IS_MIC2 << A10_ADCIS_SHIFT); 295 break; 296 default: 297 break; 298 } 299 300 CODEC_WRITE(sc, A10_ADC_ACTL, val); 301 302 switch ((val & A10_ADCIS_MASK) >> A10_ADCIS_SHIFT) { 303 case A10_ADC_IS_LINEIN: 304 return (SOUND_MASK_LINE); 305 case A10_ADC_IS_MIC1: 306 return (SOUND_MASK_MIC); 307 case A10_ADC_IS_MIC2: 308 return (SOUND_MASK_LINE1); 309 default: 310 return (0); 311 } 312 } 313 314 static void 315 a10_mute(struct a10codec_info *sc, int mute, int dir) 316 { 317 uint32_t val; 318 319 if (dir == PCMDIR_PLAY) { 320 val = CODEC_READ(sc, A10_DAC_ACTL); 321 if (mute) { 322 /* Disable DAC analog l/r channels and output mixer */ 323 val &= ~A10_DACAREN; 324 val &= ~A10_DACALEN; 325 val &= ~A10_DACPAS; 326 } else { 327 /* Enable DAC analog l/r channels and output mixer */ 328 val |= A10_DACAREN; 329 val |= A10_DACALEN; 330 val |= A10_DACPAS; 331 } 332 CODEC_WRITE(sc, A10_DAC_ACTL, val); 333 } else { 334 val = CODEC_READ(sc, A10_ADC_ACTL); 335 if (mute) { 336 /* Disable ADC analog l/r channels, MIC1 preamp, 337 * and VMIC pin voltage 338 */ 339 val &= ~A10_ADCREN; 340 val &= ~A10_ADCLEN; 341 val &= ~A10_PREG1EN; 342 val &= ~A10_VMICEN; 343 } else { 344 /* Enable ADC analog l/r channels, MIC1 preamp, 345 * and VMIC pin voltage 346 */ 347 val |= A10_ADCREN; 348 val |= A10_ADCLEN; 349 val |= A10_PREG1EN; 350 val |= A10_VMICEN; 351 } 352 CODEC_WRITE(sc, A10_ADC_ACTL, val); 353 } 354 } 355 356 static kobj_method_t a10_mixer_methods[] = { 357 KOBJMETHOD(mixer_init, a10_mixer_init), 358 KOBJMETHOD(mixer_set, a10_mixer_set), 359 KOBJMETHOD(mixer_setrecsrc, a10_mixer_setrecsrc), 360 KOBJMETHOD_END 361 }; 362 MIXER_DECLARE(a10_mixer); 363 364 /* 365 * H3 mixer interface 366 */ 367 368 #define H3_PR_CFG 0x00 369 #define H3_AC_PR_RST (1 << 28) 370 #define H3_AC_PR_RW (1 << 24) 371 #define H3_AC_PR_ADDR_SHIFT 16 372 #define H3_AC_PR_ADDR_MASK (0x1f << H3_AC_PR_ADDR_SHIFT) 373 #define H3_ACDA_PR_WDAT_SHIFT 8 374 #define H3_ACDA_PR_WDAT_MASK (0xff << H3_ACDA_PR_WDAT_SHIFT) 375 #define H3_ACDA_PR_RDAT_SHIFT 0 376 #define H3_ACDA_PR_RDAT_MASK (0xff << H3_ACDA_PR_RDAT_SHIFT) 377 378 #define H3_LOMIXSC 0x01 379 #define H3_LOMIXSC_LDAC (1 << 1) 380 #define H3_ROMIXSC 0x02 381 #define H3_ROMIXSC_RDAC (1 << 1) 382 #define H3_DAC_PA_SRC 0x03 383 #define H3_DACAREN (1 << 7) 384 #define H3_DACALEN (1 << 6) 385 #define H3_RMIXEN (1 << 5) 386 #define H3_LMIXEN (1 << 4) 387 #define H3_LINEIN_GCTR 0x05 388 #define H3_LINEING_SHIFT 4 389 #define H3_LINEING_MASK (0x7 << H3_LINEING_SHIFT) 390 #define H3_MIC_GCTR 0x06 391 #define H3_MIC1_GAIN_SHIFT 4 392 #define H3_MIC1_GAIN_MASK (0x7 << H3_MIC1_GAIN_SHIFT) 393 #define H3_MIC2_GAIN_SHIFT 0 394 #define H3_MIC2_GAIN_MASK (0x7 << H3_MIC2_GAIN_SHIFT) 395 #define H3_PAEN_CTR 0x07 396 #define H3_LINEOUTEN (1 << 7) 397 #define H3_LINEOUT_VOLC 0x09 398 #define H3_LINEOUTVOL_SHIFT 3 399 #define H3_LINEOUTVOL_MASK (0x1f << H3_LINEOUTVOL_SHIFT) 400 #define H3_MIC2G_LINEOUT_CTR 0x0a 401 #define H3_LINEOUT_LSEL (1 << 3) 402 #define H3_LINEOUT_RSEL (1 << 2) 403 #define H3_LADCMIXSC 0x0c 404 #define H3_RADCMIXSC 0x0d 405 #define H3_ADCMIXSC_MIC1 (1 << 6) 406 #define H3_ADCMIXSC_MIC2 (1 << 5) 407 #define H3_ADCMIXSC_LINEIN (1 << 2) 408 #define H3_ADCMIXSC_OMIXER (3 << 0) 409 #define H3_ADC_AP_EN 0x0f 410 #define H3_ADCREN (1 << 7) 411 #define H3_ADCLEN (1 << 6) 412 #define H3_ADCG_SHIFT 0 413 #define H3_ADCG_MASK (0x7 << H3_ADCG_SHIFT) 414 415 static u_int 416 h3_pr_read(struct a10codec_info *sc, u_int addr) 417 { 418 uint32_t val; 419 420 /* Read current value */ 421 val = CODEC_ANALOG_READ(sc, H3_PR_CFG); 422 423 /* De-assert reset */ 424 val |= H3_AC_PR_RST; 425 CODEC_ANALOG_WRITE(sc, H3_PR_CFG, val); 426 427 /* Read mode */ 428 val &= ~H3_AC_PR_RW; 429 CODEC_ANALOG_WRITE(sc, H3_PR_CFG, val); 430 431 /* Set address */ 432 val &= ~H3_AC_PR_ADDR_MASK; 433 val |= (addr << H3_AC_PR_ADDR_SHIFT); 434 CODEC_ANALOG_WRITE(sc, H3_PR_CFG, val); 435 436 /* Read data */ 437 return (CODEC_ANALOG_READ(sc , H3_PR_CFG) & H3_ACDA_PR_RDAT_MASK); 438 } 439 440 static void 441 h3_pr_write(struct a10codec_info *sc, u_int addr, u_int data) 442 { 443 uint32_t val; 444 445 /* Read current value */ 446 val = CODEC_ANALOG_READ(sc, H3_PR_CFG); 447 448 /* De-assert reset */ 449 val |= H3_AC_PR_RST; 450 CODEC_ANALOG_WRITE(sc, H3_PR_CFG, val); 451 452 /* Set address */ 453 val &= ~H3_AC_PR_ADDR_MASK; 454 val |= (addr << H3_AC_PR_ADDR_SHIFT); 455 CODEC_ANALOG_WRITE(sc, H3_PR_CFG, val); 456 457 /* Write data */ 458 val &= ~H3_ACDA_PR_WDAT_MASK; 459 val |= (data << H3_ACDA_PR_WDAT_SHIFT); 460 CODEC_ANALOG_WRITE(sc, H3_PR_CFG, val); 461 462 /* Write mode */ 463 val |= H3_AC_PR_RW; 464 CODEC_ANALOG_WRITE(sc, H3_PR_CFG, val); 465 } 466 467 static void 468 h3_pr_set_clear(struct a10codec_info *sc, u_int addr, u_int set, u_int clr) 469 { 470 u_int old, new; 471 472 old = h3_pr_read(sc, addr); 473 new = set | (old & ~clr); 474 h3_pr_write(sc, addr, new); 475 } 476 477 static int 478 h3_mixer_init(struct snd_mixer *m) 479 { 480 int rid=1; 481 pcell_t reg[2]; 482 phandle_t analogref; 483 struct a10codec_info *sc = mix_getdevinfo(m); 484 485 if (OF_getencprop(ofw_bus_get_node(sc->dev), "allwinner,codec-analog-controls", 486 &analogref, sizeof(analogref)) <= 0) { 487 return (ENXIO); 488 } 489 490 if (OF_getencprop(OF_node_from_xref(analogref), "reg", 491 reg, sizeof(reg)) <= 0) { 492 return (ENXIO); 493 } 494 495 sc->res[1] = bus_alloc_resource(sc->dev, SYS_RES_MEMORY, &rid, reg[0], 496 reg[0]+reg[1], reg[1], RF_ACTIVE ); 497 498 if (sc->res[1] == NULL) { 499 return (ENXIO); 500 } 501 502 mix_setdevs(m, SOUND_MASK_PCM | SOUND_MASK_VOLUME | SOUND_MASK_RECLEV | 503 SOUND_MASK_MIC | SOUND_MASK_LINE | SOUND_MASK_LINE1); 504 mix_setrecdevs(m, SOUND_MASK_MIC | SOUND_MASK_LINE | SOUND_MASK_LINE1 | 505 SOUND_MASK_IMIX); 506 507 pcm_setflags(sc->dev, pcm_getflags(sc->dev) | SD_F_SOFTPCMVOL); 508 509 /* Right & Left LINEOUT enable */ 510 h3_pr_set_clear(sc, H3_PAEN_CTR, H3_LINEOUTEN, 0); 511 h3_pr_set_clear(sc, H3_MIC2G_LINEOUT_CTR, 512 H3_LINEOUT_LSEL | H3_LINEOUT_RSEL, 0); 513 514 return (0); 515 } 516 517 static const struct h3_mixer { 518 unsigned reg; 519 unsigned mask; 520 unsigned shift; 521 } h3_mixers[SOUND_MIXER_NRDEVICES] = { 522 [SOUND_MIXER_VOLUME] = { H3_LINEOUT_VOLC, H3_LINEOUTVOL_MASK, 523 H3_LINEOUTVOL_SHIFT }, 524 [SOUND_MIXER_RECLEV] = { H3_ADC_AP_EN, H3_ADCG_MASK, 525 H3_ADCG_SHIFT }, 526 [SOUND_MIXER_LINE] = { H3_LINEIN_GCTR, H3_LINEING_MASK, 527 H3_LINEING_SHIFT }, 528 [SOUND_MIXER_MIC] = { H3_MIC_GCTR, H3_MIC1_GAIN_MASK, 529 H3_MIC1_GAIN_SHIFT }, 530 [SOUND_MIXER_LINE1] = { H3_MIC_GCTR, H3_MIC2_GAIN_MASK, 531 H3_MIC2_GAIN_SHIFT }, 532 }; 533 534 static int 535 h3_mixer_set(struct snd_mixer *m, unsigned dev, unsigned left, 536 unsigned right) 537 { 538 struct a10codec_info *sc = mix_getdevinfo(m); 539 unsigned nvol, max; 540 541 max = h3_mixers[dev].mask >> h3_mixers[dev].shift; 542 nvol = (left * max) / 100; 543 544 h3_pr_set_clear(sc, h3_mixers[dev].reg, 545 nvol << h3_mixers[dev].shift, h3_mixers[dev].mask); 546 547 left = right = (left * 100) / max; 548 return (left | (right << 8)); 549 } 550 551 static uint32_t 552 h3_mixer_setrecsrc(struct snd_mixer *m, uint32_t src) 553 { 554 struct a10codec_info *sc = mix_getdevinfo(m); 555 uint32_t val; 556 557 val = 0; 558 src &= (SOUND_MASK_LINE | SOUND_MASK_MIC | 559 SOUND_MASK_LINE1 | SOUND_MASK_IMIX); 560 561 if ((src & SOUND_MASK_LINE) != 0) /* line-in */ 562 val |= H3_ADCMIXSC_LINEIN; 563 if ((src & SOUND_MASK_MIC) != 0) /* MIC1 */ 564 val |= H3_ADCMIXSC_MIC1; 565 if ((src & SOUND_MASK_LINE1) != 0) /* MIC2 */ 566 val |= H3_ADCMIXSC_MIC2; 567 if ((src & SOUND_MASK_IMIX) != 0) /* l/r output mixer */ 568 val |= H3_ADCMIXSC_OMIXER; 569 570 h3_pr_write(sc, H3_LADCMIXSC, val); 571 h3_pr_write(sc, H3_RADCMIXSC, val); 572 573 return (src); 574 } 575 576 static void 577 h3_mute(struct a10codec_info *sc, int mute, int dir) 578 { 579 if (dir == PCMDIR_PLAY) { 580 if (mute) { 581 /* Mute DAC l/r channels to output mixer */ 582 h3_pr_set_clear(sc, H3_LOMIXSC, 0, H3_LOMIXSC_LDAC); 583 h3_pr_set_clear(sc, H3_ROMIXSC, 0, H3_ROMIXSC_RDAC); 584 /* Disable DAC analog l/r channels and output mixer */ 585 h3_pr_set_clear(sc, H3_DAC_PA_SRC, 586 0, H3_DACAREN | H3_DACALEN | H3_RMIXEN | H3_LMIXEN); 587 } else { 588 /* Enable DAC analog l/r channels and output mixer */ 589 h3_pr_set_clear(sc, H3_DAC_PA_SRC, 590 H3_DACAREN | H3_DACALEN | H3_RMIXEN | H3_LMIXEN, 0); 591 /* Unmute DAC l/r channels to output mixer */ 592 h3_pr_set_clear(sc, H3_LOMIXSC, H3_LOMIXSC_LDAC, 0); 593 h3_pr_set_clear(sc, H3_ROMIXSC, H3_ROMIXSC_RDAC, 0); 594 } 595 } else { 596 if (mute) { 597 /* Disable ADC analog l/r channels */ 598 h3_pr_set_clear(sc, H3_ADC_AP_EN, 599 0, H3_ADCREN | H3_ADCLEN); 600 } else { 601 /* Enable ADC analog l/r channels */ 602 h3_pr_set_clear(sc, H3_ADC_AP_EN, 603 H3_ADCREN | H3_ADCLEN, 0); 604 } 605 } 606 } 607 608 static kobj_method_t h3_mixer_methods[] = { 609 KOBJMETHOD(mixer_init, h3_mixer_init), 610 KOBJMETHOD(mixer_set, h3_mixer_set), 611 KOBJMETHOD(mixer_setrecsrc, h3_mixer_setrecsrc), 612 KOBJMETHOD_END 613 }; 614 MIXER_DECLARE(h3_mixer); 615 616 /* 617 * Channel interface 618 */ 619 620 static void 621 a10codec_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 622 { 623 struct a10codec_chinfo *ch = arg; 624 625 if (error != 0) 626 return; 627 628 ch->physaddr = segs[0].ds_addr; 629 } 630 631 static void 632 a10codec_transfer(struct a10codec_chinfo *ch) 633 { 634 bus_addr_t src, dst; 635 int error; 636 637 if (ch->dir == PCMDIR_PLAY) { 638 src = ch->physaddr + ch->pos; 639 dst = ch->fifo; 640 } else { 641 src = ch->fifo; 642 dst = ch->physaddr + ch->pos; 643 } 644 645 error = SUNXI_DMA_TRANSFER(ch->dmac, ch->dmachan, src, dst, 646 ch->blocksize); 647 if (error) { 648 ch->run = 0; 649 device_printf(ch->parent->dev, "DMA transfer failed: %d\n", 650 error); 651 } 652 } 653 654 static void 655 a10codec_dmaconfig(struct a10codec_chinfo *ch) 656 { 657 struct a10codec_info *sc = ch->parent; 658 struct sunxi_dma_config conf; 659 660 memset(&conf, 0, sizeof(conf)); 661 conf.src_width = conf.dst_width = 16; 662 conf.src_burst_len = conf.dst_burst_len = 4; 663 664 if (ch->dir == PCMDIR_PLAY) { 665 conf.dst_noincr = true; 666 conf.src_drqtype = sc->cfg->drqtype_sdram; 667 conf.dst_drqtype = sc->cfg->drqtype_codec; 668 } else { 669 conf.src_noincr = true; 670 conf.src_drqtype = sc->cfg->drqtype_codec; 671 conf.dst_drqtype = sc->cfg->drqtype_sdram; 672 } 673 674 SUNXI_DMA_SET_CONFIG(ch->dmac, ch->dmachan, &conf); 675 } 676 677 static void 678 a10codec_dmaintr(void *priv) 679 { 680 struct a10codec_chinfo *ch = priv; 681 unsigned bufsize; 682 683 bufsize = sndbuf_getsize(ch->buffer); 684 685 ch->pos += ch->blocksize; 686 if (ch->pos >= bufsize) 687 ch->pos -= bufsize; 688 689 if (ch->run) { 690 chn_intr(ch->channel); 691 a10codec_transfer(ch); 692 } 693 } 694 695 static unsigned 696 a10codec_fs(struct a10codec_chinfo *ch) 697 { 698 switch (ch->speed) { 699 case 48000: 700 return (DAC_FS_48KHZ); 701 case 24000: 702 return (DAC_FS_24KHZ); 703 case 12000: 704 return (DAC_FS_12KHZ); 705 case 192000: 706 return (DAC_FS_192KHZ); 707 case 32000: 708 return (DAC_FS_32KHZ); 709 case 16000: 710 return (DAC_FS_16KHZ); 711 case 8000: 712 return (DAC_FS_8KHZ); 713 case 96000: 714 return (DAC_FS_96KHZ); 715 default: 716 return (DAC_FS_48KHZ); 717 } 718 } 719 720 static void 721 a10codec_start(struct a10codec_chinfo *ch) 722 { 723 struct a10codec_info *sc = ch->parent; 724 uint32_t val; 725 726 ch->pos = 0; 727 728 if (ch->dir == PCMDIR_PLAY) { 729 /* Flush DAC FIFO */ 730 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), DAC_FIFOC_FIFO_FLUSH); 731 732 /* Clear DAC FIFO status */ 733 CODEC_WRITE(sc, AC_DAC_FIFOS(sc), 734 CODEC_READ(sc, AC_DAC_FIFOS(sc))); 735 736 /* Unmute output */ 737 sc->cfg->mute(sc, 0, ch->dir); 738 739 /* Configure DAC DMA channel */ 740 a10codec_dmaconfig(ch); 741 742 /* Configure DAC FIFO */ 743 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), 744 (AFMT_CHANNEL(ch->format) == 1 ? DAC_FIFOC_MONO_EN : 0) | 745 (a10codec_fs(ch) << DAC_FIFOC_FS_SHIFT) | 746 (FIFO_MODE_16_15_0 << DAC_FIFOC_FIFO_MODE_SHIFT) | 747 (DRQ_CLR_CNT << DAC_FIFOC_DRQ_CLR_CNT_SHIFT) | 748 (TX_TRIG_LEVEL << DAC_FIFOC_TX_TRIG_LEVEL_SHIFT)); 749 750 /* Enable DAC DRQ */ 751 val = CODEC_READ(sc, AC_DAC_FIFOC(sc)); 752 val |= DAC_FIFOC_DRQ_EN; 753 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), val); 754 } else { 755 /* Flush ADC FIFO */ 756 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), ADC_FIFOC_FIFO_FLUSH); 757 758 /* Clear ADC FIFO status */ 759 CODEC_WRITE(sc, AC_ADC_FIFOS(sc), 760 CODEC_READ(sc, AC_ADC_FIFOS(sc))); 761 762 /* Unmute input */ 763 sc->cfg->mute(sc, 0, ch->dir); 764 765 /* Configure ADC DMA channel */ 766 a10codec_dmaconfig(ch); 767 768 /* Configure ADC FIFO */ 769 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), 770 ADC_FIFOC_EN_AD | 771 ADC_FIFOC_RX_FIFO_MODE | 772 (AFMT_CHANNEL(ch->format) == 1 ? ADC_FIFOC_MONO_EN : 0) | 773 (a10codec_fs(ch) << ADC_FIFOC_FS_SHIFT) | 774 (RX_TRIG_LEVEL << ADC_FIFOC_RX_TRIG_LEVEL_SHIFT)); 775 776 /* Enable ADC DRQ */ 777 val = CODEC_READ(sc, AC_ADC_FIFOC(sc)); 778 val |= ADC_FIFOC_DRQ_EN; 779 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), val); 780 } 781 782 /* Start DMA transfer */ 783 a10codec_transfer(ch); 784 } 785 786 static void 787 a10codec_stop(struct a10codec_chinfo *ch) 788 { 789 struct a10codec_info *sc = ch->parent; 790 791 /* Disable DMA channel */ 792 SUNXI_DMA_HALT(ch->dmac, ch->dmachan); 793 794 sc->cfg->mute(sc, 1, ch->dir); 795 796 if (ch->dir == PCMDIR_PLAY) { 797 /* Disable DAC DRQ */ 798 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), 0); 799 } else { 800 /* Disable ADC DRQ */ 801 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), 0); 802 } 803 } 804 805 static void * 806 a10codec_chan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, 807 struct pcm_channel *c, int dir) 808 { 809 struct a10codec_info *sc = devinfo; 810 struct a10codec_chinfo *ch = dir == PCMDIR_PLAY ? &sc->play : &sc->rec; 811 phandle_t xref; 812 pcell_t *cells; 813 int ncells, error; 814 815 error = ofw_bus_parse_xref_list_alloc(ofw_bus_get_node(sc->dev), 816 "dmas", "#dma-cells", dir == PCMDIR_PLAY ? 1 : 0, 817 &xref, &ncells, &cells); 818 if (error != 0) { 819 device_printf(sc->dev, "cannot parse 'dmas' property\n"); 820 return (NULL); 821 } 822 OF_prop_free(cells); 823 824 ch->parent = sc; 825 ch->channel = c; 826 ch->buffer = b; 827 ch->dir = dir; 828 ch->fifo = rman_get_start(sc->res[0]) + 829 (dir == PCMDIR_REC ? AC_ADC_RXDATA(sc) : AC_DAC_TXDATA(sc)); 830 831 ch->dmac = OF_device_from_xref(xref); 832 if (ch->dmac == NULL) { 833 device_printf(sc->dev, "cannot find DMA controller\n"); 834 device_printf(sc->dev, "xref = 0x%x\n", (u_int)xref); 835 return (NULL); 836 } 837 ch->dmachan = SUNXI_DMA_ALLOC(ch->dmac, false, a10codec_dmaintr, ch); 838 if (ch->dmachan == NULL) { 839 device_printf(sc->dev, "cannot allocate DMA channel\n"); 840 return (NULL); 841 } 842 843 error = bus_dmamem_alloc(sc->dmat, &ch->dmaaddr, 844 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &ch->dmamap); 845 if (error != 0) { 846 device_printf(sc->dev, "cannot allocate channel buffer\n"); 847 return (NULL); 848 } 849 error = bus_dmamap_load(sc->dmat, ch->dmamap, ch->dmaaddr, 850 sc->dmasize, a10codec_dmamap_cb, ch, BUS_DMA_NOWAIT); 851 if (error != 0) { 852 device_printf(sc->dev, "cannot load DMA map\n"); 853 return (NULL); 854 } 855 memset(ch->dmaaddr, 0, sc->dmasize); 856 857 if (sndbuf_setup(ch->buffer, ch->dmaaddr, sc->dmasize) != 0) { 858 device_printf(sc->dev, "cannot setup sndbuf\n"); 859 return (NULL); 860 } 861 862 return (ch); 863 } 864 865 static int 866 a10codec_chan_free(kobj_t obj, void *data) 867 { 868 struct a10codec_chinfo *ch = data; 869 struct a10codec_info *sc = ch->parent; 870 871 SUNXI_DMA_FREE(ch->dmac, ch->dmachan); 872 bus_dmamap_unload(sc->dmat, ch->dmamap); 873 bus_dmamem_free(sc->dmat, ch->dmaaddr, ch->dmamap); 874 875 return (0); 876 } 877 878 static int 879 a10codec_chan_setformat(kobj_t obj, void *data, uint32_t format) 880 { 881 struct a10codec_chinfo *ch = data; 882 883 ch->format = format; 884 885 return (0); 886 } 887 888 static uint32_t 889 a10codec_chan_setspeed(kobj_t obj, void *data, uint32_t speed) 890 { 891 struct a10codec_chinfo *ch = data; 892 893 /* 894 * The codec supports full duplex operation but both DAC and ADC 895 * use the same source clock (PLL2). Limit the available speeds to 896 * those supported by a 24576000 Hz input. 897 */ 898 switch (speed) { 899 case 8000: 900 case 12000: 901 case 16000: 902 case 24000: 903 case 32000: 904 case 48000: 905 ch->speed = speed; 906 break; 907 case 96000: 908 case 192000: 909 /* 96 KHz / 192 KHz mode only supported for playback */ 910 if (ch->dir == PCMDIR_PLAY) { 911 ch->speed = speed; 912 } else { 913 ch->speed = 48000; 914 } 915 break; 916 case 44100: 917 ch->speed = 48000; 918 break; 919 case 22050: 920 ch->speed = 24000; 921 break; 922 case 11025: 923 ch->speed = 12000; 924 break; 925 default: 926 ch->speed = 48000; 927 break; 928 } 929 930 return (ch->speed); 931 } 932 933 static uint32_t 934 a10codec_chan_setblocksize(kobj_t obj, void *data, uint32_t blocksize) 935 { 936 struct a10codec_chinfo *ch = data; 937 938 ch->blocksize = blocksize & ~3; 939 940 return (ch->blocksize); 941 } 942 943 static int 944 a10codec_chan_trigger(kobj_t obj, void *data, int go) 945 { 946 struct a10codec_chinfo *ch = data; 947 struct a10codec_info *sc = ch->parent; 948 949 if (!PCMTRIG_COMMON(go)) 950 return (0); 951 952 snd_mtxlock(sc->lock); 953 switch (go) { 954 case PCMTRIG_START: 955 ch->run = 1; 956 a10codec_stop(ch); 957 a10codec_start(ch); 958 break; 959 case PCMTRIG_STOP: 960 case PCMTRIG_ABORT: 961 ch->run = 0; 962 a10codec_stop(ch); 963 break; 964 default: 965 break; 966 } 967 snd_mtxunlock(sc->lock); 968 969 return (0); 970 } 971 972 static uint32_t 973 a10codec_chan_getptr(kobj_t obj, void *data) 974 { 975 struct a10codec_chinfo *ch = data; 976 977 return (ch->pos); 978 } 979 980 static struct pcmchan_caps * 981 a10codec_chan_getcaps(kobj_t obj, void *data) 982 { 983 struct a10codec_chinfo *ch = data; 984 985 if (ch->dir == PCMDIR_PLAY) { 986 return (&a10codec_pcaps); 987 } else { 988 return (&a10codec_rcaps); 989 } 990 } 991 992 static kobj_method_t a10codec_chan_methods[] = { 993 KOBJMETHOD(channel_init, a10codec_chan_init), 994 KOBJMETHOD(channel_free, a10codec_chan_free), 995 KOBJMETHOD(channel_setformat, a10codec_chan_setformat), 996 KOBJMETHOD(channel_setspeed, a10codec_chan_setspeed), 997 KOBJMETHOD(channel_setblocksize, a10codec_chan_setblocksize), 998 KOBJMETHOD(channel_trigger, a10codec_chan_trigger), 999 KOBJMETHOD(channel_getptr, a10codec_chan_getptr), 1000 KOBJMETHOD(channel_getcaps, a10codec_chan_getcaps), 1001 KOBJMETHOD_END 1002 }; 1003 CHANNEL_DECLARE(a10codec_chan); 1004 1005 /* 1006 * Device interface 1007 */ 1008 1009 static const struct a10codec_config a10_config = { 1010 .mixer_class = &a10_mixer_class, 1011 .mute = a10_mute, 1012 .drqtype_codec = 19, 1013 .drqtype_sdram = 22, 1014 .DPC = 0x00, 1015 .DAC_FIFOC = 0x04, 1016 .DAC_FIFOS = 0x08, 1017 .DAC_TXDATA = 0x0c, 1018 .ADC_FIFOC = 0x1c, 1019 .ADC_FIFOS = 0x20, 1020 .ADC_RXDATA = 0x24, 1021 .DAC_CNT = 0x30, 1022 .ADC_CNT = 0x34, 1023 }; 1024 1025 static const struct a10codec_config h3_config = { 1026 .mixer_class = &h3_mixer_class, 1027 .mute = h3_mute, 1028 .drqtype_codec = 15, 1029 .drqtype_sdram = 1, 1030 .DPC = 0x00, 1031 .DAC_FIFOC = 0x04, 1032 .DAC_FIFOS = 0x08, 1033 .DAC_TXDATA = 0x20, 1034 .ADC_FIFOC = 0x10, 1035 .ADC_FIFOS = 0x14, 1036 .ADC_RXDATA = 0x18, 1037 .DAC_CNT = 0x40, 1038 .ADC_CNT = 0x44, 1039 }; 1040 1041 static struct ofw_compat_data compat_data[] = { 1042 { "allwinner,sun4i-a10-codec", (uintptr_t)&a10_config }, 1043 { "allwinner,sun7i-a20-codec", (uintptr_t)&a10_config }, 1044 { "allwinner,sun8i-h3-codec", (uintptr_t)&h3_config }, 1045 { NULL, 0 } 1046 }; 1047 1048 static int 1049 a10codec_probe(device_t dev) 1050 { 1051 if (!ofw_bus_status_okay(dev)) 1052 return (ENXIO); 1053 1054 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 1055 return (ENXIO); 1056 1057 device_set_desc(dev, "Allwinner Audio Codec"); 1058 return (BUS_PROBE_DEFAULT); 1059 } 1060 1061 static int 1062 a10codec_attach(device_t dev) 1063 { 1064 struct a10codec_info *sc; 1065 char status[SND_STATUSLEN]; 1066 struct gpiobus_pin *pa_pin; 1067 phandle_t node; 1068 clk_t clk_bus, clk_codec; 1069 hwreset_t rst; 1070 uint32_t val; 1071 int error; 1072 1073 node = ofw_bus_get_node(dev); 1074 1075 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); 1076 sc->cfg = (void *)ofw_bus_search_compatible(dev, compat_data)->ocd_data; 1077 sc->dev = dev; 1078 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "a10codec softc"); 1079 1080 if (bus_alloc_resources(dev, a10codec_spec, sc->res)) { 1081 device_printf(dev, "cannot allocate resources for device\n"); 1082 error = ENXIO; 1083 goto fail; 1084 } 1085 1086 sc->dmasize = 131072; 1087 error = bus_dma_tag_create( 1088 bus_get_dma_tag(dev), 1089 4, sc->dmasize, /* alignment, boundary */ 1090 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1091 BUS_SPACE_MAXADDR, /* highaddr */ 1092 NULL, NULL, /* filter, filterarg */ 1093 sc->dmasize, 1, /* maxsize, nsegs */ 1094 sc->dmasize, 0, /* maxsegsize, flags */ 1095 NULL, NULL, /* lockfunc, lockarg */ 1096 &sc->dmat); 1097 if (error != 0) { 1098 device_printf(dev, "cannot create DMA tag\n"); 1099 goto fail; 1100 } 1101 1102 /* Get clocks */ 1103 if (clk_get_by_ofw_name(dev, 0, "apb", &clk_bus) != 0 && 1104 clk_get_by_ofw_name(dev, 0, "ahb", &clk_bus) != 0) { 1105 device_printf(dev, "cannot find bus clock\n"); 1106 goto fail; 1107 } 1108 if (clk_get_by_ofw_name(dev, 0, "codec", &clk_codec) != 0) { 1109 device_printf(dev, "cannot find codec clock\n"); 1110 goto fail; 1111 } 1112 1113 /* Gating bus clock for codec */ 1114 if (clk_enable(clk_bus) != 0) { 1115 device_printf(dev, "cannot enable bus clock\n"); 1116 goto fail; 1117 } 1118 /* Activate audio codec clock. According to the A10 and A20 user 1119 * manuals, Audio_pll can be either 24.576MHz or 22.5792MHz. Most 1120 * audio sampling rates require an 24.576MHz input clock with the 1121 * exception of 44.1kHz, 22.05kHz, and 11.025kHz. Unfortunately, 1122 * both capture and playback use the same clock source so to 1123 * safely support independent full duplex operation, we use a fixed 1124 * 24.576MHz clock source and don't advertise native support for 1125 * the three sampling rates that require a 22.5792MHz input. 1126 */ 1127 error = clk_set_freq(clk_codec, 24576000, CLK_SET_ROUND_DOWN); 1128 if (error != 0) { 1129 device_printf(dev, "cannot set codec clock frequency\n"); 1130 goto fail; 1131 } 1132 /* Enable audio codec clock */ 1133 error = clk_enable(clk_codec); 1134 if (error != 0) { 1135 device_printf(dev, "cannot enable codec clock\n"); 1136 goto fail; 1137 } 1138 1139 /* De-assert hwreset */ 1140 if (hwreset_get_by_ofw_idx(dev, 0, 0, &rst) == 0) { 1141 error = hwreset_deassert(rst); 1142 if (error != 0) { 1143 device_printf(dev, "cannot de-assert reset\n"); 1144 goto fail; 1145 } 1146 } 1147 1148 /* Enable DAC */ 1149 val = CODEC_READ(sc, AC_DAC_DPC(sc)); 1150 val |= DAC_DPC_EN_DA; 1151 CODEC_WRITE(sc, AC_DAC_DPC(sc), val); 1152 1153 if (mixer_init(dev, sc->cfg->mixer_class, sc)) { 1154 device_printf(dev, "mixer_init failed\n"); 1155 goto fail; 1156 } 1157 1158 /* Unmute PA */ 1159 if (gpio_pin_get_by_ofw_property(dev, node, "allwinner,pa-gpios", 1160 &pa_pin) == 0) { 1161 error = gpio_pin_set_active(pa_pin, 1); 1162 if (error != 0) 1163 device_printf(dev, "failed to unmute PA\n"); 1164 } 1165 1166 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE); 1167 1168 pcm_init(dev, sc); 1169 1170 pcm_addchan(dev, PCMDIR_PLAY, &a10codec_chan_class, sc); 1171 pcm_addchan(dev, PCMDIR_REC, &a10codec_chan_class, sc); 1172 1173 snprintf(status, SND_STATUSLEN, "at %s", ofw_bus_get_name(dev)); 1174 if (pcm_register(dev, status)) { 1175 device_printf(dev, "pcm_register failed\n"); 1176 goto fail; 1177 } 1178 1179 return (0); 1180 1181 fail: 1182 bus_release_resources(dev, a10codec_spec, sc->res); 1183 snd_mtxfree(sc->lock); 1184 free(sc, M_DEVBUF); 1185 1186 return (ENXIO); 1187 } 1188 1189 static device_method_t a10codec_pcm_methods[] = { 1190 /* Device interface */ 1191 DEVMETHOD(device_probe, a10codec_probe), 1192 DEVMETHOD(device_attach, a10codec_attach), 1193 1194 DEVMETHOD_END 1195 }; 1196 1197 static driver_t a10codec_pcm_driver = { 1198 "pcm", 1199 a10codec_pcm_methods, 1200 PCM_SOFTC_SIZE, 1201 }; 1202 1203 DRIVER_MODULE(a10codec, simplebus, a10codec_pcm_driver, 0, 0); 1204 MODULE_DEPEND(a10codec, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1205 MODULE_VERSION(a10codec, 1); 1206