1 /*- 2 * Copyright (c) 2014-2016 Jared D. McNeill <jmcneill@invisible.ca> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * Allwinner A10/A20 and H3 Audio Codec 29 */ 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 #include <sys/rman.h> 35 #include <sys/condvar.h> 36 #include <sys/kernel.h> 37 #include <sys/module.h> 38 #include <sys/gpio.h> 39 40 #include <machine/bus.h> 41 42 #include <dev/sound/pcm/sound.h> 43 #include <dev/sound/chip.h> 44 45 #include <dev/ofw/ofw_bus.h> 46 #include <dev/ofw/ofw_bus_subr.h> 47 48 #include <dev/gpio/gpiobusvar.h> 49 50 #include <dev/clk/clk.h> 51 #include <dev/hwreset/hwreset.h> 52 53 #include "sunxi_dma_if.h" 54 #include "mixer_if.h" 55 56 struct a10codec_info; 57 58 struct a10codec_config { 59 /* mixer class */ 60 struct kobj_class *mixer_class; 61 62 /* toggle DAC/ADC mute */ 63 void (*mute)(struct a10codec_info *, int, int); 64 65 /* DRQ types */ 66 u_int drqtype_codec; 67 u_int drqtype_sdram; 68 69 /* register map */ 70 bus_size_t DPC, 71 DAC_FIFOC, 72 DAC_FIFOS, 73 DAC_TXDATA, 74 ADC_FIFOC, 75 ADC_FIFOS, 76 ADC_RXDATA, 77 DAC_CNT, 78 ADC_CNT; 79 }; 80 81 #define TX_TRIG_LEVEL 0xf 82 #define RX_TRIG_LEVEL 0x7 83 #define DRQ_CLR_CNT 0x3 84 85 #define AC_DAC_DPC(_sc) ((_sc)->cfg->DPC) 86 #define DAC_DPC_EN_DA 0x80000000 87 #define AC_DAC_FIFOC(_sc) ((_sc)->cfg->DAC_FIFOC) 88 #define DAC_FIFOC_FS_SHIFT 29 89 #define DAC_FIFOC_FS_MASK (7U << DAC_FIFOC_FS_SHIFT) 90 #define DAC_FS_48KHZ 0 91 #define DAC_FS_32KHZ 1 92 #define DAC_FS_24KHZ 2 93 #define DAC_FS_16KHZ 3 94 #define DAC_FS_12KHZ 4 95 #define DAC_FS_8KHZ 5 96 #define DAC_FS_192KHZ 6 97 #define DAC_FS_96KHZ 7 98 #define DAC_FIFOC_FIFO_MODE_SHIFT 24 99 #define DAC_FIFOC_FIFO_MODE_MASK (3U << DAC_FIFOC_FIFO_MODE_SHIFT) 100 #define FIFO_MODE_24_31_8 0 101 #define FIFO_MODE_16_31_16 0 102 #define FIFO_MODE_16_15_0 1 103 #define DAC_FIFOC_DRQ_CLR_CNT_SHIFT 21 104 #define DAC_FIFOC_DRQ_CLR_CNT_MASK (3U << DAC_FIFOC_DRQ_CLR_CNT_SHIFT) 105 #define DAC_FIFOC_TX_TRIG_LEVEL_SHIFT 8 106 #define DAC_FIFOC_TX_TRIG_LEVEL_MASK (0x7f << DAC_FIFOC_TX_TRIG_LEVEL_SHIFT) 107 #define DAC_FIFOC_MONO_EN (1U << 6) 108 #define DAC_FIFOC_TX_BITS (1U << 5) 109 #define DAC_FIFOC_DRQ_EN (1U << 4) 110 #define DAC_FIFOC_FIFO_FLUSH (1U << 0) 111 #define AC_DAC_FIFOS(_sc) ((_sc)->cfg->DAC_FIFOS) 112 #define AC_DAC_TXDATA(_sc) ((_sc)->cfg->DAC_TXDATA) 113 #define AC_ADC_FIFOC(_sc) ((_sc)->cfg->ADC_FIFOC) 114 #define ADC_FIFOC_FS_SHIFT 29 115 #define ADC_FIFOC_FS_MASK (7U << ADC_FIFOC_FS_SHIFT) 116 #define ADC_FS_48KHZ 0 117 #define ADC_FIFOC_EN_AD (1U << 28) 118 #define ADC_FIFOC_RX_FIFO_MODE (1U << 24) 119 #define ADC_FIFOC_RX_TRIG_LEVEL_SHIFT 8 120 #define ADC_FIFOC_RX_TRIG_LEVEL_MASK (0x1f << ADC_FIFOC_RX_TRIG_LEVEL_SHIFT) 121 #define ADC_FIFOC_MONO_EN (1U << 7) 122 #define ADC_FIFOC_RX_BITS (1U << 6) 123 #define ADC_FIFOC_DRQ_EN (1U << 4) 124 #define ADC_FIFOC_FIFO_FLUSH (1U << 1) 125 #define AC_ADC_FIFOS(_sc) ((_sc)->cfg->ADC_FIFOS) 126 #define AC_ADC_RXDATA(_sc) ((_sc)->cfg->ADC_RXDATA) 127 #define AC_DAC_CNT(_sc) ((_sc)->cfg->DAC_CNT) 128 #define AC_ADC_CNT(_sc) ((_sc)->cfg->ADC_CNT) 129 130 static uint32_t a10codec_fmt[] = { 131 SND_FORMAT(AFMT_S16_LE, 1, 0), 132 SND_FORMAT(AFMT_S16_LE, 2, 0), 133 0 134 }; 135 136 static struct pcmchan_caps a10codec_pcaps = { 8000, 192000, a10codec_fmt, 0 }; 137 static struct pcmchan_caps a10codec_rcaps = { 8000, 48000, a10codec_fmt, 0 }; 138 139 struct a10codec_info; 140 141 struct a10codec_chinfo { 142 struct snd_dbuf *buffer; 143 struct pcm_channel *channel; 144 struct a10codec_info *parent; 145 bus_dmamap_t dmamap; 146 void *dmaaddr; 147 bus_addr_t physaddr; 148 bus_size_t fifo; 149 device_t dmac; 150 void *dmachan; 151 152 int dir; 153 int run; 154 uint32_t pos; 155 uint32_t format; 156 uint32_t blocksize; 157 uint32_t speed; 158 }; 159 160 struct a10codec_info { 161 device_t dev; 162 struct resource *res[2]; 163 struct mtx *lock; 164 bus_dma_tag_t dmat; 165 unsigned dmasize; 166 void *ih; 167 168 struct a10codec_config *cfg; 169 170 struct a10codec_chinfo play; 171 struct a10codec_chinfo rec; 172 }; 173 174 static struct resource_spec a10codec_spec[] = { 175 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 176 { -1, 0 } 177 }; 178 179 #define CODEC_ANALOG_READ(sc, reg) bus_read_4((sc)->res[1], (reg)) 180 #define CODEC_ANALOG_WRITE(sc, reg, val) bus_write_4((sc)->res[1], (reg), (val)) 181 182 #define CODEC_READ(sc, reg) bus_read_4((sc)->res[0], (reg)) 183 #define CODEC_WRITE(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val)) 184 185 /* 186 * A10/A20 mixer interface 187 */ 188 189 #define A10_DAC_ACTL 0x10 190 #define A10_DACAREN (1U << 31) 191 #define A10_DACALEN (1U << 30) 192 #define A10_MIXEN (1U << 29) 193 #define A10_DACPAS (1U << 8) 194 #define A10_PAMUTE (1U << 6) 195 #define A10_PAVOL_SHIFT 0 196 #define A10_PAVOL_MASK (0x3f << A10_PAVOL_SHIFT) 197 #define A10_ADC_ACTL 0x28 198 #define A10_ADCREN (1U << 31) 199 #define A10_ADCLEN (1U << 30) 200 #define A10_PREG1EN (1U << 29) 201 #define A10_PREG2EN (1U << 28) 202 #define A10_VMICEN (1U << 27) 203 #define A10_ADCG_SHIFT 20 204 #define A10_ADCG_MASK (7U << A10_ADCG_SHIFT) 205 #define A10_ADCIS_SHIFT 17 206 #define A10_ADCIS_MASK (7U << A10_ADCIS_SHIFT) 207 #define A10_ADC_IS_LINEIN 0 208 #define A10_ADC_IS_FMIN 1 209 #define A10_ADC_IS_MIC1 2 210 #define A10_ADC_IS_MIC2 3 211 #define A10_ADC_IS_MIC1_L_MIC2_R 4 212 #define A10_ADC_IS_MIC1_LR_MIC2_LR 5 213 #define A10_ADC_IS_OMIX 6 214 #define A10_ADC_IS_LINEIN_L_MIC1_R 7 215 #define A10_LNRDF (1U << 16) 216 #define A10_LNPREG_SHIFT 13 217 #define A10_LNPREG_MASK (7U << A10_LNPREG_SHIFT) 218 #define A10_PA_EN (1U << 4) 219 #define A10_DDE (1U << 3) 220 221 static int 222 a10_mixer_init(struct snd_mixer *m) 223 { 224 struct a10codec_info *sc = mix_getdevinfo(m); 225 uint32_t val; 226 227 mix_setdevs(m, SOUND_MASK_VOLUME | SOUND_MASK_LINE | SOUND_MASK_RECLEV); 228 mix_setrecdevs(m, SOUND_MASK_LINE | SOUND_MASK_LINE1 | SOUND_MASK_MIC); 229 230 /* Unmute input source to PA */ 231 val = CODEC_READ(sc, A10_DAC_ACTL); 232 val |= A10_PAMUTE; 233 CODEC_WRITE(sc, A10_DAC_ACTL, val); 234 235 /* Enable PA */ 236 val = CODEC_READ(sc, A10_ADC_ACTL); 237 val |= A10_PA_EN; 238 CODEC_WRITE(sc, A10_ADC_ACTL, val); 239 240 return (0); 241 } 242 243 static const struct a10_mixer { 244 unsigned reg; 245 unsigned mask; 246 unsigned shift; 247 } a10_mixers[SOUND_MIXER_NRDEVICES] = { 248 [SOUND_MIXER_VOLUME] = { A10_DAC_ACTL, A10_PAVOL_MASK, 249 A10_PAVOL_SHIFT }, 250 [SOUND_MIXER_LINE] = { A10_ADC_ACTL, A10_LNPREG_MASK, 251 A10_LNPREG_SHIFT }, 252 [SOUND_MIXER_RECLEV] = { A10_ADC_ACTL, A10_ADCG_MASK, 253 A10_ADCG_SHIFT }, 254 }; 255 256 static int 257 a10_mixer_set(struct snd_mixer *m, unsigned dev, unsigned left, 258 unsigned right) 259 { 260 struct a10codec_info *sc = mix_getdevinfo(m); 261 uint32_t val; 262 unsigned nvol, max; 263 264 max = a10_mixers[dev].mask >> a10_mixers[dev].shift; 265 nvol = (left * max) / 100; 266 267 val = CODEC_READ(sc, a10_mixers[dev].reg); 268 val &= ~a10_mixers[dev].mask; 269 val |= (nvol << a10_mixers[dev].shift); 270 CODEC_WRITE(sc, a10_mixers[dev].reg, val); 271 272 left = right = (left * 100) / max; 273 return (left | (right << 8)); 274 } 275 276 static uint32_t 277 a10_mixer_setrecsrc(struct snd_mixer *m, uint32_t src) 278 { 279 struct a10codec_info *sc = mix_getdevinfo(m); 280 uint32_t val; 281 282 val = CODEC_READ(sc, A10_ADC_ACTL); 283 284 switch (src) { 285 case SOUND_MASK_LINE: /* line-in */ 286 val &= ~A10_ADCIS_MASK; 287 val |= (A10_ADC_IS_LINEIN << A10_ADCIS_SHIFT); 288 break; 289 case SOUND_MASK_MIC: /* MIC1 */ 290 val &= ~A10_ADCIS_MASK; 291 val |= (A10_ADC_IS_MIC1 << A10_ADCIS_SHIFT); 292 break; 293 case SOUND_MASK_LINE1: /* MIC2 */ 294 val &= ~A10_ADCIS_MASK; 295 val |= (A10_ADC_IS_MIC2 << A10_ADCIS_SHIFT); 296 break; 297 default: 298 break; 299 } 300 301 CODEC_WRITE(sc, A10_ADC_ACTL, val); 302 303 switch ((val & A10_ADCIS_MASK) >> A10_ADCIS_SHIFT) { 304 case A10_ADC_IS_LINEIN: 305 return (SOUND_MASK_LINE); 306 case A10_ADC_IS_MIC1: 307 return (SOUND_MASK_MIC); 308 case A10_ADC_IS_MIC2: 309 return (SOUND_MASK_LINE1); 310 default: 311 return (0); 312 } 313 } 314 315 static void 316 a10_mute(struct a10codec_info *sc, int mute, int dir) 317 { 318 uint32_t val; 319 320 if (dir == PCMDIR_PLAY) { 321 val = CODEC_READ(sc, A10_DAC_ACTL); 322 if (mute) { 323 /* Disable DAC analog l/r channels and output mixer */ 324 val &= ~A10_DACAREN; 325 val &= ~A10_DACALEN; 326 val &= ~A10_DACPAS; 327 } else { 328 /* Enable DAC analog l/r channels and output mixer */ 329 val |= A10_DACAREN; 330 val |= A10_DACALEN; 331 val |= A10_DACPAS; 332 } 333 CODEC_WRITE(sc, A10_DAC_ACTL, val); 334 } else { 335 val = CODEC_READ(sc, A10_ADC_ACTL); 336 if (mute) { 337 /* Disable ADC analog l/r channels, MIC1 preamp, 338 * and VMIC pin voltage 339 */ 340 val &= ~A10_ADCREN; 341 val &= ~A10_ADCLEN; 342 val &= ~A10_PREG1EN; 343 val &= ~A10_VMICEN; 344 } else { 345 /* Enable ADC analog l/r channels, MIC1 preamp, 346 * and VMIC pin voltage 347 */ 348 val |= A10_ADCREN; 349 val |= A10_ADCLEN; 350 val |= A10_PREG1EN; 351 val |= A10_VMICEN; 352 } 353 CODEC_WRITE(sc, A10_ADC_ACTL, val); 354 } 355 } 356 357 static kobj_method_t a10_mixer_methods[] = { 358 KOBJMETHOD(mixer_init, a10_mixer_init), 359 KOBJMETHOD(mixer_set, a10_mixer_set), 360 KOBJMETHOD(mixer_setrecsrc, a10_mixer_setrecsrc), 361 KOBJMETHOD_END 362 }; 363 MIXER_DECLARE(a10_mixer); 364 365 /* 366 * H3 mixer interface 367 */ 368 369 #define H3_PR_CFG 0x00 370 #define H3_AC_PR_RST (1 << 28) 371 #define H3_AC_PR_RW (1 << 24) 372 #define H3_AC_PR_ADDR_SHIFT 16 373 #define H3_AC_PR_ADDR_MASK (0x1f << H3_AC_PR_ADDR_SHIFT) 374 #define H3_ACDA_PR_WDAT_SHIFT 8 375 #define H3_ACDA_PR_WDAT_MASK (0xff << H3_ACDA_PR_WDAT_SHIFT) 376 #define H3_ACDA_PR_RDAT_SHIFT 0 377 #define H3_ACDA_PR_RDAT_MASK (0xff << H3_ACDA_PR_RDAT_SHIFT) 378 379 #define H3_LOMIXSC 0x01 380 #define H3_LOMIXSC_LDAC (1 << 1) 381 #define H3_ROMIXSC 0x02 382 #define H3_ROMIXSC_RDAC (1 << 1) 383 #define H3_DAC_PA_SRC 0x03 384 #define H3_DACAREN (1 << 7) 385 #define H3_DACALEN (1 << 6) 386 #define H3_RMIXEN (1 << 5) 387 #define H3_LMIXEN (1 << 4) 388 #define H3_LINEIN_GCTR 0x05 389 #define H3_LINEING_SHIFT 4 390 #define H3_LINEING_MASK (0x7 << H3_LINEING_SHIFT) 391 #define H3_MIC_GCTR 0x06 392 #define H3_MIC1_GAIN_SHIFT 4 393 #define H3_MIC1_GAIN_MASK (0x7 << H3_MIC1_GAIN_SHIFT) 394 #define H3_MIC2_GAIN_SHIFT 0 395 #define H3_MIC2_GAIN_MASK (0x7 << H3_MIC2_GAIN_SHIFT) 396 #define H3_PAEN_CTR 0x07 397 #define H3_LINEOUTEN (1 << 7) 398 #define H3_LINEOUT_VOLC 0x09 399 #define H3_LINEOUTVOL_SHIFT 3 400 #define H3_LINEOUTVOL_MASK (0x1f << H3_LINEOUTVOL_SHIFT) 401 #define H3_MIC2G_LINEOUT_CTR 0x0a 402 #define H3_LINEOUT_LSEL (1 << 3) 403 #define H3_LINEOUT_RSEL (1 << 2) 404 #define H3_LADCMIXSC 0x0c 405 #define H3_RADCMIXSC 0x0d 406 #define H3_ADCMIXSC_MIC1 (1 << 6) 407 #define H3_ADCMIXSC_MIC2 (1 << 5) 408 #define H3_ADCMIXSC_LINEIN (1 << 2) 409 #define H3_ADCMIXSC_OMIXER (3 << 0) 410 #define H3_ADC_AP_EN 0x0f 411 #define H3_ADCREN (1 << 7) 412 #define H3_ADCLEN (1 << 6) 413 #define H3_ADCG_SHIFT 0 414 #define H3_ADCG_MASK (0x7 << H3_ADCG_SHIFT) 415 416 static u_int 417 h3_pr_read(struct a10codec_info *sc, u_int addr) 418 { 419 uint32_t val; 420 421 /* Read current value */ 422 val = CODEC_ANALOG_READ(sc, H3_PR_CFG); 423 424 /* De-assert reset */ 425 val |= H3_AC_PR_RST; 426 CODEC_ANALOG_WRITE(sc, H3_PR_CFG, val); 427 428 /* Read mode */ 429 val &= ~H3_AC_PR_RW; 430 CODEC_ANALOG_WRITE(sc, H3_PR_CFG, val); 431 432 /* Set address */ 433 val &= ~H3_AC_PR_ADDR_MASK; 434 val |= (addr << H3_AC_PR_ADDR_SHIFT); 435 CODEC_ANALOG_WRITE(sc, H3_PR_CFG, val); 436 437 /* Read data */ 438 return (CODEC_ANALOG_READ(sc , H3_PR_CFG) & H3_ACDA_PR_RDAT_MASK); 439 } 440 441 static void 442 h3_pr_write(struct a10codec_info *sc, u_int addr, u_int data) 443 { 444 uint32_t val; 445 446 /* Read current value */ 447 val = CODEC_ANALOG_READ(sc, H3_PR_CFG); 448 449 /* De-assert reset */ 450 val |= H3_AC_PR_RST; 451 CODEC_ANALOG_WRITE(sc, H3_PR_CFG, val); 452 453 /* Set address */ 454 val &= ~H3_AC_PR_ADDR_MASK; 455 val |= (addr << H3_AC_PR_ADDR_SHIFT); 456 CODEC_ANALOG_WRITE(sc, H3_PR_CFG, val); 457 458 /* Write data */ 459 val &= ~H3_ACDA_PR_WDAT_MASK; 460 val |= (data << H3_ACDA_PR_WDAT_SHIFT); 461 CODEC_ANALOG_WRITE(sc, H3_PR_CFG, val); 462 463 /* Write mode */ 464 val |= H3_AC_PR_RW; 465 CODEC_ANALOG_WRITE(sc, H3_PR_CFG, val); 466 } 467 468 static void 469 h3_pr_set_clear(struct a10codec_info *sc, u_int addr, u_int set, u_int clr) 470 { 471 u_int old, new; 472 473 old = h3_pr_read(sc, addr); 474 new = set | (old & ~clr); 475 h3_pr_write(sc, addr, new); 476 } 477 478 static int 479 h3_mixer_init(struct snd_mixer *m) 480 { 481 int rid=1; 482 pcell_t reg[2]; 483 phandle_t analogref; 484 struct a10codec_info *sc = mix_getdevinfo(m); 485 486 if (OF_getencprop(ofw_bus_get_node(sc->dev), "allwinner,codec-analog-controls", 487 &analogref, sizeof(analogref)) <= 0) { 488 return (ENXIO); 489 } 490 491 if (OF_getencprop(OF_node_from_xref(analogref), "reg", 492 reg, sizeof(reg)) <= 0) { 493 return (ENXIO); 494 } 495 496 sc->res[1] = bus_alloc_resource(sc->dev, SYS_RES_MEMORY, &rid, reg[0], 497 reg[0]+reg[1], reg[1], RF_ACTIVE ); 498 499 if (sc->res[1] == NULL) { 500 return (ENXIO); 501 } 502 503 mix_setdevs(m, SOUND_MASK_PCM | SOUND_MASK_VOLUME | SOUND_MASK_RECLEV | 504 SOUND_MASK_MIC | SOUND_MASK_LINE | SOUND_MASK_LINE1); 505 mix_setrecdevs(m, SOUND_MASK_MIC | SOUND_MASK_LINE | SOUND_MASK_LINE1 | 506 SOUND_MASK_IMIX); 507 508 pcm_setflags(sc->dev, pcm_getflags(sc->dev) | SD_F_SOFTPCMVOL); 509 510 /* Right & Left LINEOUT enable */ 511 h3_pr_set_clear(sc, H3_PAEN_CTR, H3_LINEOUTEN, 0); 512 h3_pr_set_clear(sc, H3_MIC2G_LINEOUT_CTR, 513 H3_LINEOUT_LSEL | H3_LINEOUT_RSEL, 0); 514 515 return (0); 516 } 517 518 static const struct h3_mixer { 519 unsigned reg; 520 unsigned mask; 521 unsigned shift; 522 } h3_mixers[SOUND_MIXER_NRDEVICES] = { 523 [SOUND_MIXER_VOLUME] = { H3_LINEOUT_VOLC, H3_LINEOUTVOL_MASK, 524 H3_LINEOUTVOL_SHIFT }, 525 [SOUND_MIXER_RECLEV] = { H3_ADC_AP_EN, H3_ADCG_MASK, 526 H3_ADCG_SHIFT }, 527 [SOUND_MIXER_LINE] = { H3_LINEIN_GCTR, H3_LINEING_MASK, 528 H3_LINEING_SHIFT }, 529 [SOUND_MIXER_MIC] = { H3_MIC_GCTR, H3_MIC1_GAIN_MASK, 530 H3_MIC1_GAIN_SHIFT }, 531 [SOUND_MIXER_LINE1] = { H3_MIC_GCTR, H3_MIC2_GAIN_MASK, 532 H3_MIC2_GAIN_SHIFT }, 533 }; 534 535 static int 536 h3_mixer_set(struct snd_mixer *m, unsigned dev, unsigned left, 537 unsigned right) 538 { 539 struct a10codec_info *sc = mix_getdevinfo(m); 540 unsigned nvol, max; 541 542 max = h3_mixers[dev].mask >> h3_mixers[dev].shift; 543 nvol = (left * max) / 100; 544 545 h3_pr_set_clear(sc, h3_mixers[dev].reg, 546 nvol << h3_mixers[dev].shift, h3_mixers[dev].mask); 547 548 left = right = (left * 100) / max; 549 return (left | (right << 8)); 550 } 551 552 static uint32_t 553 h3_mixer_setrecsrc(struct snd_mixer *m, uint32_t src) 554 { 555 struct a10codec_info *sc = mix_getdevinfo(m); 556 uint32_t val; 557 558 val = 0; 559 src &= (SOUND_MASK_LINE | SOUND_MASK_MIC | 560 SOUND_MASK_LINE1 | SOUND_MASK_IMIX); 561 562 if ((src & SOUND_MASK_LINE) != 0) /* line-in */ 563 val |= H3_ADCMIXSC_LINEIN; 564 if ((src & SOUND_MASK_MIC) != 0) /* MIC1 */ 565 val |= H3_ADCMIXSC_MIC1; 566 if ((src & SOUND_MASK_LINE1) != 0) /* MIC2 */ 567 val |= H3_ADCMIXSC_MIC2; 568 if ((src & SOUND_MASK_IMIX) != 0) /* l/r output mixer */ 569 val |= H3_ADCMIXSC_OMIXER; 570 571 h3_pr_write(sc, H3_LADCMIXSC, val); 572 h3_pr_write(sc, H3_RADCMIXSC, val); 573 574 return (src); 575 } 576 577 static void 578 h3_mute(struct a10codec_info *sc, int mute, int dir) 579 { 580 if (dir == PCMDIR_PLAY) { 581 if (mute) { 582 /* Mute DAC l/r channels to output mixer */ 583 h3_pr_set_clear(sc, H3_LOMIXSC, 0, H3_LOMIXSC_LDAC); 584 h3_pr_set_clear(sc, H3_ROMIXSC, 0, H3_ROMIXSC_RDAC); 585 /* Disable DAC analog l/r channels and output mixer */ 586 h3_pr_set_clear(sc, H3_DAC_PA_SRC, 587 0, H3_DACAREN | H3_DACALEN | H3_RMIXEN | H3_LMIXEN); 588 } else { 589 /* Enable DAC analog l/r channels and output mixer */ 590 h3_pr_set_clear(sc, H3_DAC_PA_SRC, 591 H3_DACAREN | H3_DACALEN | H3_RMIXEN | H3_LMIXEN, 0); 592 /* Unmute DAC l/r channels to output mixer */ 593 h3_pr_set_clear(sc, H3_LOMIXSC, H3_LOMIXSC_LDAC, 0); 594 h3_pr_set_clear(sc, H3_ROMIXSC, H3_ROMIXSC_RDAC, 0); 595 } 596 } else { 597 if (mute) { 598 /* Disable ADC analog l/r channels */ 599 h3_pr_set_clear(sc, H3_ADC_AP_EN, 600 0, H3_ADCREN | H3_ADCLEN); 601 } else { 602 /* Enable ADC analog l/r channels */ 603 h3_pr_set_clear(sc, H3_ADC_AP_EN, 604 H3_ADCREN | H3_ADCLEN, 0); 605 } 606 } 607 } 608 609 static kobj_method_t h3_mixer_methods[] = { 610 KOBJMETHOD(mixer_init, h3_mixer_init), 611 KOBJMETHOD(mixer_set, h3_mixer_set), 612 KOBJMETHOD(mixer_setrecsrc, h3_mixer_setrecsrc), 613 KOBJMETHOD_END 614 }; 615 MIXER_DECLARE(h3_mixer); 616 617 /* 618 * Channel interface 619 */ 620 621 static void 622 a10codec_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 623 { 624 struct a10codec_chinfo *ch = arg; 625 626 if (error != 0) 627 return; 628 629 ch->physaddr = segs[0].ds_addr; 630 } 631 632 static void 633 a10codec_transfer(struct a10codec_chinfo *ch) 634 { 635 bus_addr_t src, dst; 636 int error; 637 638 if (ch->dir == PCMDIR_PLAY) { 639 src = ch->physaddr + ch->pos; 640 dst = ch->fifo; 641 } else { 642 src = ch->fifo; 643 dst = ch->physaddr + ch->pos; 644 } 645 646 error = SUNXI_DMA_TRANSFER(ch->dmac, ch->dmachan, src, dst, 647 ch->blocksize); 648 if (error) { 649 ch->run = 0; 650 device_printf(ch->parent->dev, "DMA transfer failed: %d\n", 651 error); 652 } 653 } 654 655 static void 656 a10codec_dmaconfig(struct a10codec_chinfo *ch) 657 { 658 struct a10codec_info *sc = ch->parent; 659 struct sunxi_dma_config conf; 660 661 memset(&conf, 0, sizeof(conf)); 662 conf.src_width = conf.dst_width = 16; 663 conf.src_burst_len = conf.dst_burst_len = 4; 664 665 if (ch->dir == PCMDIR_PLAY) { 666 conf.dst_noincr = true; 667 conf.src_drqtype = sc->cfg->drqtype_sdram; 668 conf.dst_drqtype = sc->cfg->drqtype_codec; 669 } else { 670 conf.src_noincr = true; 671 conf.src_drqtype = sc->cfg->drqtype_codec; 672 conf.dst_drqtype = sc->cfg->drqtype_sdram; 673 } 674 675 SUNXI_DMA_SET_CONFIG(ch->dmac, ch->dmachan, &conf); 676 } 677 678 static void 679 a10codec_dmaintr(void *priv) 680 { 681 struct a10codec_chinfo *ch = priv; 682 unsigned bufsize; 683 684 bufsize = sndbuf_getsize(ch->buffer); 685 686 ch->pos += ch->blocksize; 687 if (ch->pos >= bufsize) 688 ch->pos -= bufsize; 689 690 if (ch->run) { 691 chn_intr(ch->channel); 692 a10codec_transfer(ch); 693 } 694 } 695 696 static unsigned 697 a10codec_fs(struct a10codec_chinfo *ch) 698 { 699 switch (ch->speed) { 700 case 48000: 701 return (DAC_FS_48KHZ); 702 case 24000: 703 return (DAC_FS_24KHZ); 704 case 12000: 705 return (DAC_FS_12KHZ); 706 case 192000: 707 return (DAC_FS_192KHZ); 708 case 32000: 709 return (DAC_FS_32KHZ); 710 case 16000: 711 return (DAC_FS_16KHZ); 712 case 8000: 713 return (DAC_FS_8KHZ); 714 case 96000: 715 return (DAC_FS_96KHZ); 716 default: 717 return (DAC_FS_48KHZ); 718 } 719 } 720 721 static void 722 a10codec_start(struct a10codec_chinfo *ch) 723 { 724 struct a10codec_info *sc = ch->parent; 725 uint32_t val; 726 727 ch->pos = 0; 728 729 if (ch->dir == PCMDIR_PLAY) { 730 /* Flush DAC FIFO */ 731 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), DAC_FIFOC_FIFO_FLUSH); 732 733 /* Clear DAC FIFO status */ 734 CODEC_WRITE(sc, AC_DAC_FIFOS(sc), 735 CODEC_READ(sc, AC_DAC_FIFOS(sc))); 736 737 /* Unmute output */ 738 sc->cfg->mute(sc, 0, ch->dir); 739 740 /* Configure DAC DMA channel */ 741 a10codec_dmaconfig(ch); 742 743 /* Configure DAC FIFO */ 744 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), 745 (AFMT_CHANNEL(ch->format) == 1 ? DAC_FIFOC_MONO_EN : 0) | 746 (a10codec_fs(ch) << DAC_FIFOC_FS_SHIFT) | 747 (FIFO_MODE_16_15_0 << DAC_FIFOC_FIFO_MODE_SHIFT) | 748 (DRQ_CLR_CNT << DAC_FIFOC_DRQ_CLR_CNT_SHIFT) | 749 (TX_TRIG_LEVEL << DAC_FIFOC_TX_TRIG_LEVEL_SHIFT)); 750 751 /* Enable DAC DRQ */ 752 val = CODEC_READ(sc, AC_DAC_FIFOC(sc)); 753 val |= DAC_FIFOC_DRQ_EN; 754 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), val); 755 } else { 756 /* Flush ADC FIFO */ 757 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), ADC_FIFOC_FIFO_FLUSH); 758 759 /* Clear ADC FIFO status */ 760 CODEC_WRITE(sc, AC_ADC_FIFOS(sc), 761 CODEC_READ(sc, AC_ADC_FIFOS(sc))); 762 763 /* Unmute input */ 764 sc->cfg->mute(sc, 0, ch->dir); 765 766 /* Configure ADC DMA channel */ 767 a10codec_dmaconfig(ch); 768 769 /* Configure ADC FIFO */ 770 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), 771 ADC_FIFOC_EN_AD | 772 ADC_FIFOC_RX_FIFO_MODE | 773 (AFMT_CHANNEL(ch->format) == 1 ? ADC_FIFOC_MONO_EN : 0) | 774 (a10codec_fs(ch) << ADC_FIFOC_FS_SHIFT) | 775 (RX_TRIG_LEVEL << ADC_FIFOC_RX_TRIG_LEVEL_SHIFT)); 776 777 /* Enable ADC DRQ */ 778 val = CODEC_READ(sc, AC_ADC_FIFOC(sc)); 779 val |= ADC_FIFOC_DRQ_EN; 780 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), val); 781 } 782 783 /* Start DMA transfer */ 784 a10codec_transfer(ch); 785 } 786 787 static void 788 a10codec_stop(struct a10codec_chinfo *ch) 789 { 790 struct a10codec_info *sc = ch->parent; 791 792 /* Disable DMA channel */ 793 SUNXI_DMA_HALT(ch->dmac, ch->dmachan); 794 795 sc->cfg->mute(sc, 1, ch->dir); 796 797 if (ch->dir == PCMDIR_PLAY) { 798 /* Disable DAC DRQ */ 799 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), 0); 800 } else { 801 /* Disable ADC DRQ */ 802 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), 0); 803 } 804 } 805 806 static void * 807 a10codec_chan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, 808 struct pcm_channel *c, int dir) 809 { 810 struct a10codec_info *sc = devinfo; 811 struct a10codec_chinfo *ch = dir == PCMDIR_PLAY ? &sc->play : &sc->rec; 812 phandle_t xref; 813 pcell_t *cells; 814 int ncells, error; 815 816 error = ofw_bus_parse_xref_list_alloc(ofw_bus_get_node(sc->dev), 817 "dmas", "#dma-cells", dir == PCMDIR_PLAY ? 1 : 0, 818 &xref, &ncells, &cells); 819 if (error != 0) { 820 device_printf(sc->dev, "cannot parse 'dmas' property\n"); 821 return (NULL); 822 } 823 OF_prop_free(cells); 824 825 ch->parent = sc; 826 ch->channel = c; 827 ch->buffer = b; 828 ch->dir = dir; 829 ch->fifo = rman_get_start(sc->res[0]) + 830 (dir == PCMDIR_REC ? AC_ADC_RXDATA(sc) : AC_DAC_TXDATA(sc)); 831 832 ch->dmac = OF_device_from_xref(xref); 833 if (ch->dmac == NULL) { 834 device_printf(sc->dev, "cannot find DMA controller\n"); 835 device_printf(sc->dev, "xref = 0x%x\n", (u_int)xref); 836 return (NULL); 837 } 838 ch->dmachan = SUNXI_DMA_ALLOC(ch->dmac, false, a10codec_dmaintr, ch); 839 if (ch->dmachan == NULL) { 840 device_printf(sc->dev, "cannot allocate DMA channel\n"); 841 return (NULL); 842 } 843 844 error = bus_dmamem_alloc(sc->dmat, &ch->dmaaddr, 845 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &ch->dmamap); 846 if (error != 0) { 847 device_printf(sc->dev, "cannot allocate channel buffer\n"); 848 return (NULL); 849 } 850 error = bus_dmamap_load(sc->dmat, ch->dmamap, ch->dmaaddr, 851 sc->dmasize, a10codec_dmamap_cb, ch, BUS_DMA_NOWAIT); 852 if (error != 0) { 853 device_printf(sc->dev, "cannot load DMA map\n"); 854 return (NULL); 855 } 856 memset(ch->dmaaddr, 0, sc->dmasize); 857 858 if (sndbuf_setup(ch->buffer, ch->dmaaddr, sc->dmasize) != 0) { 859 device_printf(sc->dev, "cannot setup sndbuf\n"); 860 return (NULL); 861 } 862 863 return (ch); 864 } 865 866 static int 867 a10codec_chan_free(kobj_t obj, void *data) 868 { 869 struct a10codec_chinfo *ch = data; 870 struct a10codec_info *sc = ch->parent; 871 872 SUNXI_DMA_FREE(ch->dmac, ch->dmachan); 873 bus_dmamap_unload(sc->dmat, ch->dmamap); 874 bus_dmamem_free(sc->dmat, ch->dmaaddr, ch->dmamap); 875 876 return (0); 877 } 878 879 static int 880 a10codec_chan_setformat(kobj_t obj, void *data, uint32_t format) 881 { 882 struct a10codec_chinfo *ch = data; 883 884 ch->format = format; 885 886 return (0); 887 } 888 889 static uint32_t 890 a10codec_chan_setspeed(kobj_t obj, void *data, uint32_t speed) 891 { 892 struct a10codec_chinfo *ch = data; 893 894 /* 895 * The codec supports full duplex operation but both DAC and ADC 896 * use the same source clock (PLL2). Limit the available speeds to 897 * those supported by a 24576000 Hz input. 898 */ 899 switch (speed) { 900 case 8000: 901 case 12000: 902 case 16000: 903 case 24000: 904 case 32000: 905 case 48000: 906 ch->speed = speed; 907 break; 908 case 96000: 909 case 192000: 910 /* 96 KHz / 192 KHz mode only supported for playback */ 911 if (ch->dir == PCMDIR_PLAY) { 912 ch->speed = speed; 913 } else { 914 ch->speed = 48000; 915 } 916 break; 917 case 44100: 918 ch->speed = 48000; 919 break; 920 case 22050: 921 ch->speed = 24000; 922 break; 923 case 11025: 924 ch->speed = 12000; 925 break; 926 default: 927 ch->speed = 48000; 928 break; 929 } 930 931 return (ch->speed); 932 } 933 934 static uint32_t 935 a10codec_chan_setblocksize(kobj_t obj, void *data, uint32_t blocksize) 936 { 937 struct a10codec_chinfo *ch = data; 938 939 ch->blocksize = blocksize & ~3; 940 941 return (ch->blocksize); 942 } 943 944 static int 945 a10codec_chan_trigger(kobj_t obj, void *data, int go) 946 { 947 struct a10codec_chinfo *ch = data; 948 struct a10codec_info *sc = ch->parent; 949 950 if (!PCMTRIG_COMMON(go)) 951 return (0); 952 953 snd_mtxlock(sc->lock); 954 switch (go) { 955 case PCMTRIG_START: 956 ch->run = 1; 957 a10codec_stop(ch); 958 a10codec_start(ch); 959 break; 960 case PCMTRIG_STOP: 961 case PCMTRIG_ABORT: 962 ch->run = 0; 963 a10codec_stop(ch); 964 break; 965 default: 966 break; 967 } 968 snd_mtxunlock(sc->lock); 969 970 return (0); 971 } 972 973 static uint32_t 974 a10codec_chan_getptr(kobj_t obj, void *data) 975 { 976 struct a10codec_chinfo *ch = data; 977 978 return (ch->pos); 979 } 980 981 static struct pcmchan_caps * 982 a10codec_chan_getcaps(kobj_t obj, void *data) 983 { 984 struct a10codec_chinfo *ch = data; 985 986 if (ch->dir == PCMDIR_PLAY) { 987 return (&a10codec_pcaps); 988 } else { 989 return (&a10codec_rcaps); 990 } 991 } 992 993 static kobj_method_t a10codec_chan_methods[] = { 994 KOBJMETHOD(channel_init, a10codec_chan_init), 995 KOBJMETHOD(channel_free, a10codec_chan_free), 996 KOBJMETHOD(channel_setformat, a10codec_chan_setformat), 997 KOBJMETHOD(channel_setspeed, a10codec_chan_setspeed), 998 KOBJMETHOD(channel_setblocksize, a10codec_chan_setblocksize), 999 KOBJMETHOD(channel_trigger, a10codec_chan_trigger), 1000 KOBJMETHOD(channel_getptr, a10codec_chan_getptr), 1001 KOBJMETHOD(channel_getcaps, a10codec_chan_getcaps), 1002 KOBJMETHOD_END 1003 }; 1004 CHANNEL_DECLARE(a10codec_chan); 1005 1006 /* 1007 * Device interface 1008 */ 1009 1010 static const struct a10codec_config a10_config = { 1011 .mixer_class = &a10_mixer_class, 1012 .mute = a10_mute, 1013 .drqtype_codec = 19, 1014 .drqtype_sdram = 22, 1015 .DPC = 0x00, 1016 .DAC_FIFOC = 0x04, 1017 .DAC_FIFOS = 0x08, 1018 .DAC_TXDATA = 0x0c, 1019 .ADC_FIFOC = 0x1c, 1020 .ADC_FIFOS = 0x20, 1021 .ADC_RXDATA = 0x24, 1022 .DAC_CNT = 0x30, 1023 .ADC_CNT = 0x34, 1024 }; 1025 1026 static const struct a10codec_config h3_config = { 1027 .mixer_class = &h3_mixer_class, 1028 .mute = h3_mute, 1029 .drqtype_codec = 15, 1030 .drqtype_sdram = 1, 1031 .DPC = 0x00, 1032 .DAC_FIFOC = 0x04, 1033 .DAC_FIFOS = 0x08, 1034 .DAC_TXDATA = 0x20, 1035 .ADC_FIFOC = 0x10, 1036 .ADC_FIFOS = 0x14, 1037 .ADC_RXDATA = 0x18, 1038 .DAC_CNT = 0x40, 1039 .ADC_CNT = 0x44, 1040 }; 1041 1042 static struct ofw_compat_data compat_data[] = { 1043 { "allwinner,sun4i-a10-codec", (uintptr_t)&a10_config }, 1044 { "allwinner,sun7i-a20-codec", (uintptr_t)&a10_config }, 1045 { "allwinner,sun8i-h3-codec", (uintptr_t)&h3_config }, 1046 { NULL, 0 } 1047 }; 1048 1049 static int 1050 a10codec_probe(device_t dev) 1051 { 1052 if (!ofw_bus_status_okay(dev)) 1053 return (ENXIO); 1054 1055 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 1056 return (ENXIO); 1057 1058 device_set_desc(dev, "Allwinner Audio Codec"); 1059 return (BUS_PROBE_DEFAULT); 1060 } 1061 1062 static int 1063 a10codec_attach(device_t dev) 1064 { 1065 struct a10codec_info *sc; 1066 char status[SND_STATUSLEN]; 1067 struct gpiobus_pin *pa_pin; 1068 phandle_t node; 1069 clk_t clk_bus, clk_codec; 1070 hwreset_t rst; 1071 uint32_t val; 1072 int error; 1073 1074 node = ofw_bus_get_node(dev); 1075 1076 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); 1077 sc->cfg = (void *)ofw_bus_search_compatible(dev, compat_data)->ocd_data; 1078 sc->dev = dev; 1079 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "a10codec softc"); 1080 1081 if (bus_alloc_resources(dev, a10codec_spec, sc->res)) { 1082 device_printf(dev, "cannot allocate resources for device\n"); 1083 error = ENXIO; 1084 goto fail; 1085 } 1086 1087 sc->dmasize = 131072; 1088 error = bus_dma_tag_create( 1089 bus_get_dma_tag(dev), 1090 4, sc->dmasize, /* alignment, boundary */ 1091 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1092 BUS_SPACE_MAXADDR, /* highaddr */ 1093 NULL, NULL, /* filter, filterarg */ 1094 sc->dmasize, 1, /* maxsize, nsegs */ 1095 sc->dmasize, 0, /* maxsegsize, flags */ 1096 NULL, NULL, /* lockfunc, lockarg */ 1097 &sc->dmat); 1098 if (error != 0) { 1099 device_printf(dev, "cannot create DMA tag\n"); 1100 goto fail; 1101 } 1102 1103 /* Get clocks */ 1104 if (clk_get_by_ofw_name(dev, 0, "apb", &clk_bus) != 0 && 1105 clk_get_by_ofw_name(dev, 0, "ahb", &clk_bus) != 0) { 1106 device_printf(dev, "cannot find bus clock\n"); 1107 goto fail; 1108 } 1109 if (clk_get_by_ofw_name(dev, 0, "codec", &clk_codec) != 0) { 1110 device_printf(dev, "cannot find codec clock\n"); 1111 goto fail; 1112 } 1113 1114 /* Gating bus clock for codec */ 1115 if (clk_enable(clk_bus) != 0) { 1116 device_printf(dev, "cannot enable bus clock\n"); 1117 goto fail; 1118 } 1119 /* Activate audio codec clock. According to the A10 and A20 user 1120 * manuals, Audio_pll can be either 24.576MHz or 22.5792MHz. Most 1121 * audio sampling rates require an 24.576MHz input clock with the 1122 * exception of 44.1kHz, 22.05kHz, and 11.025kHz. Unfortunately, 1123 * both capture and playback use the same clock source so to 1124 * safely support independent full duplex operation, we use a fixed 1125 * 24.576MHz clock source and don't advertise native support for 1126 * the three sampling rates that require a 22.5792MHz input. 1127 */ 1128 error = clk_set_freq(clk_codec, 24576000, CLK_SET_ROUND_DOWN); 1129 if (error != 0) { 1130 device_printf(dev, "cannot set codec clock frequency\n"); 1131 goto fail; 1132 } 1133 /* Enable audio codec clock */ 1134 error = clk_enable(clk_codec); 1135 if (error != 0) { 1136 device_printf(dev, "cannot enable codec clock\n"); 1137 goto fail; 1138 } 1139 1140 /* De-assert hwreset */ 1141 if (hwreset_get_by_ofw_idx(dev, 0, 0, &rst) == 0) { 1142 error = hwreset_deassert(rst); 1143 if (error != 0) { 1144 device_printf(dev, "cannot de-assert reset\n"); 1145 goto fail; 1146 } 1147 } 1148 1149 /* Enable DAC */ 1150 val = CODEC_READ(sc, AC_DAC_DPC(sc)); 1151 val |= DAC_DPC_EN_DA; 1152 CODEC_WRITE(sc, AC_DAC_DPC(sc), val); 1153 1154 if (mixer_init(dev, sc->cfg->mixer_class, sc)) { 1155 device_printf(dev, "mixer_init failed\n"); 1156 goto fail; 1157 } 1158 1159 /* Unmute PA */ 1160 if (gpio_pin_get_by_ofw_property(dev, node, "allwinner,pa-gpios", 1161 &pa_pin) == 0) { 1162 error = gpio_pin_set_active(pa_pin, 1); 1163 if (error != 0) 1164 device_printf(dev, "failed to unmute PA\n"); 1165 } 1166 1167 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE); 1168 1169 if (pcm_register(dev, sc, 1, 1)) { 1170 device_printf(dev, "pcm_register failed\n"); 1171 goto fail; 1172 } 1173 1174 pcm_addchan(dev, PCMDIR_PLAY, &a10codec_chan_class, sc); 1175 pcm_addchan(dev, PCMDIR_REC, &a10codec_chan_class, sc); 1176 1177 snprintf(status, SND_STATUSLEN, "at %s", ofw_bus_get_name(dev)); 1178 pcm_setstatus(dev, status); 1179 1180 return (0); 1181 1182 fail: 1183 bus_release_resources(dev, a10codec_spec, sc->res); 1184 snd_mtxfree(sc->lock); 1185 free(sc, M_DEVBUF); 1186 1187 return (ENXIO); 1188 } 1189 1190 static device_method_t a10codec_pcm_methods[] = { 1191 /* Device interface */ 1192 DEVMETHOD(device_probe, a10codec_probe), 1193 DEVMETHOD(device_attach, a10codec_attach), 1194 1195 DEVMETHOD_END 1196 }; 1197 1198 static driver_t a10codec_pcm_driver = { 1199 "pcm", 1200 a10codec_pcm_methods, 1201 PCM_SOFTC_SIZE, 1202 }; 1203 1204 DRIVER_MODULE(a10codec, simplebus, a10codec_pcm_driver, 0, 0); 1205 MODULE_DEPEND(a10codec, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1206 MODULE_VERSION(a10codec, 1); 1207