1 /*- 2 * Copyright (c) 2014-2015 M. Warner Losh <imp@freebsd.org> 3 * Copyright (c) 2015 Luiz Otavio O Souza <loos@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * The magic-bit-bang sequence used in this code may be based on a linux 28 * platform driver in the Allwinner SDK from Allwinner Technology Co., Ltd. 29 * www.allwinnertech.com, by Daniel Wang <danielwang@allwinnertech.com> 30 * though none of the original code was copied. 31 */ 32 33 #include "opt_bus.h" 34 35 #include <sys/cdefs.h> 36 __FBSDID("$FreeBSD$"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/bus.h> 41 #include <sys/rman.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 45 #include <machine/bus.h> 46 #include <dev/ofw/ofw_bus.h> 47 #include <dev/ofw/ofw_bus_subr.h> 48 49 #include <dev/ahci/ahci.h> 50 #include <arm/allwinner/a10_clk.h> 51 52 /* 53 * Allwinner a1x/a2x/a8x SATA attachment. This is just the AHCI register 54 * set with a few extra implementation-specific registers that need to 55 * be accounted for. There's only one PHY in the system, and it needs 56 * to be trained to bring the link up. In addition, there's some DMA 57 * specific things that need to be done as well. These things are also 58 * just about completely undocumented, except in ugly code in the Linux 59 * SDK Allwinner releases. 60 */ 61 62 /* BITx -- Unknown bit that needs to be set/cleared at position x */ 63 /* UFx -- Uknown multi-bit field frobbed during init */ 64 #define AHCI_BISTAFR 0x00A0 65 #define AHCI_BISTCR 0x00A4 66 #define AHCI_BISTFCTR 0x00A8 67 #define AHCI_BISTSR 0x00AC 68 #define AHCI_BISTDECR 0x00B0 69 #define AHCI_DIAGNR 0x00B4 70 #define AHCI_DIAGNR1 0x00B8 71 #define AHCI_OOBR 0x00BC 72 #define AHCI_PHYCS0R 0x00C0 73 /* Bits 0..17 are a mystery */ 74 #define PHYCS0R_BIT18 (1 << 18) 75 #define PHYCS0R_POWER_ENABLE (1 << 19) 76 #define PHYCS0R_UF1_MASK (7 << 20) /* Unknown Field 1 */ 77 #define PHYCS0R_UF1_INIT (3 << 20) 78 #define PHYCS0R_BIT23 (1 << 23) 79 #define PHYCS0R_UF2_MASK (7 << 24) /* Uknown Field 2 */ 80 #define PHYCS0R_UF2_INIT (5 << 24) 81 /* Bit 27 mystery */ 82 #define PHYCS0R_POWER_STATUS_MASK (7 << 28) 83 #define PHYCS0R_PS_GOOD (2 << 28) 84 /* Bit 31 mystery */ 85 #define AHCI_PHYCS1R 0x00C4 86 /* Bits 0..5 are a mystery */ 87 #define PHYCS1R_UF1_MASK (3 << 6) 88 #define PHYCS1R_UF1_INIT (2 << 6) 89 #define PHYCS1R_UF2_MASK (0x1f << 8) 90 #define PHYCS1R_UF2_INIT (6 << 8) 91 /* Bits 13..14 are a mystery */ 92 #define PHYCS1R_BIT15 (1 << 15) 93 #define PHYCS1R_UF3_MASK (3 << 16) 94 #define PHYCS1R_UF3_INIT (2 << 16) 95 /* Bit 18 mystery */ 96 #define PHYCS1R_HIGHZ (1 << 19) 97 /* Bits 20..27 mystery */ 98 #define PHYCS1R_BIT28 (1 << 28) 99 /* Bits 29..31 mystery */ 100 #define AHCI_PHYCS2R 0x00C8 101 /* bits 0..4 mystery */ 102 #define PHYCS2R_UF1_MASK (0x1f << 5) 103 #define PHYCS2R_UF1_INIT (0x19 << 5) 104 /* Bits 10..23 mystery */ 105 #define PHYCS2R_CALIBRATE (1 << 24) 106 /* Bits 25..31 mystery */ 107 #define AHCI_TIMER1MS 0x00E0 108 #define AHCI_GPARAM1R 0x00E8 109 #define AHCI_GPARAM2R 0x00EC 110 #define AHCI_PPARAMR 0x00F0 111 #define AHCI_TESTR 0x00F4 112 #define AHCI_VERSIONR 0x00F8 113 #define AHCI_IDR 0x00FC 114 #define AHCI_RWCR 0x00FC 115 116 #define AHCI_P0DMACR 0x0070 117 #define AHCI_P0PHYCR 0x0078 118 #define AHCI_P0PHYSR 0x007C 119 120 static void inline 121 ahci_set(struct resource *m, bus_size_t off, uint32_t set) 122 { 123 uint32_t val = ATA_INL(m, off); 124 125 val |= set; 126 ATA_OUTL(m, off, val); 127 } 128 129 static void inline 130 ahci_clr(struct resource *m, bus_size_t off, uint32_t clr) 131 { 132 uint32_t val = ATA_INL(m, off); 133 134 val &= ~clr; 135 ATA_OUTL(m, off, val); 136 } 137 138 static void inline 139 ahci_mask_set(struct resource *m, bus_size_t off, uint32_t mask, uint32_t set) 140 { 141 uint32_t val = ATA_INL(m, off); 142 143 val &= mask; 144 val |= set; 145 ATA_OUTL(m, off, val); 146 } 147 148 /* 149 * Should this be phy_reset or phy_init 150 */ 151 #define PHY_RESET_TIMEOUT 1000 152 static void 153 ahci_a10_phy_reset(device_t dev) 154 { 155 uint32_t to, val; 156 struct ahci_controller *ctlr = device_get_softc(dev); 157 158 /* 159 * Here start the the magic -- most of the comments are based 160 * on guesswork, names of routines and printf error 161 * messages. The code works, but it will do that even if the 162 * comments are 100% BS. 163 */ 164 165 /* 166 * Lock out other access while we initialize. Or at least that 167 * seems to be the case based on Linux SDK #defines. Maybe this 168 * put things into reset? 169 */ 170 ATA_OUTL(ctlr->r_mem, AHCI_RWCR, 0); 171 DELAY(100); 172 173 /* 174 * Set bit 19 in PHYCS1R. Guessing this disables driving the PHY 175 * port for a bit while we reset things. 176 */ 177 ahci_set(ctlr->r_mem, AHCI_PHYCS1R, PHYCS1R_HIGHZ); 178 179 /* 180 * Frob PHYCS0R... 181 */ 182 ahci_mask_set(ctlr->r_mem, AHCI_PHYCS0R, 183 ~PHYCS0R_UF2_MASK, 184 PHYCS0R_UF2_INIT | PHYCS0R_BIT23 | PHYCS0R_BIT18); 185 186 /* 187 * Set three fields in PHYCS1R 188 */ 189 ahci_mask_set(ctlr->r_mem, AHCI_PHYCS1R, 190 ~(PHYCS1R_UF1_MASK | PHYCS1R_UF2_MASK | PHYCS1R_UF3_MASK), 191 PHYCS1R_UF1_INIT | PHYCS1R_UF2_INIT | PHYCS1R_UF3_INIT); 192 193 /* 194 * Two more mystery bits in PHYCS1R. -- can these be combined above? 195 */ 196 ahci_set(ctlr->r_mem, AHCI_PHYCS1R, PHYCS1R_BIT15 | PHYCS1R_BIT28); 197 198 /* 199 * Now clear that first mysery bit. Perhaps this starts 200 * driving the PHY again so we can power it up and start 201 * talking to the SATA drive, if any below. 202 */ 203 ahci_clr(ctlr->r_mem, AHCI_PHYCS1R, PHYCS1R_HIGHZ); 204 205 /* 206 * Frob PHYCS0R again... 207 */ 208 ahci_mask_set(ctlr->r_mem, AHCI_PHYCS0R, 209 ~PHYCS0R_UF1_MASK, PHYCS0R_UF1_INIT); 210 211 /* 212 * Frob PHYCS2R, because 25 means something? 213 */ 214 ahci_mask_set(ctlr->r_mem, AHCI_PHYCS2R, ~PHYCS2R_UF1_MASK, 215 PHYCS2R_UF1_INIT); 216 217 DELAY(100); /* WAG */ 218 219 /* 220 * Turn on the power to the PHY and wait for it to report back 221 * good? 222 */ 223 ahci_set(ctlr->r_mem, AHCI_PHYCS0R, PHYCS0R_POWER_ENABLE); 224 for (to = PHY_RESET_TIMEOUT; to > 0; to--) { 225 val = ATA_INL(ctlr->r_mem, AHCI_PHYCS0R); 226 if ((val & PHYCS0R_POWER_STATUS_MASK) == PHYCS0R_PS_GOOD) 227 break; 228 DELAY(10); 229 } 230 if (to == 0 && bootverbose) 231 device_printf(dev, "PHY Power Failed PHYCS0R = %#x\n", val); 232 233 /* 234 * Calibrate the clocks between the device and the host. This appears 235 * to be an automated process that clears the bit when it is done. 236 */ 237 ahci_set(ctlr->r_mem, AHCI_PHYCS2R, PHYCS2R_CALIBRATE); 238 for (to = PHY_RESET_TIMEOUT; to > 0; to--) { 239 val = ATA_INL(ctlr->r_mem, AHCI_PHYCS2R); 240 if ((val & PHYCS2R_CALIBRATE) == 0) 241 break; 242 DELAY(10); 243 } 244 if (to == 0 && bootverbose) 245 device_printf(dev, "PHY Cal Failed PHYCS2R %#x\n", val); 246 247 /* 248 * OK, let things settle down a bit. 249 */ 250 DELAY(1000); 251 252 /* 253 * Go back into normal mode now that we've calibrated the PHY. 254 */ 255 ATA_OUTL(ctlr->r_mem, AHCI_RWCR, 7); 256 } 257 258 static void 259 ahci_a10_ch_start(struct ahci_channel *ch) 260 { 261 uint32_t reg; 262 263 /* 264 * Magical values from Allwinner SDK, setup the DMA before start 265 * operations on this channel. 266 */ 267 reg = ATA_INL(ch->r_mem, AHCI_P0DMACR); 268 reg &= ~0xff00; 269 reg |= 0x4400; 270 ATA_OUTL(ch->r_mem, AHCI_P0DMACR, reg); 271 } 272 273 static int 274 ahci_a10_ctlr_reset(device_t dev) 275 { 276 277 ahci_a10_phy_reset(dev); 278 279 return (ahci_ctlr_reset(dev)); 280 } 281 282 static int 283 ahci_a10_probe(device_t dev) 284 { 285 286 if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-a10-ahci")) 287 return (ENXIO); 288 device_set_desc(dev, "Allwinner Integrated AHCI controller"); 289 290 return (BUS_PROBE_DEFAULT); 291 } 292 293 static int 294 ahci_a10_attach(device_t dev) 295 { 296 int error; 297 struct ahci_controller *ctlr; 298 299 ctlr = device_get_softc(dev); 300 ctlr->quirks = AHCI_Q_NOPMP; 301 ctlr->vendorid = 0; 302 ctlr->deviceid = 0; 303 ctlr->subvendorid = 0; 304 ctlr->subdeviceid = 0; 305 ctlr->r_rid = 0; 306 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 307 &ctlr->r_rid, RF_ACTIVE))) 308 return (ENXIO); 309 310 /* Turn on the PLL for SATA */ 311 a10_clk_ahci_activate(); 312 313 /* Reset controller */ 314 if ((error = ahci_a10_ctlr_reset(dev)) != 0) { 315 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, 316 ctlr->r_mem); 317 return (error); 318 }; 319 320 /* 321 * No MSI registers on this platform. 322 */ 323 ctlr->msi = 0; 324 ctlr->numirqs = 1; 325 326 /* Channel start callback(). */ 327 ctlr->ch_start = ahci_a10_ch_start; 328 329 /* 330 * Note: ahci_attach will release ctlr->r_mem on errors automatically 331 */ 332 return (ahci_attach(dev)); 333 } 334 335 static int 336 ahci_a10_detach(device_t dev) 337 { 338 339 return (ahci_detach(dev)); 340 } 341 342 devclass_t ahci_devclass; 343 344 static device_method_t ahci_ata_methods[] = { 345 DEVMETHOD(device_probe, ahci_a10_probe), 346 DEVMETHOD(device_attach, ahci_a10_attach), 347 DEVMETHOD(device_detach, ahci_a10_detach), 348 DEVMETHOD(bus_print_child, ahci_print_child), 349 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 350 DEVMETHOD(bus_release_resource, ahci_release_resource), 351 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 352 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 353 DEVMETHOD(bus_child_location_str, ahci_child_location_str), 354 DEVMETHOD_END 355 }; 356 357 static driver_t ahci_ata_driver = { 358 "ahci", 359 ahci_ata_methods, 360 sizeof(struct ahci_controller) 361 }; 362 363 DRIVER_MODULE(ahci, simplebus, ahci_ata_driver, ahci_devclass, 0, 0); 364