1 /*- 2 * Copyright (c) 2012 Ganbold Tsagaankhuu <ganbold@freebsd.org> 3 * Copyright (c) 2016 Emmanuel Vadot <manu@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_platform.h" 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/cpuset.h> 36 #include <sys/kernel.h> 37 #include <sys/ktr.h> 38 #include <sys/lock.h> 39 #include <sys/module.h> 40 #include <sys/mutex.h> 41 #include <sys/param.h> 42 #include <sys/pcpu.h> 43 #include <sys/proc.h> 44 #include <sys/rman.h> 45 #include <sys/smp.h> 46 #include <sys/systm.h> 47 #include <sys/sched.h> 48 #include <machine/bus.h> 49 #include <machine/intr.h> 50 51 #include <dev/ofw/openfirm.h> 52 #include <dev/ofw/ofw_bus.h> 53 #include <dev/ofw/ofw_bus_subr.h> 54 55 #include "pic_if.h" 56 57 /** 58 * Interrupt controller registers 59 * 60 */ 61 #define SW_INT_VECTOR_REG 0x00 62 #define SW_INT_BASE_ADR_REG 0x04 63 #define SW_INT_PROTECTION_REG 0x08 64 #define SW_INT_NMI_CTRL_REG 0x0c 65 66 #define SW_INT_IRQ_PENDING_REG0 0x10 67 #define SW_INT_IRQ_PENDING_REG1 0x14 68 #define SW_INT_IRQ_PENDING_REG2 0x18 69 70 #define SW_INT_FIQ_PENDING_REG0 0x20 71 #define SW_INT_FIQ_PENDING_REG1 0x24 72 #define SW_INT_FIQ_PENDING_REG2 0x28 73 74 #define SW_INT_SELECT_REG0 0x30 75 #define SW_INT_SELECT_REG1 0x34 76 #define SW_INT_SELECT_REG2 0x38 77 78 #define SW_INT_ENABLE_REG0 0x40 79 #define SW_INT_ENABLE_REG1 0x44 80 #define SW_INT_ENABLE_REG2 0x48 81 82 #define SW_INT_MASK_REG0 0x50 83 #define SW_INT_MASK_REG1 0x54 84 #define SW_INT_MASK_REG2 0x58 85 86 #define SW_INT_IRQNO_ENMI 0 87 88 #define A10_INTR_MAX_NIRQS 81 89 90 #define SW_INT_IRQ_PENDING_REG(_b) (0x10 + ((_b) * 4)) 91 #define SW_INT_FIQ_PENDING_REG(_b) (0x20 + ((_b) * 4)) 92 #define SW_INT_SELECT_REG(_b) (0x30 + ((_b) * 4)) 93 #define SW_INT_ENABLE_REG(_b) (0x40 + ((_b) * 4)) 94 #define SW_INT_MASK_REG(_b) (0x50 + ((_b) * 4)) 95 96 struct a10_intr_irqsrc { 97 struct intr_irqsrc isrc; 98 u_int irq; 99 }; 100 101 struct a10_aintc_softc { 102 device_t sc_dev; 103 struct resource * aintc_res; 104 bus_space_tag_t aintc_bst; 105 bus_space_handle_t aintc_bsh; 106 struct mtx mtx; 107 struct a10_intr_irqsrc isrcs[A10_INTR_MAX_NIRQS]; 108 }; 109 110 #define aintc_read_4(sc, reg) \ 111 bus_space_read_4(sc->aintc_bst, sc->aintc_bsh, reg) 112 #define aintc_write_4(sc, reg, val) \ 113 bus_space_write_4(sc->aintc_bst, sc->aintc_bsh, reg, val) 114 115 static __inline void 116 a10_intr_eoi(struct a10_aintc_softc *sc, u_int irq) 117 { 118 119 if (irq != SW_INT_IRQNO_ENMI) 120 return; 121 mtx_lock_spin(&sc->mtx); 122 aintc_write_4(sc, SW_INT_IRQ_PENDING_REG(0), 123 (1 << SW_INT_IRQNO_ENMI)); 124 mtx_unlock_spin(&sc->mtx); 125 } 126 127 static void 128 a10_intr_unmask(struct a10_aintc_softc *sc, u_int irq) 129 { 130 uint32_t bit, block, value; 131 132 bit = (irq % 32); 133 block = (irq / 32); 134 135 mtx_lock_spin(&sc->mtx); 136 value = aintc_read_4(sc, SW_INT_ENABLE_REG(block)); 137 value |= (1 << bit); 138 aintc_write_4(sc, SW_INT_ENABLE_REG(block), value); 139 140 value = aintc_read_4(sc, SW_INT_MASK_REG(block)); 141 value &= ~(1 << bit); 142 aintc_write_4(sc, SW_INT_MASK_REG(block), value); 143 mtx_unlock_spin(&sc->mtx); 144 } 145 146 static void 147 a10_intr_mask(struct a10_aintc_softc *sc, u_int irq) 148 { 149 uint32_t bit, block, value; 150 151 bit = (irq % 32); 152 block = (irq / 32); 153 154 mtx_lock_spin(&sc->mtx); 155 value = aintc_read_4(sc, SW_INT_ENABLE_REG(block)); 156 value &= ~(1 << bit); 157 aintc_write_4(sc, SW_INT_ENABLE_REG(block), value); 158 159 value = aintc_read_4(sc, SW_INT_MASK_REG(block)); 160 value |= (1 << bit); 161 aintc_write_4(sc, SW_INT_MASK_REG(block), value); 162 mtx_unlock_spin(&sc->mtx); 163 } 164 165 static int 166 a10_pending_irq(struct a10_aintc_softc *sc) 167 { 168 uint32_t value; 169 int i, b; 170 171 for (i = 0; i < 3; i++) { 172 value = aintc_read_4(sc, SW_INT_IRQ_PENDING_REG(i)); 173 if (value == 0) 174 continue; 175 for (b = 0; b < 32; b++) 176 if (value & (1 << b)) { 177 return (i * 32 + b); 178 } 179 } 180 181 return (-1); 182 } 183 184 static int 185 a10_intr(void *arg) 186 { 187 struct a10_aintc_softc *sc = arg; 188 u_int irq; 189 190 irq = a10_pending_irq(sc); 191 if (irq == -1 || irq > A10_INTR_MAX_NIRQS) { 192 device_printf(sc->sc_dev, "Spurious interrupt %d\n", irq); 193 return (FILTER_HANDLED); 194 } 195 196 while (irq != -1) { 197 if (irq > A10_INTR_MAX_NIRQS) { 198 device_printf(sc->sc_dev, "Spurious interrupt %d\n", 199 irq); 200 return (FILTER_HANDLED); 201 } 202 if (intr_isrc_dispatch(&sc->isrcs[irq].isrc, 203 curthread->td_intr_frame) != 0) { 204 a10_intr_mask(sc, irq); 205 a10_intr_eoi(sc, irq); 206 device_printf(sc->sc_dev, 207 "Stray interrupt %d disabled\n", irq); 208 } 209 210 arm_irq_memory_barrier(irq); 211 irq = a10_pending_irq(sc); 212 } 213 214 return (FILTER_HANDLED); 215 } 216 217 static int 218 a10_intr_pic_attach(struct a10_aintc_softc *sc) 219 { 220 struct intr_pic *pic; 221 int error; 222 uint32_t irq; 223 const char *name; 224 intptr_t xref; 225 226 name = device_get_nameunit(sc->sc_dev); 227 for (irq = 0; irq < A10_INTR_MAX_NIRQS; irq++) { 228 sc->isrcs[irq].irq = irq; 229 230 error = intr_isrc_register(&sc->isrcs[irq].isrc, 231 sc->sc_dev, 0, "%s,%u", name, irq); 232 if (error != 0) 233 return (error); 234 } 235 236 xref = OF_xref_from_node(ofw_bus_get_node(sc->sc_dev)); 237 pic = intr_pic_register(sc->sc_dev, xref); 238 if (pic == NULL) 239 return (ENXIO); 240 241 return (intr_pic_claim_root(sc->sc_dev, xref, a10_intr, sc, 0)); 242 } 243 244 static void 245 a10_intr_enable_intr(device_t dev, struct intr_irqsrc *isrc) 246 { 247 struct a10_aintc_softc *sc; 248 u_int irq = ((struct a10_intr_irqsrc *)isrc)->irq; 249 250 sc = device_get_softc(dev); 251 arm_irq_memory_barrier(irq); 252 a10_intr_unmask(sc, irq); 253 } 254 255 static void 256 a10_intr_disable_intr(device_t dev, struct intr_irqsrc *isrc) 257 { 258 struct a10_aintc_softc *sc; 259 u_int irq = ((struct a10_intr_irqsrc *)isrc)->irq; 260 261 sc = device_get_softc(dev); 262 a10_intr_mask(sc, irq); 263 } 264 265 static int 266 a10_intr_map_intr(device_t dev, struct intr_map_data *data, 267 struct intr_irqsrc **isrcp) 268 { 269 struct intr_map_data_fdt *daf; 270 struct a10_aintc_softc *sc; 271 272 if (data->type != INTR_MAP_DATA_FDT) 273 return (ENOTSUP); 274 275 daf = (struct intr_map_data_fdt *)data; 276 if (daf->ncells != 1 || daf->cells[0] >= A10_INTR_MAX_NIRQS) 277 return (EINVAL); 278 279 sc = device_get_softc(dev); 280 *isrcp = &sc->isrcs[daf->cells[0]].isrc; 281 return (0); 282 } 283 284 static void 285 a10_intr_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 286 { 287 struct a10_aintc_softc *sc = device_get_softc(dev); 288 u_int irq = ((struct a10_intr_irqsrc *)isrc)->irq; 289 290 a10_intr_mask(sc, irq); 291 a10_intr_eoi(sc, irq); 292 } 293 294 static void 295 a10_intr_post_ithread(device_t dev, struct intr_irqsrc *isrc) 296 { 297 298 a10_intr_enable_intr(dev, isrc); 299 } 300 301 static void 302 a10_intr_post_filter(device_t dev, struct intr_irqsrc *isrc) 303 { 304 struct a10_aintc_softc *sc = device_get_softc(dev); 305 u_int irq = ((struct a10_intr_irqsrc *)isrc)->irq; 306 307 a10_intr_eoi(sc, irq); 308 } 309 310 static int 311 a10_aintc_probe(device_t dev) 312 { 313 314 if (!ofw_bus_status_okay(dev)) 315 return (ENXIO); 316 317 if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-a10-ic")) 318 return (ENXIO); 319 device_set_desc(dev, "A10 AINTC Interrupt Controller"); 320 return (BUS_PROBE_DEFAULT); 321 } 322 323 static int 324 a10_aintc_attach(device_t dev) 325 { 326 struct a10_aintc_softc *sc = device_get_softc(dev); 327 int rid = 0; 328 int i; 329 sc->sc_dev = dev; 330 331 sc->aintc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 332 &rid, RF_ACTIVE); 333 if (!sc->aintc_res) { 334 device_printf(dev, "could not allocate resource\n"); 335 goto error; 336 } 337 338 sc->aintc_bst = rman_get_bustag(sc->aintc_res); 339 sc->aintc_bsh = rman_get_bushandle(sc->aintc_res); 340 341 mtx_init(&sc->mtx, "A10 AINTC lock", "", MTX_SPIN); 342 343 /* Disable & clear all interrupts */ 344 for (i = 0; i < 3; i++) { 345 aintc_write_4(sc, SW_INT_ENABLE_REG(i), 0); 346 aintc_write_4(sc, SW_INT_MASK_REG(i), 0xffffffff); 347 } 348 /* enable protection mode*/ 349 aintc_write_4(sc, SW_INT_PROTECTION_REG, 0x01); 350 351 /* config the external interrupt source type*/ 352 aintc_write_4(sc, SW_INT_NMI_CTRL_REG, 0x00); 353 354 if (a10_intr_pic_attach(sc) != 0) { 355 device_printf(dev, "could not attach PIC\n"); 356 return (ENXIO); 357 } 358 359 return (0); 360 361 error: 362 bus_release_resource(dev, SYS_RES_MEMORY, rid, 363 sc->aintc_res); 364 return (ENXIO); 365 } 366 367 static device_method_t a10_aintc_methods[] = { 368 DEVMETHOD(device_probe, a10_aintc_probe), 369 DEVMETHOD(device_attach, a10_aintc_attach), 370 371 /* Interrupt controller interface */ 372 DEVMETHOD(pic_disable_intr, a10_intr_disable_intr), 373 DEVMETHOD(pic_enable_intr, a10_intr_enable_intr), 374 DEVMETHOD(pic_map_intr, a10_intr_map_intr), 375 DEVMETHOD(pic_post_filter, a10_intr_post_filter), 376 DEVMETHOD(pic_post_ithread, a10_intr_post_ithread), 377 DEVMETHOD(pic_pre_ithread, a10_intr_pre_ithread), 378 379 { 0, 0 } 380 }; 381 382 static driver_t a10_aintc_driver = { 383 "aintc", 384 a10_aintc_methods, 385 sizeof(struct a10_aintc_softc), 386 }; 387 388 static devclass_t a10_aintc_devclass; 389 390 EARLY_DRIVER_MODULE(aintc, simplebus, a10_aintc_driver, a10_aintc_devclass, 0, 0, 391 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_FIRST); 392