1 /*- 2 * Copyright (c) 2012 Ganbold Tsagaankhuu <ganbold@freebsd.org> 3 * Copyright (c) 2016 Emmanuel Vadot <manu@bidouilliste.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_platform.h" 32 33 #include <sys/types.h> 34 #include <sys/bus.h> 35 #include <sys/cpuset.h> 36 #include <sys/kernel.h> 37 #include <sys/ktr.h> 38 #include <sys/module.h> 39 #include <sys/mutex.h> 40 #include <sys/param.h> 41 #include <sys/pcpu.h> 42 #include <sys/proc.h> 43 #include <sys/rman.h> 44 #include <sys/smp.h> 45 #include <sys/systm.h> 46 #ifdef INTRNG 47 #include <sys/sched.h> 48 #endif 49 #include <machine/bus.h> 50 #include <machine/intr.h> 51 52 #include <dev/fdt/fdt_common.h> 53 #include <dev/ofw/openfirm.h> 54 #include <dev/ofw/ofw_bus.h> 55 #include <dev/ofw/ofw_bus_subr.h> 56 57 #ifdef INTRNG 58 #include "pic_if.h" 59 #endif 60 61 /** 62 * Interrupt controller registers 63 * 64 */ 65 #define SW_INT_VECTOR_REG 0x00 66 #define SW_INT_BASE_ADR_REG 0x04 67 #define SW_INT_PROTECTION_REG 0x08 68 #define SW_INT_NMI_CTRL_REG 0x0c 69 70 #define SW_INT_IRQ_PENDING_REG0 0x10 71 #define SW_INT_IRQ_PENDING_REG1 0x14 72 #define SW_INT_IRQ_PENDING_REG2 0x18 73 74 #define SW_INT_FIQ_PENDING_REG0 0x20 75 #define SW_INT_FIQ_PENDING_REG1 0x24 76 #define SW_INT_FIQ_PENDING_REG2 0x28 77 78 #define SW_INT_SELECT_REG0 0x30 79 #define SW_INT_SELECT_REG1 0x34 80 #define SW_INT_SELECT_REG2 0x38 81 82 #define SW_INT_ENABLE_REG0 0x40 83 #define SW_INT_ENABLE_REG1 0x44 84 #define SW_INT_ENABLE_REG2 0x48 85 86 #define SW_INT_MASK_REG0 0x50 87 #define SW_INT_MASK_REG1 0x54 88 #define SW_INT_MASK_REG2 0x58 89 90 #define SW_INT_IRQNO_ENMI 0 91 92 #define A10_INTR_MAX_NIRQS 81 93 94 #define SW_INT_IRQ_PENDING_REG(_b) (0x10 + ((_b) * 4)) 95 #define SW_INT_FIQ_PENDING_REG(_b) (0x20 + ((_b) * 4)) 96 #define SW_INT_SELECT_REG(_b) (0x30 + ((_b) * 4)) 97 #define SW_INT_ENABLE_REG(_b) (0x40 + ((_b) * 4)) 98 #define SW_INT_MASK_REG(_b) (0x50 + ((_b) * 4)) 99 100 #ifdef INTRNG 101 struct a10_intr_irqsrc { 102 struct intr_irqsrc isrc; 103 u_int irq; 104 }; 105 #endif 106 107 struct a10_aintc_softc { 108 device_t sc_dev; 109 struct resource * aintc_res; 110 bus_space_tag_t aintc_bst; 111 bus_space_handle_t aintc_bsh; 112 struct mtx mtx; 113 #ifdef INTRNG 114 struct a10_intr_irqsrc isrcs[A10_INTR_MAX_NIRQS]; 115 #endif 116 }; 117 118 #define aintc_read_4(sc, reg) \ 119 bus_space_read_4(sc->aintc_bst, sc->aintc_bsh, reg) 120 #define aintc_write_4(sc, reg, val) \ 121 bus_space_write_4(sc->aintc_bst, sc->aintc_bsh, reg, val) 122 123 static __inline void 124 a10_intr_eoi(struct a10_aintc_softc *sc, u_int irq) 125 { 126 127 if (irq != SW_INT_IRQNO_ENMI) 128 return; 129 mtx_lock_spin(&sc->mtx); 130 aintc_write_4(sc, SW_INT_IRQ_PENDING_REG(0), 131 (1 << SW_INT_IRQNO_ENMI)); 132 mtx_unlock_spin(&sc->mtx); 133 } 134 135 static void 136 a10_intr_unmask(struct a10_aintc_softc *sc, u_int irq) 137 { 138 uint32_t bit, block, value; 139 140 bit = (irq % 32); 141 block = (irq / 32); 142 143 mtx_lock_spin(&sc->mtx); 144 value = aintc_read_4(sc, SW_INT_ENABLE_REG(block)); 145 value |= (1 << bit); 146 aintc_write_4(sc, SW_INT_ENABLE_REG(block), value); 147 148 value = aintc_read_4(sc, SW_INT_MASK_REG(block)); 149 value &= ~(1 << bit); 150 aintc_write_4(sc, SW_INT_MASK_REG(block), value); 151 mtx_unlock_spin(&sc->mtx); 152 } 153 154 static void 155 a10_intr_mask(struct a10_aintc_softc *sc, u_int irq) 156 { 157 uint32_t bit, block, value; 158 159 bit = (irq % 32); 160 block = (irq / 32); 161 162 mtx_lock_spin(&sc->mtx); 163 value = aintc_read_4(sc, SW_INT_ENABLE_REG(block)); 164 value &= ~(1 << bit); 165 aintc_write_4(sc, SW_INT_ENABLE_REG(block), value); 166 167 value = aintc_read_4(sc, SW_INT_MASK_REG(block)); 168 value |= (1 << bit); 169 aintc_write_4(sc, SW_INT_MASK_REG(block), value); 170 mtx_unlock_spin(&sc->mtx); 171 } 172 173 static int 174 a10_pending_irq(struct a10_aintc_softc *sc) 175 { 176 uint32_t value; 177 int i, b; 178 179 for (i = 0; i < 3; i++) { 180 value = aintc_read_4(sc, SW_INT_IRQ_PENDING_REG(i)); 181 if (value == 0) 182 continue; 183 for (b = 0; b < 32; b++) 184 if (value & (1 << b)) { 185 return (i * 32 + b); 186 } 187 } 188 189 return (-1); 190 } 191 192 #ifndef INTRNG 193 194 static struct a10_aintc_softc *a10_aintc_sc = NULL; 195 196 int 197 arm_get_next_irq(int last_irq) 198 { 199 return (a10_pending_irq(a10_aintc_sc)); 200 } 201 202 void 203 arm_mask_irq(uintptr_t irq) 204 { 205 a10_intr_mask(a10_aintc_sc, irq); 206 } 207 208 void 209 arm_unmask_irq(uintptr_t irq) 210 { 211 a10_intr_unmask(a10_aintc_sc, irq); 212 a10_intr_eoi(a10_aintc_sc, irq); 213 } 214 215 #else /* INTRNG */ 216 217 static int 218 a10_intr(void *arg) 219 { 220 struct a10_aintc_softc *sc = arg; 221 u_int irq; 222 223 irq = a10_pending_irq(sc); 224 if (irq == -1 || irq > A10_INTR_MAX_NIRQS) { 225 device_printf(sc->sc_dev, "Spurious interrupt %d\n", irq); 226 return (FILTER_HANDLED); 227 } 228 229 while (irq != -1) { 230 if (irq > A10_INTR_MAX_NIRQS) { 231 device_printf(sc->sc_dev, "Spurious interrupt %d\n", 232 irq); 233 return (FILTER_HANDLED); 234 } 235 if (intr_isrc_dispatch(&sc->isrcs[irq].isrc, 236 curthread->td_intr_frame) != 0) { 237 a10_intr_mask(sc, irq); 238 a10_intr_eoi(sc, irq); 239 device_printf(sc->sc_dev, 240 "Stray interrupt %d disabled\n", irq); 241 } 242 243 arm_irq_memory_barrier(irq); 244 irq = a10_pending_irq(sc); 245 } 246 247 return (FILTER_HANDLED); 248 } 249 250 static int 251 a10_intr_pic_attach(struct a10_aintc_softc *sc) 252 { 253 int error; 254 uint32_t irq; 255 const char *name; 256 intptr_t xref; 257 258 name = device_get_nameunit(sc->sc_dev); 259 for (irq = 0; irq < A10_INTR_MAX_NIRQS; irq++) { 260 sc->isrcs[irq].irq = irq; 261 262 error = intr_isrc_register(&sc->isrcs[irq].isrc, 263 sc->sc_dev, 0, "%s,%u", name, irq); 264 if (error != 0) 265 return (error); 266 } 267 268 xref = OF_xref_from_node(ofw_bus_get_node(sc->sc_dev)); 269 error = intr_pic_register(sc->sc_dev, xref); 270 if (error != 0) 271 return (error); 272 273 return (intr_pic_claim_root(sc->sc_dev, xref, a10_intr, sc, 0)); 274 } 275 276 static void 277 a10_intr_enable_intr(device_t dev, struct intr_irqsrc *isrc) 278 { 279 struct a10_aintc_softc *sc; 280 u_int irq = ((struct a10_intr_irqsrc *)isrc)->irq; 281 282 sc = device_get_softc(dev); 283 arm_irq_memory_barrier(irq); 284 a10_intr_unmask(sc, irq); 285 } 286 287 static void 288 a10_intr_disable_intr(device_t dev, struct intr_irqsrc *isrc) 289 { 290 struct a10_aintc_softc *sc; 291 u_int irq = ((struct a10_intr_irqsrc *)isrc)->irq; 292 293 sc = device_get_softc(dev); 294 a10_intr_mask(sc, irq); 295 } 296 297 static int 298 a10_intr_map_intr(device_t dev, struct intr_map_data *data, 299 struct intr_irqsrc **isrcp) 300 { 301 struct intr_map_data_fdt *daf; 302 struct a10_aintc_softc *sc; 303 304 if (data->type != INTR_MAP_DATA_FDT) 305 return (ENOTSUP); 306 307 daf = (struct intr_map_data_fdt *)data; 308 if (daf->ncells != 1 || daf->cells[0] >= A10_INTR_MAX_NIRQS) 309 return (EINVAL); 310 311 sc = device_get_softc(dev); 312 *isrcp = &sc->isrcs[daf->cells[0]].isrc; 313 return (0); 314 } 315 316 static void 317 a10_intr_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 318 { 319 struct a10_aintc_softc *sc = device_get_softc(dev); 320 u_int irq = ((struct a10_intr_irqsrc *)isrc)->irq; 321 322 a10_intr_mask(sc, irq); 323 a10_intr_eoi(sc, irq); 324 } 325 326 static void 327 a10_intr_post_ithread(device_t dev, struct intr_irqsrc *isrc) 328 { 329 330 a10_intr_enable_intr(dev, isrc); 331 } 332 333 static void 334 a10_intr_post_filter(device_t dev, struct intr_irqsrc *isrc) 335 { 336 struct a10_aintc_softc *sc = device_get_softc(dev); 337 u_int irq = ((struct a10_intr_irqsrc *)isrc)->irq; 338 339 a10_intr_eoi(sc, irq); 340 } 341 342 #endif /* INTRNG */ 343 344 static int 345 a10_aintc_probe(device_t dev) 346 { 347 348 if (!ofw_bus_status_okay(dev)) 349 return (ENXIO); 350 351 if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-a10-ic")) 352 return (ENXIO); 353 device_set_desc(dev, "A10 AINTC Interrupt Controller"); 354 return (BUS_PROBE_DEFAULT); 355 } 356 357 static int 358 a10_aintc_attach(device_t dev) 359 { 360 struct a10_aintc_softc *sc = device_get_softc(dev); 361 int rid = 0; 362 int i; 363 sc->sc_dev = dev; 364 365 #ifndef INTRNG 366 if (a10_aintc_sc) 367 goto error; 368 369 a10_aintc_sc = sc; 370 #endif 371 372 sc->aintc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 373 &rid, RF_ACTIVE); 374 if (!sc->aintc_res) { 375 device_printf(dev, "could not allocate resource\n"); 376 goto error; 377 } 378 379 sc->aintc_bst = rman_get_bustag(sc->aintc_res); 380 sc->aintc_bsh = rman_get_bushandle(sc->aintc_res); 381 382 mtx_init(&sc->mtx, "A10 AINTC lock", "", MTX_SPIN); 383 384 /* Disable & clear all interrupts */ 385 for (i = 0; i < 3; i++) { 386 aintc_write_4(sc, SW_INT_ENABLE_REG(i), 0); 387 aintc_write_4(sc, SW_INT_MASK_REG(i), 0xffffffff); 388 } 389 /* enable protection mode*/ 390 aintc_write_4(sc, SW_INT_PROTECTION_REG, 0x01); 391 392 /* config the external interrupt source type*/ 393 aintc_write_4(sc, SW_INT_NMI_CTRL_REG, 0x00); 394 395 #ifdef INTRNG 396 if (a10_intr_pic_attach(sc) != 0) { 397 device_printf(dev, "could not attach PIC\n"); 398 return (ENXIO); 399 } 400 #endif 401 402 return (0); 403 404 error: 405 bus_release_resource(dev, SYS_RES_MEMORY, rid, 406 sc->aintc_res); 407 return (ENXIO); 408 } 409 410 static device_method_t a10_aintc_methods[] = { 411 DEVMETHOD(device_probe, a10_aintc_probe), 412 DEVMETHOD(device_attach, a10_aintc_attach), 413 #ifdef INTRNG 414 /* Interrupt controller interface */ 415 DEVMETHOD(pic_disable_intr, a10_intr_disable_intr), 416 DEVMETHOD(pic_enable_intr, a10_intr_enable_intr), 417 DEVMETHOD(pic_map_intr, a10_intr_map_intr), 418 DEVMETHOD(pic_post_filter, a10_intr_post_filter), 419 DEVMETHOD(pic_post_ithread, a10_intr_post_ithread), 420 DEVMETHOD(pic_pre_ithread, a10_intr_pre_ithread), 421 #endif 422 { 0, 0 } 423 }; 424 425 static driver_t a10_aintc_driver = { 426 "aintc", 427 a10_aintc_methods, 428 sizeof(struct a10_aintc_softc), 429 }; 430 431 static devclass_t a10_aintc_devclass; 432 433 EARLY_DRIVER_MODULE(aintc, simplebus, a10_aintc_driver, a10_aintc_devclass, 0, 0, 434 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_FIRST); 435