xref: /freebsd/sys/amd64/vmm/x86.c (revision cfd6422a5217410fbd66f7a7a8a64d9d85e61229)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3  *
4  * Copyright (c) 2011 NetApp, Inc.
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  *
28  * $FreeBSD$
29  */
30 
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
33 
34 #include <sys/param.h>
35 #include <sys/pcpu.h>
36 #include <sys/systm.h>
37 #include <sys/sysctl.h>
38 
39 #include <machine/clock.h>
40 #include <machine/cpufunc.h>
41 #include <machine/md_var.h>
42 #include <machine/segments.h>
43 #include <machine/specialreg.h>
44 
45 #include <machine/vmm.h>
46 
47 #include "vmm_host.h"
48 #include "vmm_ktr.h"
49 #include "vmm_util.h"
50 #include "x86.h"
51 
52 SYSCTL_DECL(_hw_vmm);
53 static SYSCTL_NODE(_hw_vmm, OID_AUTO, topology, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
54     NULL);
55 
56 #define	CPUID_VM_HIGH		0x40000000
57 
58 static const char bhyve_id[12] = "bhyve bhyve ";
59 
60 static uint64_t bhyve_xcpuids;
61 SYSCTL_ULONG(_hw_vmm, OID_AUTO, bhyve_xcpuids, CTLFLAG_RW, &bhyve_xcpuids, 0,
62     "Number of times an unknown cpuid leaf was accessed");
63 
64 #if __FreeBSD_version < 1200060	/* Remove after 11 EOL helps MFCing */
65 extern u_int threads_per_core;
66 SYSCTL_UINT(_hw_vmm_topology, OID_AUTO, threads_per_core, CTLFLAG_RDTUN,
67     &threads_per_core, 0, NULL);
68 
69 extern u_int cores_per_package;
70 SYSCTL_UINT(_hw_vmm_topology, OID_AUTO, cores_per_package, CTLFLAG_RDTUN,
71     &cores_per_package, 0, NULL);
72 #endif
73 
74 static int cpuid_leaf_b = 1;
75 SYSCTL_INT(_hw_vmm_topology, OID_AUTO, cpuid_leaf_b, CTLFLAG_RDTUN,
76     &cpuid_leaf_b, 0, NULL);
77 
78 /*
79  * Round up to the next power of two, if necessary, and then take log2.
80  * Returns -1 if argument is zero.
81  */
82 static __inline int
83 log2(u_int x)
84 {
85 
86 	return (fls(x << (1 - powerof2(x))) - 1);
87 }
88 
89 int
90 x86_emulate_cpuid(struct vm *vm, int vcpu_id, uint64_t *rax, uint64_t *rbx,
91     uint64_t *rcx, uint64_t *rdx)
92 {
93 	const struct xsave_limits *limits;
94 	uint64_t cr4;
95 	int error, enable_invpcid, enable_rdpid, enable_rdtscp, level,
96 	    width, x2apic_id;
97 	unsigned int func, regs[4], logical_cpus, param;
98 	enum x2apic_state x2apic_state;
99 	uint16_t cores, maxcpus, sockets, threads;
100 
101 	/*
102 	 * The function of CPUID is controlled through the provided value of
103 	 * %eax (and secondarily %ecx, for certain leaf data).
104 	 */
105 	func = (uint32_t)*rax;
106 	param = (uint32_t)*rcx;
107 
108 	VCPU_CTR2(vm, vcpu_id, "cpuid %#x,%#x", func, param);
109 
110 	/*
111 	 * Requests for invalid CPUID levels should map to the highest
112 	 * available level instead.
113 	 */
114 	if (cpu_exthigh != 0 && func >= 0x80000000) {
115 		if (func > cpu_exthigh)
116 			func = cpu_exthigh;
117 	} else if (func >= 0x40000000) {
118 		if (func > CPUID_VM_HIGH)
119 			func = CPUID_VM_HIGH;
120 	} else if (func > cpu_high) {
121 		func = cpu_high;
122 	}
123 
124 	/*
125 	 * In general the approach used for CPU topology is to
126 	 * advertise a flat topology where all CPUs are packages with
127 	 * no multi-core or SMT.
128 	 */
129 	switch (func) {
130 		/*
131 		 * Pass these through to the guest
132 		 */
133 		case CPUID_0000_0000:
134 		case CPUID_0000_0002:
135 		case CPUID_0000_0003:
136 		case CPUID_8000_0000:
137 		case CPUID_8000_0002:
138 		case CPUID_8000_0003:
139 		case CPUID_8000_0004:
140 		case CPUID_8000_0006:
141 			cpuid_count(func, param, regs);
142 			break;
143 		case CPUID_8000_0008:
144 			cpuid_count(func, param, regs);
145 			if (vmm_is_svm()) {
146 				/*
147 				 * As on Intel (0000_0007:0, EDX), mask out
148 				 * unsupported or unsafe AMD extended features
149 				 * (8000_0008 EBX).
150 				 */
151 				regs[1] &= (AMDFEID_CLZERO | AMDFEID_IRPERF |
152 				    AMDFEID_XSAVEERPTR);
153 
154 				vm_get_topology(vm, &sockets, &cores, &threads,
155 				    &maxcpus);
156 				/*
157 				 * Here, width is ApicIdCoreIdSize, present on
158 				 * at least Family 15h and newer.  It
159 				 * represents the "number of bits in the
160 				 * initial apicid that indicate thread id
161 				 * within a package."
162 				 *
163 				 * Our topo_probe_amd() uses it for
164 				 * pkg_id_shift and other OSes may rely on it.
165 				 */
166 				width = MIN(0xF, log2(threads * cores));
167 				if (width < 0x4)
168 					width = 0;
169 				logical_cpus = MIN(0xFF, threads * cores - 1);
170 				regs[2] = (width << AMDID_COREID_SIZE_SHIFT) | logical_cpus;
171 			}
172 			break;
173 
174 		case CPUID_8000_0001:
175 			cpuid_count(func, param, regs);
176 
177 			/*
178 			 * Hide SVM from guest.
179 			 */
180 			regs[2] &= ~AMDID2_SVM;
181 
182 			/*
183 			 * Don't advertise extended performance counter MSRs
184 			 * to the guest.
185 			 */
186 			regs[2] &= ~AMDID2_PCXC;
187 			regs[2] &= ~AMDID2_PNXC;
188 			regs[2] &= ~AMDID2_PTSCEL2I;
189 
190 			/*
191 			 * Don't advertise Instruction Based Sampling feature.
192 			 */
193 			regs[2] &= ~AMDID2_IBS;
194 
195 			/* NodeID MSR not available */
196 			regs[2] &= ~AMDID2_NODE_ID;
197 
198 			/* Don't advertise the OS visible workaround feature */
199 			regs[2] &= ~AMDID2_OSVW;
200 
201 			/* Hide mwaitx/monitorx capability from the guest */
202 			regs[2] &= ~AMDID2_MWAITX;
203 
204 			/* Advertise RDTSCP if it is enabled. */
205 			error = vm_get_capability(vm, vcpu_id,
206 			    VM_CAP_RDTSCP, &enable_rdtscp);
207 			if (error == 0 && enable_rdtscp)
208 				regs[3] |= AMDID_RDTSCP;
209 			else
210 				regs[3] &= ~AMDID_RDTSCP;
211 			break;
212 
213 		case CPUID_8000_0007:
214 			/*
215 			 * AMD uses this leaf to advertise the processor's
216 			 * power monitoring and RAS capabilities. These
217 			 * features are hardware-specific and exposing
218 			 * them to a guest doesn't make a lot of sense.
219 			 *
220 			 * Intel uses this leaf only to advertise the
221 			 * "Invariant TSC" feature with all other bits
222 			 * being reserved (set to zero).
223 			 */
224 			regs[0] = 0;
225 			regs[1] = 0;
226 			regs[2] = 0;
227 			regs[3] = 0;
228 
229 			/*
230 			 * "Invariant TSC" can be advertised to the guest if:
231 			 * - host TSC frequency is invariant
232 			 * - host TSCs are synchronized across physical cpus
233 			 *
234 			 * XXX This still falls short because the vcpu
235 			 * can observe the TSC moving backwards as it
236 			 * migrates across physical cpus. But at least
237 			 * it should discourage the guest from using the
238 			 * TSC to keep track of time.
239 			 */
240 			if (tsc_is_invariant && smp_tsc)
241 				regs[3] |= AMDPM_TSC_INVARIANT;
242 			break;
243 
244 		case CPUID_8000_001D:
245 			/* AMD Cache topology, like 0000_0004 for Intel. */
246 			if (!vmm_is_svm())
247 				goto default_leaf;
248 
249 			/*
250 			 * Similar to Intel, generate a ficticious cache
251 			 * topology for the guest with L3 shared by the
252 			 * package, and L1 and L2 local to a core.
253 			 */
254 			vm_get_topology(vm, &sockets, &cores, &threads,
255 			    &maxcpus);
256 			switch (param) {
257 			case 0:
258 				logical_cpus = threads;
259 				level = 1;
260 				func = 1;	/* data cache */
261 				break;
262 			case 1:
263 				logical_cpus = threads;
264 				level = 2;
265 				func = 3;	/* unified cache */
266 				break;
267 			case 2:
268 				logical_cpus = threads * cores;
269 				level = 3;
270 				func = 3;	/* unified cache */
271 				break;
272 			default:
273 				logical_cpus = 0;
274 				level = 0;
275 				func = 0;
276 				break;
277 			}
278 
279 			logical_cpus = MIN(0xfff, logical_cpus - 1);
280 			regs[0] = (logical_cpus << 14) | (1 << 8) |
281 			    (level << 5) | func;
282 			regs[1] = (func > 0) ? (CACHE_LINE_SIZE - 1) : 0;
283 			regs[2] = 0;
284 			regs[3] = 0;
285 			break;
286 
287 		case CPUID_8000_001E:
288 			/*
289 			 * AMD Family 16h+ and Hygon Family 18h additional
290 			 * identifiers.
291 			 */
292 			if (!vmm_is_svm() || CPUID_TO_FAMILY(cpu_id) < 0x16)
293 				goto default_leaf;
294 
295 			vm_get_topology(vm, &sockets, &cores, &threads,
296 			    &maxcpus);
297 			regs[0] = vcpu_id;
298 			threads = MIN(0xFF, threads - 1);
299 			regs[1] = (threads << 8) |
300 			    (vcpu_id >> log2(threads + 1));
301 			/*
302 			 * XXX Bhyve topology cannot yet represent >1 node per
303 			 * processor.
304 			 */
305 			regs[2] = 0;
306 			regs[3] = 0;
307 			break;
308 
309 		case CPUID_0000_0001:
310 			do_cpuid(1, regs);
311 
312 			error = vm_get_x2apic_state(vm, vcpu_id, &x2apic_state);
313 			if (error) {
314 				panic("x86_emulate_cpuid: error %d "
315 				      "fetching x2apic state", error);
316 			}
317 
318 			/*
319 			 * Override the APIC ID only in ebx
320 			 */
321 			regs[1] &= ~(CPUID_LOCAL_APIC_ID);
322 			regs[1] |= (vcpu_id << CPUID_0000_0001_APICID_SHIFT);
323 
324 			/*
325 			 * Don't expose VMX, SpeedStep, TME or SMX capability.
326 			 * Advertise x2APIC capability and Hypervisor guest.
327 			 */
328 			regs[2] &= ~(CPUID2_VMX | CPUID2_EST | CPUID2_TM2);
329 			regs[2] &= ~(CPUID2_SMX);
330 
331 			regs[2] |= CPUID2_HV;
332 
333 			if (x2apic_state != X2APIC_DISABLED)
334 				regs[2] |= CPUID2_X2APIC;
335 			else
336 				regs[2] &= ~CPUID2_X2APIC;
337 
338 			/*
339 			 * Only advertise CPUID2_XSAVE in the guest if
340 			 * the host is using XSAVE.
341 			 */
342 			if (!(regs[2] & CPUID2_OSXSAVE))
343 				regs[2] &= ~CPUID2_XSAVE;
344 
345 			/*
346 			 * If CPUID2_XSAVE is being advertised and the
347 			 * guest has set CR4_XSAVE, set
348 			 * CPUID2_OSXSAVE.
349 			 */
350 			regs[2] &= ~CPUID2_OSXSAVE;
351 			if (regs[2] & CPUID2_XSAVE) {
352 				error = vm_get_register(vm, vcpu_id,
353 				    VM_REG_GUEST_CR4, &cr4);
354 				if (error)
355 					panic("x86_emulate_cpuid: error %d "
356 					      "fetching %%cr4", error);
357 				if (cr4 & CR4_XSAVE)
358 					regs[2] |= CPUID2_OSXSAVE;
359 			}
360 
361 			/*
362 			 * Hide monitor/mwait until we know how to deal with
363 			 * these instructions.
364 			 */
365 			regs[2] &= ~CPUID2_MON;
366 
367                         /*
368 			 * Hide the performance and debug features.
369 			 */
370 			regs[2] &= ~CPUID2_PDCM;
371 
372 			/*
373 			 * No TSC deadline support in the APIC yet
374 			 */
375 			regs[2] &= ~CPUID2_TSCDLT;
376 
377 			/*
378 			 * Hide thermal monitoring
379 			 */
380 			regs[3] &= ~(CPUID_ACPI | CPUID_TM);
381 
382 			/*
383 			 * Hide the debug store capability.
384 			 */
385 			regs[3] &= ~CPUID_DS;
386 
387 			/*
388 			 * Advertise the Machine Check and MTRR capability.
389 			 *
390 			 * Some guest OSes (e.g. Windows) will not boot if
391 			 * these features are absent.
392 			 */
393 			regs[3] |= (CPUID_MCA | CPUID_MCE | CPUID_MTRR);
394 
395 			vm_get_topology(vm, &sockets, &cores, &threads,
396 			    &maxcpus);
397 			logical_cpus = threads * cores;
398 			regs[1] &= ~CPUID_HTT_CORES;
399 			regs[1] |= (logical_cpus & 0xff) << 16;
400 			regs[3] |= CPUID_HTT;
401 			break;
402 
403 		case CPUID_0000_0004:
404 			cpuid_count(func, param, regs);
405 
406 			if (regs[0] || regs[1] || regs[2] || regs[3]) {
407 				vm_get_topology(vm, &sockets, &cores, &threads,
408 				    &maxcpus);
409 				regs[0] &= 0x3ff;
410 				regs[0] |= (cores - 1) << 26;
411 				/*
412 				 * Cache topology:
413 				 * - L1 and L2 are shared only by the logical
414 				 *   processors in a single core.
415 				 * - L3 and above are shared by all logical
416 				 *   processors in the package.
417 				 */
418 				logical_cpus = threads;
419 				level = (regs[0] >> 5) & 0x7;
420 				if (level >= 3)
421 					logical_cpus *= cores;
422 				regs[0] |= (logical_cpus - 1) << 14;
423 			}
424 			break;
425 
426 		case CPUID_0000_0007:
427 			regs[0] = 0;
428 			regs[1] = 0;
429 			regs[2] = 0;
430 			regs[3] = 0;
431 
432 			/* leaf 0 */
433 			if (param == 0) {
434 				cpuid_count(func, param, regs);
435 
436 				/* Only leaf 0 is supported */
437 				regs[0] = 0;
438 
439 				/*
440 				 * Expose known-safe features.
441 				 */
442 				regs[1] &= (CPUID_STDEXT_FSGSBASE |
443 				    CPUID_STDEXT_BMI1 | CPUID_STDEXT_HLE |
444 				    CPUID_STDEXT_AVX2 | CPUID_STDEXT_BMI2 |
445 				    CPUID_STDEXT_ERMS | CPUID_STDEXT_RTM |
446 				    CPUID_STDEXT_AVX512F |
447 				    CPUID_STDEXT_RDSEED |
448 				    CPUID_STDEXT_AVX512PF |
449 				    CPUID_STDEXT_AVX512ER |
450 				    CPUID_STDEXT_AVX512CD | CPUID_STDEXT_SHA);
451 				regs[2] = 0;
452 				regs[3] &= CPUID_STDEXT3_MD_CLEAR;
453 
454 				/* Advertise RDPID if it is enabled. */
455 				error = vm_get_capability(vm, vcpu_id,
456 				    VM_CAP_RDPID, &enable_rdpid);
457 				if (error == 0 && enable_rdpid)
458 					regs[2] |= CPUID_STDEXT2_RDPID;
459 
460 				/* Advertise INVPCID if it is enabled. */
461 				error = vm_get_capability(vm, vcpu_id,
462 				    VM_CAP_ENABLE_INVPCID, &enable_invpcid);
463 				if (error == 0 && enable_invpcid)
464 					regs[1] |= CPUID_STDEXT_INVPCID;
465 			}
466 			break;
467 
468 		case CPUID_0000_0006:
469 			regs[0] = CPUTPM1_ARAT;
470 			regs[1] = 0;
471 			regs[2] = 0;
472 			regs[3] = 0;
473 			break;
474 
475 		case CPUID_0000_000A:
476 			/*
477 			 * Handle the access, but report 0 for
478 			 * all options
479 			 */
480 			regs[0] = 0;
481 			regs[1] = 0;
482 			regs[2] = 0;
483 			regs[3] = 0;
484 			break;
485 
486 		case CPUID_0000_000B:
487 			/*
488 			 * Intel processor topology enumeration
489 			 */
490 			if (vmm_is_intel()) {
491 				vm_get_topology(vm, &sockets, &cores, &threads,
492 				    &maxcpus);
493 				if (param == 0) {
494 					logical_cpus = threads;
495 					width = log2(logical_cpus);
496 					level = CPUID_TYPE_SMT;
497 					x2apic_id = vcpu_id;
498 				}
499 
500 				if (param == 1) {
501 					logical_cpus = threads * cores;
502 					width = log2(logical_cpus);
503 					level = CPUID_TYPE_CORE;
504 					x2apic_id = vcpu_id;
505 				}
506 
507 				if (!cpuid_leaf_b || param >= 2) {
508 					width = 0;
509 					logical_cpus = 0;
510 					level = 0;
511 					x2apic_id = 0;
512 				}
513 
514 				regs[0] = width & 0x1f;
515 				regs[1] = logical_cpus & 0xffff;
516 				regs[2] = (level << 8) | (param & 0xff);
517 				regs[3] = x2apic_id;
518 			} else {
519 				regs[0] = 0;
520 				regs[1] = 0;
521 				regs[2] = 0;
522 				regs[3] = 0;
523 			}
524 			break;
525 
526 		case CPUID_0000_000D:
527 			limits = vmm_get_xsave_limits();
528 			if (!limits->xsave_enabled) {
529 				regs[0] = 0;
530 				regs[1] = 0;
531 				regs[2] = 0;
532 				regs[3] = 0;
533 				break;
534 			}
535 
536 			cpuid_count(func, param, regs);
537 			switch (param) {
538 			case 0:
539 				/*
540 				 * Only permit the guest to use bits
541 				 * that are active in the host in
542 				 * %xcr0.  Also, claim that the
543 				 * maximum save area size is
544 				 * equivalent to the host's current
545 				 * save area size.  Since this runs
546 				 * "inside" of vmrun(), it runs with
547 				 * the guest's xcr0, so the current
548 				 * save area size is correct as-is.
549 				 */
550 				regs[0] &= limits->xcr0_allowed;
551 				regs[2] = limits->xsave_max_size;
552 				regs[3] &= (limits->xcr0_allowed >> 32);
553 				break;
554 			case 1:
555 				/* Only permit XSAVEOPT. */
556 				regs[0] &= CPUID_EXTSTATE_XSAVEOPT;
557 				regs[1] = 0;
558 				regs[2] = 0;
559 				regs[3] = 0;
560 				break;
561 			default:
562 				/*
563 				 * If the leaf is for a permitted feature,
564 				 * pass through as-is, otherwise return
565 				 * all zeroes.
566 				 */
567 				if (!(limits->xcr0_allowed & (1ul << param))) {
568 					regs[0] = 0;
569 					regs[1] = 0;
570 					regs[2] = 0;
571 					regs[3] = 0;
572 				}
573 				break;
574 			}
575 			break;
576 
577 		case CPUID_0000_0015:
578 			/*
579 			 * Don't report CPU TSC/Crystal ratio and clock
580 			 * values since guests may use these to derive the
581 			 * local APIC frequency..
582 			 */
583 			regs[0] = 0;
584 			regs[1] = 0;
585 			regs[2] = 0;
586 			regs[3] = 0;
587 			break;
588 
589 		case 0x40000000:
590 			regs[0] = CPUID_VM_HIGH;
591 			bcopy(bhyve_id, &regs[1], 4);
592 			bcopy(bhyve_id + 4, &regs[2], 4);
593 			bcopy(bhyve_id + 8, &regs[3], 4);
594 			break;
595 
596 		default:
597 default_leaf:
598 			/*
599 			 * The leaf value has already been clamped so
600 			 * simply pass this through, keeping count of
601 			 * how many unhandled leaf values have been seen.
602 			 */
603 			atomic_add_long(&bhyve_xcpuids, 1);
604 			cpuid_count(func, param, regs);
605 			break;
606 	}
607 
608 	/*
609 	 * CPUID clears the upper 32-bits of the long-mode registers.
610 	 */
611 	*rax = regs[0];
612 	*rbx = regs[1];
613 	*rcx = regs[2];
614 	*rdx = regs[3];
615 
616 	return (1);
617 }
618 
619 bool
620 vm_cpuid_capability(struct vm *vm, int vcpuid, enum vm_cpuid_capability cap)
621 {
622 	bool rv;
623 
624 	KASSERT(cap > 0 && cap < VCC_LAST, ("%s: invalid vm_cpu_capability %d",
625 	    __func__, cap));
626 
627 	/*
628 	 * Simply passthrough the capabilities of the host cpu for now.
629 	 */
630 	rv = false;
631 	switch (cap) {
632 	case VCC_NO_EXECUTE:
633 		if (amd_feature & AMDID_NX)
634 			rv = true;
635 		break;
636 	case VCC_FFXSR:
637 		if (amd_feature & AMDID_FFXSR)
638 			rv = true;
639 		break;
640 	case VCC_TCE:
641 		if (amd_feature2 & AMDID2_TCE)
642 			rv = true;
643 		break;
644 	default:
645 		panic("%s: unknown vm_cpu_capability %d", __func__, cap);
646 	}
647 	return (rv);
648 }
649