1 /*- 2 * Copyright (c) 2011 NetApp, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/smp.h> 35 36 #include <x86/specialreg.h> 37 #include <x86/apicreg.h> 38 39 #include <machine/vmm.h> 40 #include "vmm_ktr.h" 41 #include "vmm_lapic.h" 42 #include "vlapic.h" 43 44 /* 45 * Some MSI message definitions 46 */ 47 #define MSI_X86_ADDR_MASK 0xfff00000 48 #define MSI_X86_ADDR_BASE 0xfee00000 49 #define MSI_X86_ADDR_RH 0x00000008 /* Redirection Hint */ 50 #define MSI_X86_ADDR_LOG 0x00000004 /* Destination Mode */ 51 52 int 53 lapic_set_intr(struct vm *vm, int cpu, int vector, bool level) 54 { 55 struct vlapic *vlapic; 56 57 if (cpu < 0 || cpu >= VM_MAXCPU) 58 return (EINVAL); 59 60 if (vector < 32 || vector > 255) 61 return (EINVAL); 62 63 vlapic = vm_lapic(vm, cpu); 64 if (vlapic_set_intr_ready(vlapic, vector, level)) 65 vcpu_notify_event(vm, cpu, true); 66 return (0); 67 } 68 69 int 70 lapic_set_local_intr(struct vm *vm, int cpu, int vector) 71 { 72 struct vlapic *vlapic; 73 cpuset_t dmask; 74 int error; 75 76 if (cpu < -1 || cpu >= VM_MAXCPU) 77 return (EINVAL); 78 79 if (cpu == -1) 80 dmask = vm_active_cpus(vm); 81 else 82 CPU_SETOF(cpu, &dmask); 83 error = 0; 84 while ((cpu = CPU_FFS(&dmask)) != 0) { 85 cpu--; 86 CPU_CLR(cpu, &dmask); 87 vlapic = vm_lapic(vm, cpu); 88 error = vlapic_trigger_lvt(vlapic, vector); 89 if (error) 90 break; 91 } 92 93 return (error); 94 } 95 96 int 97 lapic_intr_msi(struct vm *vm, uint64_t addr, uint64_t msg) 98 { 99 int delmode, vec; 100 uint32_t dest; 101 bool phys; 102 103 VM_CTR2(vm, "lapic MSI addr: %#lx msg: %#lx", addr, msg); 104 105 if ((addr & MSI_X86_ADDR_MASK) != MSI_X86_ADDR_BASE) { 106 VM_CTR1(vm, "lapic MSI invalid addr %#lx", addr); 107 return (-1); 108 } 109 110 /* 111 * Extract the x86-specific fields from the MSI addr/msg 112 * params according to the Intel Arch spec, Vol3 Ch 10. 113 * 114 * The PCI specification does not support level triggered 115 * MSI/MSI-X so ignore trigger level in 'msg'. 116 * 117 * The 'dest' is interpreted as a logical APIC ID if both 118 * the Redirection Hint and Destination Mode are '1' and 119 * physical otherwise. 120 */ 121 dest = (addr >> 12) & 0xff; 122 phys = ((addr & (MSI_X86_ADDR_RH | MSI_X86_ADDR_LOG)) != 123 (MSI_X86_ADDR_RH | MSI_X86_ADDR_LOG)); 124 delmode = msg & APIC_DELMODE_MASK; 125 vec = msg & 0xff; 126 127 VM_CTR3(vm, "lapic MSI %s dest %#x, vec %d", 128 phys ? "physical" : "logical", dest, vec); 129 130 vlapic_deliver_intr(vm, LAPIC_TRIG_EDGE, dest, phys, delmode, vec); 131 return (0); 132 } 133 134 static boolean_t 135 x2apic_msr(u_int msr) 136 { 137 if (msr >= 0x800 && msr <= 0xBFF) 138 return (TRUE); 139 else 140 return (FALSE); 141 } 142 143 static u_int 144 x2apic_msr_to_regoff(u_int msr) 145 { 146 147 return ((msr - 0x800) << 4); 148 } 149 150 boolean_t 151 lapic_msr(u_int msr) 152 { 153 154 if (x2apic_msr(msr) || (msr == MSR_APICBASE)) 155 return (TRUE); 156 else 157 return (FALSE); 158 } 159 160 int 161 lapic_rdmsr(struct vm *vm, int cpu, u_int msr, uint64_t *rval, bool *retu) 162 { 163 int error; 164 u_int offset; 165 struct vlapic *vlapic; 166 167 vlapic = vm_lapic(vm, cpu); 168 169 if (msr == MSR_APICBASE) { 170 *rval = vlapic_get_apicbase(vlapic); 171 error = 0; 172 } else { 173 offset = x2apic_msr_to_regoff(msr); 174 error = vlapic_read(vlapic, 0, offset, rval, retu); 175 } 176 177 return (error); 178 } 179 180 int 181 lapic_wrmsr(struct vm *vm, int cpu, u_int msr, uint64_t val, bool *retu) 182 { 183 int error; 184 u_int offset; 185 struct vlapic *vlapic; 186 187 vlapic = vm_lapic(vm, cpu); 188 189 if (msr == MSR_APICBASE) { 190 error = vlapic_set_apicbase(vlapic, val); 191 } else { 192 offset = x2apic_msr_to_regoff(msr); 193 error = vlapic_write(vlapic, 0, offset, val, retu); 194 } 195 196 return (error); 197 } 198 199 int 200 lapic_mmio_write(void *vm, int cpu, uint64_t gpa, uint64_t wval, int size, 201 void *arg) 202 { 203 int error; 204 uint64_t off; 205 struct vlapic *vlapic; 206 207 off = gpa - DEFAULT_APIC_BASE; 208 209 /* 210 * Memory mapped local apic accesses must be 4 bytes wide and 211 * aligned on a 16-byte boundary. 212 */ 213 if (size != 4 || off & 0xf) 214 return (EINVAL); 215 216 vlapic = vm_lapic(vm, cpu); 217 error = vlapic_write(vlapic, 1, off, wval, arg); 218 return (error); 219 } 220 221 int 222 lapic_mmio_read(void *vm, int cpu, uint64_t gpa, uint64_t *rval, int size, 223 void *arg) 224 { 225 int error; 226 uint64_t off; 227 struct vlapic *vlapic; 228 229 off = gpa - DEFAULT_APIC_BASE; 230 231 /* 232 * Memory mapped local apic accesses should be aligned on a 233 * 16-byte boundary. They are also suggested to be 4 bytes 234 * wide, alas not all OSes follow suggestions. 235 */ 236 off &= ~3; 237 if (off & 0xf) 238 return (EINVAL); 239 240 vlapic = vm_lapic(vm, cpu); 241 error = vlapic_read(vlapic, 1, off, rval, arg); 242 return (error); 243 } 244