1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/smp.h> 35 36 #include <x86/specialreg.h> 37 #include <x86/apicreg.h> 38 39 #include <machine/vmm.h> 40 #include "vmm_ktr.h" 41 #include "vmm_lapic.h" 42 #include "vlapic.h" 43 44 /* 45 * Some MSI message definitions 46 */ 47 #define MSI_X86_ADDR_MASK 0xfff00000 48 #define MSI_X86_ADDR_BASE 0xfee00000 49 #define MSI_X86_ADDR_RH 0x00000008 /* Redirection Hint */ 50 #define MSI_X86_ADDR_LOG 0x00000004 /* Destination Mode */ 51 52 int 53 lapic_set_intr(struct vcpu *vcpu, int vector, bool level) 54 { 55 struct vlapic *vlapic; 56 57 /* 58 * According to section "Maskable Hardware Interrupts" in Intel SDM 59 * vectors 16 through 255 can be delivered through the local APIC. 60 */ 61 if (vector < 16 || vector > 255) 62 return (EINVAL); 63 64 vlapic = vm_lapic(vcpu); 65 if (vlapic_set_intr_ready(vlapic, vector, level)) 66 vcpu_notify_event(vcpu, true); 67 return (0); 68 } 69 70 int 71 lapic_set_local_intr(struct vm *vm, struct vcpu *vcpu, int vector) 72 { 73 struct vlapic *vlapic; 74 cpuset_t dmask; 75 int cpu, error; 76 77 if (vcpu == NULL) { 78 error = 0; 79 dmask = vm_active_cpus(vm); 80 CPU_FOREACH_ISSET(cpu, &dmask) { 81 vlapic = vm_lapic(vm_vcpu(vm, cpu)); 82 error = vlapic_trigger_lvt(vlapic, vector); 83 if (error) 84 break; 85 } 86 } else { 87 vlapic = vm_lapic(vcpu); 88 error = vlapic_trigger_lvt(vlapic, vector); 89 } 90 91 return (error); 92 } 93 94 int 95 lapic_intr_msi(struct vm *vm, uint64_t addr, uint64_t msg) 96 { 97 int delmode, vec; 98 uint32_t dest; 99 bool phys; 100 101 VM_CTR2(vm, "lapic MSI addr: %#lx msg: %#lx", addr, msg); 102 103 if ((addr & MSI_X86_ADDR_MASK) != MSI_X86_ADDR_BASE) { 104 VM_CTR1(vm, "lapic MSI invalid addr %#lx", addr); 105 return (-1); 106 } 107 108 /* 109 * Extract the x86-specific fields from the MSI addr/msg 110 * params according to the Intel Arch spec, Vol3 Ch 10. 111 * 112 * The PCI specification does not support level triggered 113 * MSI/MSI-X so ignore trigger level in 'msg'. 114 * 115 * The 'dest' is interpreted as a logical APIC ID if both 116 * the Redirection Hint and Destination Mode are '1' and 117 * physical otherwise. 118 */ 119 dest = (addr >> 12) & 0xff; 120 phys = ((addr & (MSI_X86_ADDR_RH | MSI_X86_ADDR_LOG)) != 121 (MSI_X86_ADDR_RH | MSI_X86_ADDR_LOG)); 122 delmode = msg & APIC_DELMODE_MASK; 123 vec = msg & 0xff; 124 125 VM_CTR3(vm, "lapic MSI %s dest %#x, vec %d", 126 phys ? "physical" : "logical", dest, vec); 127 128 vlapic_deliver_intr(vm, LAPIC_TRIG_EDGE, dest, phys, delmode, vec); 129 return (0); 130 } 131 132 static bool 133 x2apic_msr(u_int msr) 134 { 135 return (msr >= 0x800 && msr <= 0xBFF); 136 } 137 138 static u_int 139 x2apic_msr_to_regoff(u_int msr) 140 { 141 142 return ((msr - 0x800) << 4); 143 } 144 145 bool 146 lapic_msr(u_int msr) 147 { 148 149 return (x2apic_msr(msr) || msr == MSR_APICBASE); 150 } 151 152 int 153 lapic_rdmsr(struct vcpu *vcpu, u_int msr, uint64_t *rval, bool *retu) 154 { 155 int error; 156 u_int offset; 157 struct vlapic *vlapic; 158 159 vlapic = vm_lapic(vcpu); 160 161 if (msr == MSR_APICBASE) { 162 *rval = vlapic_get_apicbase(vlapic); 163 error = 0; 164 } else { 165 offset = x2apic_msr_to_regoff(msr); 166 error = vlapic_read(vlapic, 0, offset, rval, retu); 167 } 168 169 return (error); 170 } 171 172 int 173 lapic_wrmsr(struct vcpu *vcpu, u_int msr, uint64_t val, bool *retu) 174 { 175 int error; 176 u_int offset; 177 struct vlapic *vlapic; 178 179 vlapic = vm_lapic(vcpu); 180 181 if (msr == MSR_APICBASE) { 182 error = vlapic_set_apicbase(vlapic, val); 183 } else { 184 offset = x2apic_msr_to_regoff(msr); 185 error = vlapic_write(vlapic, 0, offset, val, retu); 186 } 187 188 return (error); 189 } 190 191 int 192 lapic_mmio_write(struct vcpu *vcpu, uint64_t gpa, uint64_t wval, int size, 193 void *arg) 194 { 195 int error; 196 uint64_t off; 197 struct vlapic *vlapic; 198 199 off = gpa - DEFAULT_APIC_BASE; 200 201 /* 202 * Memory mapped local apic accesses must be 4 bytes wide and 203 * aligned on a 16-byte boundary. 204 */ 205 if (size != 4 || off & 0xf) 206 return (EINVAL); 207 208 vlapic = vm_lapic(vcpu); 209 error = vlapic_write(vlapic, 1, off, wval, arg); 210 return (error); 211 } 212 213 int 214 lapic_mmio_read(struct vcpu *vcpu, uint64_t gpa, uint64_t *rval, int size, 215 void *arg) 216 { 217 int error; 218 uint64_t off; 219 struct vlapic *vlapic; 220 221 off = gpa - DEFAULT_APIC_BASE; 222 223 /* 224 * Memory mapped local apic accesses should be aligned on a 225 * 16-byte boundary. They are also suggested to be 4 bytes 226 * wide, alas not all OSes follow suggestions. 227 */ 228 off &= ~3; 229 if (off & 0xf) 230 return (EINVAL); 231 232 vlapic = vm_lapic(vcpu); 233 error = vlapic_read(vlapic, 1, off, rval, arg); 234 return (error); 235 } 236