1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/smp.h> 37 38 #include <x86/specialreg.h> 39 #include <x86/apicreg.h> 40 41 #include <machine/vmm.h> 42 #include "vmm_ktr.h" 43 #include "vmm_lapic.h" 44 #include "vlapic.h" 45 46 /* 47 * Some MSI message definitions 48 */ 49 #define MSI_X86_ADDR_MASK 0xfff00000 50 #define MSI_X86_ADDR_BASE 0xfee00000 51 #define MSI_X86_ADDR_RH 0x00000008 /* Redirection Hint */ 52 #define MSI_X86_ADDR_LOG 0x00000004 /* Destination Mode */ 53 54 int 55 lapic_set_intr(struct vm *vm, int cpu, int vector, bool level) 56 { 57 struct vlapic *vlapic; 58 59 if (cpu < 0 || cpu >= vm_get_maxcpus(vm)) 60 return (EINVAL); 61 62 /* 63 * According to section "Maskable Hardware Interrupts" in Intel SDM 64 * vectors 16 through 255 can be delivered through the local APIC. 65 */ 66 if (vector < 16 || vector > 255) 67 return (EINVAL); 68 69 vlapic = vm_lapic(vm, cpu); 70 if (vlapic_set_intr_ready(vlapic, vector, level)) 71 vcpu_notify_event(vm, cpu, true); 72 return (0); 73 } 74 75 int 76 lapic_set_local_intr(struct vm *vm, int cpu, int vector) 77 { 78 struct vlapic *vlapic; 79 cpuset_t dmask; 80 int error; 81 82 if (cpu < -1 || cpu >= vm_get_maxcpus(vm)) 83 return (EINVAL); 84 85 if (cpu == -1) 86 dmask = vm_active_cpus(vm); 87 else 88 CPU_SETOF(cpu, &dmask); 89 error = 0; 90 CPU_FOREACH_ISSET(cpu, &dmask) { 91 vlapic = vm_lapic(vm, cpu); 92 error = vlapic_trigger_lvt(vlapic, vector); 93 if (error) 94 break; 95 } 96 97 return (error); 98 } 99 100 int 101 lapic_intr_msi(struct vm *vm, uint64_t addr, uint64_t msg) 102 { 103 int delmode, vec; 104 uint32_t dest; 105 bool phys; 106 107 VM_CTR2(vm, "lapic MSI addr: %#lx msg: %#lx", addr, msg); 108 109 if ((addr & MSI_X86_ADDR_MASK) != MSI_X86_ADDR_BASE) { 110 VM_CTR1(vm, "lapic MSI invalid addr %#lx", addr); 111 return (-1); 112 } 113 114 /* 115 * Extract the x86-specific fields from the MSI addr/msg 116 * params according to the Intel Arch spec, Vol3 Ch 10. 117 * 118 * The PCI specification does not support level triggered 119 * MSI/MSI-X so ignore trigger level in 'msg'. 120 * 121 * The 'dest' is interpreted as a logical APIC ID if both 122 * the Redirection Hint and Destination Mode are '1' and 123 * physical otherwise. 124 */ 125 dest = (addr >> 12) & 0xff; 126 phys = ((addr & (MSI_X86_ADDR_RH | MSI_X86_ADDR_LOG)) != 127 (MSI_X86_ADDR_RH | MSI_X86_ADDR_LOG)); 128 delmode = msg & APIC_DELMODE_MASK; 129 vec = msg & 0xff; 130 131 VM_CTR3(vm, "lapic MSI %s dest %#x, vec %d", 132 phys ? "physical" : "logical", dest, vec); 133 134 vlapic_deliver_intr(vm, LAPIC_TRIG_EDGE, dest, phys, delmode, vec); 135 return (0); 136 } 137 138 static bool 139 x2apic_msr(u_int msr) 140 { 141 return (msr >= 0x800 && msr <= 0xBFF); 142 } 143 144 static u_int 145 x2apic_msr_to_regoff(u_int msr) 146 { 147 148 return ((msr - 0x800) << 4); 149 } 150 151 bool 152 lapic_msr(u_int msr) 153 { 154 155 return (x2apic_msr(msr) || msr == MSR_APICBASE); 156 } 157 158 int 159 lapic_rdmsr(struct vm *vm, int cpu, u_int msr, uint64_t *rval, bool *retu) 160 { 161 int error; 162 u_int offset; 163 struct vlapic *vlapic; 164 165 vlapic = vm_lapic(vm, cpu); 166 167 if (msr == MSR_APICBASE) { 168 *rval = vlapic_get_apicbase(vlapic); 169 error = 0; 170 } else { 171 offset = x2apic_msr_to_regoff(msr); 172 error = vlapic_read(vlapic, 0, offset, rval, retu); 173 } 174 175 return (error); 176 } 177 178 int 179 lapic_wrmsr(struct vm *vm, int cpu, u_int msr, uint64_t val, bool *retu) 180 { 181 int error; 182 u_int offset; 183 struct vlapic *vlapic; 184 185 vlapic = vm_lapic(vm, cpu); 186 187 if (msr == MSR_APICBASE) { 188 error = vlapic_set_apicbase(vlapic, val); 189 } else { 190 offset = x2apic_msr_to_regoff(msr); 191 error = vlapic_write(vlapic, 0, offset, val, retu); 192 } 193 194 return (error); 195 } 196 197 int 198 lapic_mmio_write(void *vm, int cpu, uint64_t gpa, uint64_t wval, int size, 199 void *arg) 200 { 201 int error; 202 uint64_t off; 203 struct vlapic *vlapic; 204 205 off = gpa - DEFAULT_APIC_BASE; 206 207 /* 208 * Memory mapped local apic accesses must be 4 bytes wide and 209 * aligned on a 16-byte boundary. 210 */ 211 if (size != 4 || off & 0xf) 212 return (EINVAL); 213 214 vlapic = vm_lapic(vm, cpu); 215 error = vlapic_write(vlapic, 1, off, wval, arg); 216 return (error); 217 } 218 219 int 220 lapic_mmio_read(void *vm, int cpu, uint64_t gpa, uint64_t *rval, int size, 221 void *arg) 222 { 223 int error; 224 uint64_t off; 225 struct vlapic *vlapic; 226 227 off = gpa - DEFAULT_APIC_BASE; 228 229 /* 230 * Memory mapped local apic accesses should be aligned on a 231 * 16-byte boundary. They are also suggested to be 4 bytes 232 * wide, alas not all OSes follow suggestions. 233 */ 234 off &= ~3; 235 if (off & 0xf) 236 return (EINVAL); 237 238 vlapic = vm_lapic(vm, cpu); 239 error = vlapic_read(vlapic, 1, off, rval, arg); 240 return (error); 241 } 242