1 /*- 2 * Copyright (c) 2011 NetApp, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef _VLAPIC_H_ 30 #define _VLAPIC_H_ 31 32 struct vm; 33 34 /* 35 * Map of APIC Registers: Offset Description Access 36 */ 37 #define APIC_OFFSET_ID 0x20 // Local APIC ID R/W 38 #define APIC_OFFSET_VER 0x30 // Local APIC Version R 39 #define APIC_OFFSET_TPR 0x80 // Task Priority Register R/W 40 #define APIC_OFFSET_APR 0x90 // Arbitration Priority Register R 41 #define APIC_OFFSET_PPR 0xA0 // Processor Priority Register R 42 #define APIC_OFFSET_EOI 0xB0 // EOI Register W 43 #define APIC_OFFSET_RRR 0xC0 // Remote read R 44 #define APIC_OFFSET_LDR 0xD0 // Logical Destination R/W 45 #define APIC_OFFSET_DFR 0xE0 // Destination Format Register 0..27 R; 28..31 R/W 46 #define APIC_OFFSET_SVR 0xF0 // Spurious Interrupt Vector Reg. 0..3 R; 4..9 R/W 47 #define APIC_OFFSET_ISR0 0x100 // ISR 000-031 R 48 #define APIC_OFFSET_ISR1 0x110 // ISR 032-063 R 49 #define APIC_OFFSET_ISR2 0x120 // ISR 064-095 R 50 #define APIC_OFFSET_ISR3 0x130 // ISR 095-128 R 51 #define APIC_OFFSET_ISR4 0x140 // ISR 128-159 R 52 #define APIC_OFFSET_ISR5 0x150 // ISR 160-191 R 53 #define APIC_OFFSET_ISR6 0x160 // ISR 192-223 R 54 #define APIC_OFFSET_ISR7 0x170 // ISR 224-255 R 55 #define APIC_OFFSET_TMR0 0x180 // TMR 000-031 R 56 #define APIC_OFFSET_TMR1 0x190 // TMR 032-063 R 57 #define APIC_OFFSET_TMR2 0x1A0 // TMR 064-095 R 58 #define APIC_OFFSET_TMR3 0x1B0 // TMR 095-128 R 59 #define APIC_OFFSET_TMR4 0x1C0 // TMR 128-159 R 60 #define APIC_OFFSET_TMR5 0x1D0 // TMR 160-191 R 61 #define APIC_OFFSET_TMR6 0x1E0 // TMR 192-223 R 62 #define APIC_OFFSET_TMR7 0x1F0 // TMR 224-255 R 63 #define APIC_OFFSET_IRR0 0x200 // IRR 000-031 R 64 #define APIC_OFFSET_IRR1 0x210 // IRR 032-063 R 65 #define APIC_OFFSET_IRR2 0x220 // IRR 064-095 R 66 #define APIC_OFFSET_IRR3 0x230 // IRR 095-128 R 67 #define APIC_OFFSET_IRR4 0x240 // IRR 128-159 R 68 #define APIC_OFFSET_IRR5 0x250 // IRR 160-191 R 69 #define APIC_OFFSET_IRR6 0x260 // IRR 192-223 R 70 #define APIC_OFFSET_IRR7 0x270 // IRR 224-255 R 71 #define APIC_OFFSET_ESR 0x280 // Error Status Register R 72 #define APIC_OFFSET_ICR_LOW 0x300 // Interrupt Command Reg. (0-31) R/W 73 #define APIC_OFFSET_ICR_HI 0x310 // Interrupt Command Reg. (32-63) R/W 74 #define APIC_OFFSET_TIMER_LVT 0x320 // Local Vector Table (Timer) R/W 75 #define APIC_OFFSET_THERM_LVT 0x330 // Local Vector Table (Thermal) R/W (PIV+) 76 #define APIC_OFFSET_PERF_LVT 0x340 // Local Vector Table (Performance) R/W (P6+) 77 #define APIC_OFFSET_LINT0_LVT 0x350 // Local Vector Table (LINT0) R/W 78 #define APIC_OFFSET_LINT1_LVT 0x360 // Local Vector Table (LINT1) R/W 79 #define APIC_OFFSET_ERROR_LVT 0x370 // Local Vector Table (ERROR) R/W 80 #define APIC_OFFSET_ICR 0x380 // Initial Count Reg. for Timer R/W 81 #define APIC_OFFSET_CCR 0x390 // Current Count of Timer R 82 #define APIC_OFFSET_DCR 0x3E0 // Timer Divide Configuration Reg. R/W 83 84 /* 85 * 16 priority levels with at most one vector injected per level. 86 */ 87 #define ISRVEC_STK_SIZE (16 + 1) 88 89 enum x2apic_state; 90 91 struct vlapic *vlapic_init(struct vm *vm, int vcpuid); 92 void vlapic_cleanup(struct vlapic *vlapic); 93 int vlapic_write(struct vlapic *vlapic, uint64_t offset, uint64_t data); 94 int vlapic_read(struct vlapic *vlapic, uint64_t offset, uint64_t *data); 95 int vlapic_pending_intr(struct vlapic *vlapic); 96 void vlapic_intr_accepted(struct vlapic *vlapic, int vector); 97 void vlapic_set_intr_ready(struct vlapic *vlapic, int vector); 98 int vlapic_timer_tick(struct vlapic *vlapic); 99 100 uint64_t vlapic_get_apicbase(struct vlapic *vlapic); 101 void vlapic_set_apicbase(struct vlapic *vlapic, uint64_t val); 102 void vlapic_set_x2apic_state(struct vm *vm, int vcpuid, enum x2apic_state s); 103 104 #endif /* _VLAPIC_H_ */ 105