1 /*- 2 * Copyright (c) 2011 NetApp, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef _VMX_H_ 30 #define _VMX_H_ 31 32 #include "vmcs.h" 33 34 struct pmap; 35 36 #define GUEST_MSR_MAX_ENTRIES 64 /* arbitrary */ 37 38 struct vmxctx { 39 register_t guest_rdi; /* Guest state */ 40 register_t guest_rsi; 41 register_t guest_rdx; 42 register_t guest_rcx; 43 register_t guest_r8; 44 register_t guest_r9; 45 register_t guest_rax; 46 register_t guest_rbx; 47 register_t guest_rbp; 48 register_t guest_r10; 49 register_t guest_r11; 50 register_t guest_r12; 51 register_t guest_r13; 52 register_t guest_r14; 53 register_t guest_r15; 54 register_t guest_cr2; 55 56 register_t host_r15; /* Host state */ 57 register_t host_r14; 58 register_t host_r13; 59 register_t host_r12; 60 register_t host_rbp; 61 register_t host_rsp; 62 register_t host_rbx; 63 /* 64 * XXX todo debug registers and fpu state 65 */ 66 67 int inst_fail_status; 68 69 /* 70 * The pmap needs to be deactivated in vmx_enter_guest() 71 * so keep a copy of the 'pmap' in each vmxctx. 72 */ 73 struct pmap *pmap; 74 }; 75 76 struct vmxcap { 77 int set; 78 uint32_t proc_ctls; 79 uint32_t proc_ctls2; 80 }; 81 82 struct vmxstate { 83 int lastcpu; /* host cpu that this 'vcpu' last ran on */ 84 uint16_t vpid; 85 }; 86 87 struct apic_page { 88 uint32_t reg[PAGE_SIZE / 4]; 89 }; 90 CTASSERT(sizeof(struct apic_page) == PAGE_SIZE); 91 92 /* Posted Interrupt Descriptor (described in section 29.6 of the Intel SDM) */ 93 struct pir_desc { 94 uint64_t pir[4]; 95 uint64_t pending; 96 uint64_t unused[3]; 97 } __aligned(64); 98 CTASSERT(sizeof(struct pir_desc) == 64); 99 100 /* virtual machine softc */ 101 struct vmx { 102 struct vmcs vmcs[VM_MAXCPU]; /* one vmcs per virtual cpu */ 103 struct apic_page apic_page[VM_MAXCPU]; /* one apic page per vcpu */ 104 char msr_bitmap[PAGE_SIZE]; 105 struct pir_desc pir_desc[VM_MAXCPU]; 106 struct msr_entry guest_msrs[VM_MAXCPU][GUEST_MSR_MAX_ENTRIES]; 107 struct vmxctx ctx[VM_MAXCPU]; 108 struct vmxcap cap[VM_MAXCPU]; 109 struct vmxstate state[VM_MAXCPU]; 110 uint64_t eptp; 111 struct vm *vm; 112 long eptgen[MAXCPU]; /* cached pmap->pm_eptgen */ 113 }; 114 CTASSERT((offsetof(struct vmx, vmcs) & PAGE_MASK) == 0); 115 CTASSERT((offsetof(struct vmx, msr_bitmap) & PAGE_MASK) == 0); 116 CTASSERT((offsetof(struct vmx, guest_msrs) & 15) == 0); 117 CTASSERT((offsetof(struct vmx, pir_desc[0]) & 63) == 0); 118 119 #define VMX_GUEST_VMEXIT 0 120 #define VMX_VMRESUME_ERROR 1 121 #define VMX_VMLAUNCH_ERROR 2 122 #define VMX_INVEPT_ERROR 3 123 int vmx_enter_guest(struct vmxctx *ctx, struct vmx *vmx, int launched); 124 void vmx_call_isr(uintptr_t entry); 125 126 u_long vmx_fix_cr0(u_long cr0); 127 u_long vmx_fix_cr4(u_long cr4); 128 129 extern char vmx_exit_guest[]; 130 131 #endif 132