1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * Copyright (c) 2018 Joyent, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include "opt_bhyve_snapshot.h" 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/smp.h> 35 #include <sys/kernel.h> 36 #include <sys/malloc.h> 37 #include <sys/pcpu.h> 38 #include <sys/proc.h> 39 #include <sys/reg.h> 40 #include <sys/smr.h> 41 #include <sys/sysctl.h> 42 43 #include <vm/vm.h> 44 #include <vm/vm_extern.h> 45 #include <vm/pmap.h> 46 47 #include <machine/psl.h> 48 #include <machine/cpufunc.h> 49 #include <machine/md_var.h> 50 #include <machine/segments.h> 51 #include <machine/smp.h> 52 #include <machine/specialreg.h> 53 #include <machine/vmparam.h> 54 55 #include <machine/vmm.h> 56 #include <machine/vmm_instruction_emul.h> 57 #include <machine/vmm_snapshot.h> 58 59 #include <dev/vmm/vmm_dev.h> 60 #include <dev/vmm/vmm_ktr.h> 61 #include <dev/vmm/vmm_mem.h> 62 #include <dev/vmm/vmm_vm.h> 63 64 #include "vmm_lapic.h" 65 #include "vmm_host.h" 66 #include "vmm_ioport.h" 67 #include "vmm_stat.h" 68 #include "vatpic.h" 69 #include "vlapic.h" 70 #include "vlapic_priv.h" 71 72 #include "ept.h" 73 #include "vmx_cpufunc.h" 74 #include "vmx.h" 75 #include "vmx_msr.h" 76 #include "x86.h" 77 #include "vmx_controls.h" 78 #include "io/ppt.h" 79 80 #define PINBASED_CTLS_ONE_SETTING \ 81 (PINBASED_EXTINT_EXITING | \ 82 PINBASED_NMI_EXITING | \ 83 PINBASED_VIRTUAL_NMI) 84 #define PINBASED_CTLS_ZERO_SETTING 0 85 86 #define PROCBASED_CTLS_WINDOW_SETTING \ 87 (PROCBASED_INT_WINDOW_EXITING | \ 88 PROCBASED_NMI_WINDOW_EXITING) 89 90 #define PROCBASED_CTLS_ONE_SETTING \ 91 (PROCBASED_SECONDARY_CONTROLS | \ 92 PROCBASED_MWAIT_EXITING | \ 93 PROCBASED_MONITOR_EXITING | \ 94 PROCBASED_IO_EXITING | \ 95 PROCBASED_MSR_BITMAPS | \ 96 PROCBASED_CTLS_WINDOW_SETTING | \ 97 PROCBASED_CR8_LOAD_EXITING | \ 98 PROCBASED_CR8_STORE_EXITING) 99 #define PROCBASED_CTLS_ZERO_SETTING \ 100 (PROCBASED_CR3_LOAD_EXITING | \ 101 PROCBASED_CR3_STORE_EXITING | \ 102 PROCBASED_IO_BITMAPS) 103 104 #define PROCBASED_CTLS2_ONE_SETTING PROCBASED2_ENABLE_EPT 105 #define PROCBASED_CTLS2_ZERO_SETTING 0 106 107 #define VM_EXIT_CTLS_ONE_SETTING \ 108 (VM_EXIT_SAVE_DEBUG_CONTROLS | \ 109 VM_EXIT_HOST_LMA | \ 110 VM_EXIT_SAVE_EFER | \ 111 VM_EXIT_LOAD_EFER | \ 112 VM_EXIT_ACKNOWLEDGE_INTERRUPT) 113 114 #define VM_EXIT_CTLS_ZERO_SETTING 0 115 116 #define VM_ENTRY_CTLS_ONE_SETTING \ 117 (VM_ENTRY_LOAD_DEBUG_CONTROLS | \ 118 VM_ENTRY_LOAD_EFER) 119 120 #define VM_ENTRY_CTLS_ZERO_SETTING \ 121 (VM_ENTRY_INTO_SMM | \ 122 VM_ENTRY_DEACTIVATE_DUAL_MONITOR) 123 124 #define HANDLED 1 125 #define UNHANDLED 0 126 127 static MALLOC_DEFINE(M_VMX, "vmx", "vmx"); 128 static MALLOC_DEFINE(M_VLAPIC, "vlapic", "vlapic"); 129 130 bool vmx_have_msr_tsc_aux; 131 132 SYSCTL_DECL(_hw_vmm); 133 SYSCTL_NODE(_hw_vmm, OID_AUTO, vmx, CTLFLAG_RW | CTLFLAG_MPSAFE, NULL, 134 NULL); 135 136 int vmxon_enabled[MAXCPU]; 137 static uint8_t *vmxon_region; 138 139 static uint32_t pinbased_ctls, procbased_ctls, procbased_ctls2; 140 static uint32_t exit_ctls, entry_ctls; 141 142 static uint64_t cr0_ones_mask, cr0_zeros_mask; 143 SYSCTL_ULONG(_hw_vmm_vmx, OID_AUTO, cr0_ones_mask, CTLFLAG_RD, 144 &cr0_ones_mask, 0, NULL); 145 SYSCTL_ULONG(_hw_vmm_vmx, OID_AUTO, cr0_zeros_mask, CTLFLAG_RD, 146 &cr0_zeros_mask, 0, NULL); 147 148 static uint64_t cr4_ones_mask, cr4_zeros_mask; 149 SYSCTL_ULONG(_hw_vmm_vmx, OID_AUTO, cr4_ones_mask, CTLFLAG_RD, 150 &cr4_ones_mask, 0, NULL); 151 SYSCTL_ULONG(_hw_vmm_vmx, OID_AUTO, cr4_zeros_mask, CTLFLAG_RD, 152 &cr4_zeros_mask, 0, NULL); 153 154 static int vmx_initialized; 155 SYSCTL_INT(_hw_vmm_vmx, OID_AUTO, initialized, CTLFLAG_RD, 156 &vmx_initialized, 0, "Intel VMX initialized"); 157 158 /* 159 * Optional capabilities 160 */ 161 static SYSCTL_NODE(_hw_vmm_vmx, OID_AUTO, cap, 162 CTLFLAG_RW | CTLFLAG_MPSAFE, NULL, 163 NULL); 164 165 static int cap_halt_exit; 166 SYSCTL_INT(_hw_vmm_vmx_cap, OID_AUTO, halt_exit, CTLFLAG_RD, &cap_halt_exit, 0, 167 "HLT triggers a VM-exit"); 168 169 static int cap_pause_exit; 170 SYSCTL_INT(_hw_vmm_vmx_cap, OID_AUTO, pause_exit, CTLFLAG_RD, &cap_pause_exit, 171 0, "PAUSE triggers a VM-exit"); 172 173 static int cap_wbinvd_exit; 174 SYSCTL_INT(_hw_vmm_vmx_cap, OID_AUTO, wbinvd_exit, CTLFLAG_RD, &cap_wbinvd_exit, 175 0, "WBINVD triggers a VM-exit"); 176 177 static int cap_rdpid; 178 SYSCTL_INT(_hw_vmm_vmx_cap, OID_AUTO, rdpid, CTLFLAG_RD, &cap_rdpid, 0, 179 "Guests are allowed to use RDPID"); 180 181 static int cap_rdtscp; 182 SYSCTL_INT(_hw_vmm_vmx_cap, OID_AUTO, rdtscp, CTLFLAG_RD, &cap_rdtscp, 0, 183 "Guests are allowed to use RDTSCP"); 184 185 static int cap_unrestricted_guest; 186 SYSCTL_INT(_hw_vmm_vmx_cap, OID_AUTO, unrestricted_guest, CTLFLAG_RD, 187 &cap_unrestricted_guest, 0, "Unrestricted guests"); 188 189 static int cap_monitor_trap; 190 SYSCTL_INT(_hw_vmm_vmx_cap, OID_AUTO, monitor_trap, CTLFLAG_RD, 191 &cap_monitor_trap, 0, "Monitor trap flag"); 192 193 static int cap_invpcid; 194 SYSCTL_INT(_hw_vmm_vmx_cap, OID_AUTO, invpcid, CTLFLAG_RD, &cap_invpcid, 195 0, "Guests are allowed to use INVPCID"); 196 197 static int tpr_shadowing; 198 SYSCTL_INT(_hw_vmm_vmx_cap, OID_AUTO, tpr_shadowing, 199 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, 200 &tpr_shadowing, 0, "TPR shadowing support"); 201 202 static int virtual_interrupt_delivery; 203 SYSCTL_INT(_hw_vmm_vmx_cap, OID_AUTO, virtual_interrupt_delivery, 204 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, 205 &virtual_interrupt_delivery, 0, "APICv virtual interrupt delivery support"); 206 207 static int posted_interrupts; 208 SYSCTL_INT(_hw_vmm_vmx_cap, OID_AUTO, posted_interrupts, 209 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, 210 &posted_interrupts, 0, "APICv posted interrupt support"); 211 212 static int pirvec = -1; 213 SYSCTL_INT(_hw_vmm_vmx, OID_AUTO, posted_interrupt_vector, CTLFLAG_RD, 214 &pirvec, 0, "APICv posted interrupt vector"); 215 216 static struct unrhdr *vpid_unr; 217 static u_int vpid_alloc_failed; 218 SYSCTL_UINT(_hw_vmm_vmx, OID_AUTO, vpid_alloc_failed, CTLFLAG_RD, 219 &vpid_alloc_failed, 0, NULL); 220 221 int guest_l1d_flush; 222 SYSCTL_INT(_hw_vmm_vmx, OID_AUTO, l1d_flush, CTLFLAG_RDTUN | CTLFLAG_NOFETCH, 223 &guest_l1d_flush, 0, NULL); 224 int guest_l1d_flush_sw; 225 SYSCTL_INT(_hw_vmm_vmx, OID_AUTO, l1d_flush_sw, CTLFLAG_RDTUN | CTLFLAG_NOFETCH, 226 &guest_l1d_flush_sw, 0, NULL); 227 228 static struct msr_entry msr_load_list[1] __aligned(16); 229 230 /* 231 * The definitions of SDT probes for VMX. 232 */ 233 234 SDT_PROBE_DEFINE3(vmm, vmx, exit, entry, 235 "struct vmx *", "int", "struct vm_exit *"); 236 237 SDT_PROBE_DEFINE4(vmm, vmx, exit, taskswitch, 238 "struct vmx *", "int", "struct vm_exit *", "struct vm_task_switch *"); 239 240 SDT_PROBE_DEFINE4(vmm, vmx, exit, craccess, 241 "struct vmx *", "int", "struct vm_exit *", "uint64_t"); 242 243 SDT_PROBE_DEFINE4(vmm, vmx, exit, rdmsr, 244 "struct vmx *", "int", "struct vm_exit *", "uint32_t"); 245 246 SDT_PROBE_DEFINE5(vmm, vmx, exit, wrmsr, 247 "struct vmx *", "int", "struct vm_exit *", "uint32_t", "uint64_t"); 248 249 SDT_PROBE_DEFINE3(vmm, vmx, exit, halt, 250 "struct vmx *", "int", "struct vm_exit *"); 251 252 SDT_PROBE_DEFINE3(vmm, vmx, exit, mtrap, 253 "struct vmx *", "int", "struct vm_exit *"); 254 255 SDT_PROBE_DEFINE3(vmm, vmx, exit, pause, 256 "struct vmx *", "int", "struct vm_exit *"); 257 258 SDT_PROBE_DEFINE3(vmm, vmx, exit, intrwindow, 259 "struct vmx *", "int", "struct vm_exit *"); 260 261 SDT_PROBE_DEFINE4(vmm, vmx, exit, interrupt, 262 "struct vmx *", "int", "struct vm_exit *", "uint32_t"); 263 264 SDT_PROBE_DEFINE3(vmm, vmx, exit, nmiwindow, 265 "struct vmx *", "int", "struct vm_exit *"); 266 267 SDT_PROBE_DEFINE3(vmm, vmx, exit, inout, 268 "struct vmx *", "int", "struct vm_exit *"); 269 270 SDT_PROBE_DEFINE3(vmm, vmx, exit, cpuid, 271 "struct vmx *", "int", "struct vm_exit *"); 272 273 SDT_PROBE_DEFINE5(vmm, vmx, exit, exception, 274 "struct vmx *", "int", "struct vm_exit *", "uint32_t", "int"); 275 276 SDT_PROBE_DEFINE5(vmm, vmx, exit, nestedfault, 277 "struct vmx *", "int", "struct vm_exit *", "uint64_t", "uint64_t"); 278 279 SDT_PROBE_DEFINE4(vmm, vmx, exit, mmiofault, 280 "struct vmx *", "int", "struct vm_exit *", "uint64_t"); 281 282 SDT_PROBE_DEFINE3(vmm, vmx, exit, eoi, 283 "struct vmx *", "int", "struct vm_exit *"); 284 285 SDT_PROBE_DEFINE3(vmm, vmx, exit, apicaccess, 286 "struct vmx *", "int", "struct vm_exit *"); 287 288 SDT_PROBE_DEFINE4(vmm, vmx, exit, apicwrite, 289 "struct vmx *", "int", "struct vm_exit *", "struct vlapic *"); 290 291 SDT_PROBE_DEFINE3(vmm, vmx, exit, xsetbv, 292 "struct vmx *", "int", "struct vm_exit *"); 293 294 SDT_PROBE_DEFINE3(vmm, vmx, exit, monitor, 295 "struct vmx *", "int", "struct vm_exit *"); 296 297 SDT_PROBE_DEFINE3(vmm, vmx, exit, mwait, 298 "struct vmx *", "int", "struct vm_exit *"); 299 300 SDT_PROBE_DEFINE3(vmm, vmx, exit, vminsn, 301 "struct vmx *", "int", "struct vm_exit *"); 302 303 SDT_PROBE_DEFINE4(vmm, vmx, exit, unknown, 304 "struct vmx *", "int", "struct vm_exit *", "uint32_t"); 305 306 SDT_PROBE_DEFINE4(vmm, vmx, exit, return, 307 "struct vmx *", "int", "struct vm_exit *", "int"); 308 309 /* 310 * Use the last page below 4GB as the APIC access address. This address is 311 * occupied by the boot firmware so it is guaranteed that it will not conflict 312 * with a page in system memory. 313 */ 314 #define APIC_ACCESS_ADDRESS 0xFFFFF000 315 316 static int vmx_getdesc(void *vcpui, int reg, struct seg_desc *desc); 317 static int vmx_getreg(void *vcpui, int reg, uint64_t *retval); 318 static int vmxctx_setreg(struct vmxctx *vmxctx, int reg, uint64_t val); 319 static void vmx_inject_pir(struct vlapic *vlapic); 320 #ifdef BHYVE_SNAPSHOT 321 static int vmx_restore_tsc(void *vcpui, uint64_t now); 322 #endif 323 324 static inline bool 325 host_has_rdpid(void) 326 { 327 return ((cpu_stdext_feature2 & CPUID_STDEXT2_RDPID) != 0); 328 } 329 330 static inline bool 331 host_has_rdtscp(void) 332 { 333 return ((amd_feature & AMDID_RDTSCP) != 0); 334 } 335 336 #ifdef KTR 337 static const char * 338 exit_reason_to_str(int reason) 339 { 340 static char reasonbuf[32]; 341 342 switch (reason) { 343 case EXIT_REASON_EXCEPTION: 344 return "exception"; 345 case EXIT_REASON_EXT_INTR: 346 return "extint"; 347 case EXIT_REASON_TRIPLE_FAULT: 348 return "triplefault"; 349 case EXIT_REASON_INIT: 350 return "init"; 351 case EXIT_REASON_SIPI: 352 return "sipi"; 353 case EXIT_REASON_IO_SMI: 354 return "iosmi"; 355 case EXIT_REASON_SMI: 356 return "smi"; 357 case EXIT_REASON_INTR_WINDOW: 358 return "intrwindow"; 359 case EXIT_REASON_NMI_WINDOW: 360 return "nmiwindow"; 361 case EXIT_REASON_TASK_SWITCH: 362 return "taskswitch"; 363 case EXIT_REASON_CPUID: 364 return "cpuid"; 365 case EXIT_REASON_GETSEC: 366 return "getsec"; 367 case EXIT_REASON_HLT: 368 return "hlt"; 369 case EXIT_REASON_INVD: 370 return "invd"; 371 case EXIT_REASON_INVLPG: 372 return "invlpg"; 373 case EXIT_REASON_RDPMC: 374 return "rdpmc"; 375 case EXIT_REASON_RDTSC: 376 return "rdtsc"; 377 case EXIT_REASON_RSM: 378 return "rsm"; 379 case EXIT_REASON_VMCALL: 380 return "vmcall"; 381 case EXIT_REASON_VMCLEAR: 382 return "vmclear"; 383 case EXIT_REASON_VMLAUNCH: 384 return "vmlaunch"; 385 case EXIT_REASON_VMPTRLD: 386 return "vmptrld"; 387 case EXIT_REASON_VMPTRST: 388 return "vmptrst"; 389 case EXIT_REASON_VMREAD: 390 return "vmread"; 391 case EXIT_REASON_VMRESUME: 392 return "vmresume"; 393 case EXIT_REASON_VMWRITE: 394 return "vmwrite"; 395 case EXIT_REASON_VMXOFF: 396 return "vmxoff"; 397 case EXIT_REASON_VMXON: 398 return "vmxon"; 399 case EXIT_REASON_CR_ACCESS: 400 return "craccess"; 401 case EXIT_REASON_DR_ACCESS: 402 return "draccess"; 403 case EXIT_REASON_INOUT: 404 return "inout"; 405 case EXIT_REASON_RDMSR: 406 return "rdmsr"; 407 case EXIT_REASON_WRMSR: 408 return "wrmsr"; 409 case EXIT_REASON_INVAL_VMCS: 410 return "invalvmcs"; 411 case EXIT_REASON_INVAL_MSR: 412 return "invalmsr"; 413 case EXIT_REASON_MWAIT: 414 return "mwait"; 415 case EXIT_REASON_MTF: 416 return "mtf"; 417 case EXIT_REASON_MONITOR: 418 return "monitor"; 419 case EXIT_REASON_PAUSE: 420 return "pause"; 421 case EXIT_REASON_MCE_DURING_ENTRY: 422 return "mce-during-entry"; 423 case EXIT_REASON_TPR: 424 return "tpr"; 425 case EXIT_REASON_APIC_ACCESS: 426 return "apic-access"; 427 case EXIT_REASON_GDTR_IDTR: 428 return "gdtridtr"; 429 case EXIT_REASON_LDTR_TR: 430 return "ldtrtr"; 431 case EXIT_REASON_EPT_FAULT: 432 return "eptfault"; 433 case EXIT_REASON_EPT_MISCONFIG: 434 return "eptmisconfig"; 435 case EXIT_REASON_INVEPT: 436 return "invept"; 437 case EXIT_REASON_RDTSCP: 438 return "rdtscp"; 439 case EXIT_REASON_VMX_PREEMPT: 440 return "vmxpreempt"; 441 case EXIT_REASON_INVVPID: 442 return "invvpid"; 443 case EXIT_REASON_WBINVD: 444 return "wbinvd"; 445 case EXIT_REASON_XSETBV: 446 return "xsetbv"; 447 case EXIT_REASON_APIC_WRITE: 448 return "apic-write"; 449 default: 450 snprintf(reasonbuf, sizeof(reasonbuf), "%d", reason); 451 return (reasonbuf); 452 } 453 } 454 #endif /* KTR */ 455 456 static int 457 vmx_allow_x2apic_msrs(struct vmx *vmx) 458 { 459 int i, error; 460 461 error = 0; 462 463 /* 464 * Allow readonly access to the following x2APIC MSRs from the guest. 465 */ 466 error += guest_msr_ro(vmx, MSR_APIC_ID); 467 error += guest_msr_ro(vmx, MSR_APIC_VERSION); 468 error += guest_msr_ro(vmx, MSR_APIC_LDR); 469 error += guest_msr_ro(vmx, MSR_APIC_SVR); 470 471 for (i = 0; i < 8; i++) 472 error += guest_msr_ro(vmx, MSR_APIC_ISR0 + i); 473 474 for (i = 0; i < 8; i++) 475 error += guest_msr_ro(vmx, MSR_APIC_TMR0 + i); 476 477 for (i = 0; i < 8; i++) 478 error += guest_msr_ro(vmx, MSR_APIC_IRR0 + i); 479 480 error += guest_msr_ro(vmx, MSR_APIC_ESR); 481 error += guest_msr_ro(vmx, MSR_APIC_LVT_TIMER); 482 error += guest_msr_ro(vmx, MSR_APIC_LVT_THERMAL); 483 error += guest_msr_ro(vmx, MSR_APIC_LVT_PCINT); 484 error += guest_msr_ro(vmx, MSR_APIC_LVT_LINT0); 485 error += guest_msr_ro(vmx, MSR_APIC_LVT_LINT1); 486 error += guest_msr_ro(vmx, MSR_APIC_LVT_ERROR); 487 error += guest_msr_ro(vmx, MSR_APIC_ICR_TIMER); 488 error += guest_msr_ro(vmx, MSR_APIC_DCR_TIMER); 489 error += guest_msr_ro(vmx, MSR_APIC_ICR); 490 491 /* 492 * Allow TPR, EOI and SELF_IPI MSRs to be read and written by the guest. 493 * 494 * These registers get special treatment described in the section 495 * "Virtualizing MSR-Based APIC Accesses". 496 */ 497 error += guest_msr_rw(vmx, MSR_APIC_TPR); 498 error += guest_msr_rw(vmx, MSR_APIC_EOI); 499 error += guest_msr_rw(vmx, MSR_APIC_SELF_IPI); 500 501 return (error); 502 } 503 504 u_long 505 vmx_fix_cr0(u_long cr0) 506 { 507 508 return ((cr0 | cr0_ones_mask) & ~cr0_zeros_mask); 509 } 510 511 u_long 512 vmx_fix_cr4(u_long cr4) 513 { 514 515 return ((cr4 | cr4_ones_mask) & ~cr4_zeros_mask); 516 } 517 518 static void 519 vpid_free(int vpid) 520 { 521 if (vpid < 0 || vpid > 0xffff) 522 panic("vpid_free: invalid vpid %d", vpid); 523 524 /* 525 * VPIDs [0,vm_maxcpu] are special and are not allocated from 526 * the unit number allocator. 527 */ 528 529 if (vpid > vm_maxcpu) 530 free_unr(vpid_unr, vpid); 531 } 532 533 static uint16_t 534 vpid_alloc(int vcpuid) 535 { 536 int x; 537 538 /* 539 * If the "enable vpid" execution control is not enabled then the 540 * VPID is required to be 0 for all vcpus. 541 */ 542 if ((procbased_ctls2 & PROCBASED2_ENABLE_VPID) == 0) 543 return (0); 544 545 /* 546 * Try to allocate a unique VPID for each from the unit number 547 * allocator. 548 */ 549 x = alloc_unr(vpid_unr); 550 551 if (x == -1) { 552 atomic_add_int(&vpid_alloc_failed, 1); 553 554 /* 555 * If the unit number allocator does not have enough unique 556 * VPIDs then we need to allocate from the [1,vm_maxcpu] range. 557 * 558 * These VPIDs are not be unique across VMs but this does not 559 * affect correctness because the combined mappings are also 560 * tagged with the EP4TA which is unique for each VM. 561 * 562 * It is still sub-optimal because the invvpid will invalidate 563 * combined mappings for a particular VPID across all EP4TAs. 564 */ 565 return (vcpuid + 1); 566 } 567 568 return (x); 569 } 570 571 static void 572 vpid_init(void) 573 { 574 /* 575 * VPID 0 is required when the "enable VPID" execution control is 576 * disabled. 577 * 578 * VPIDs [1,vm_maxcpu] are used as the "overflow namespace" when the 579 * unit number allocator does not have sufficient unique VPIDs to 580 * satisfy the allocation. 581 * 582 * The remaining VPIDs are managed by the unit number allocator. 583 */ 584 vpid_unr = new_unrhdr(vm_maxcpu + 1, 0xffff, NULL); 585 } 586 587 static void 588 vmx_disable(void *arg __unused) 589 { 590 struct invvpid_desc invvpid_desc = { 0 }; 591 struct invept_desc invept_desc = { 0 }; 592 593 if (vmxon_enabled[curcpu]) { 594 /* 595 * See sections 25.3.3.3 and 25.3.3.4 in Intel Vol 3b. 596 * 597 * VMXON or VMXOFF are not required to invalidate any TLB 598 * caching structures. This prevents potential retention of 599 * cached information in the TLB between distinct VMX episodes. 600 */ 601 invvpid(INVVPID_TYPE_ALL_CONTEXTS, invvpid_desc); 602 invept(INVEPT_TYPE_ALL_CONTEXTS, invept_desc); 603 vmxoff(); 604 } 605 load_cr4(rcr4() & ~CR4_VMXE); 606 } 607 608 static int 609 vmx_modcleanup(void) 610 { 611 612 if (pirvec >= 0) 613 lapic_ipi_free(pirvec); 614 615 if (vpid_unr != NULL) { 616 delete_unrhdr(vpid_unr); 617 vpid_unr = NULL; 618 } 619 620 if (nmi_flush_l1d_sw == 1) 621 nmi_flush_l1d_sw = 0; 622 623 smp_rendezvous(NULL, vmx_disable, NULL, NULL); 624 625 if (vmxon_region != NULL) 626 kmem_free(vmxon_region, (mp_maxid + 1) * PAGE_SIZE); 627 628 return (0); 629 } 630 631 static void 632 vmx_enable(void *arg __unused) 633 { 634 int error; 635 uint64_t feature_control; 636 637 feature_control = rdmsr(MSR_IA32_FEATURE_CONTROL); 638 if ((feature_control & IA32_FEATURE_CONTROL_LOCK) == 0 || 639 (feature_control & IA32_FEATURE_CONTROL_VMX_EN) == 0) { 640 wrmsr(MSR_IA32_FEATURE_CONTROL, 641 feature_control | IA32_FEATURE_CONTROL_VMX_EN | 642 IA32_FEATURE_CONTROL_LOCK); 643 } 644 645 load_cr4(rcr4() | CR4_VMXE); 646 647 *(uint32_t *)&vmxon_region[curcpu * PAGE_SIZE] = vmx_revision(); 648 error = vmxon(&vmxon_region[curcpu * PAGE_SIZE]); 649 if (error == 0) 650 vmxon_enabled[curcpu] = 1; 651 } 652 653 static void 654 vmx_modsuspend(void) 655 { 656 657 if (vmxon_enabled[curcpu]) 658 vmx_disable(NULL); 659 } 660 661 static void 662 vmx_modresume(void) 663 { 664 665 if (vmxon_enabled[curcpu]) 666 vmx_enable(NULL); 667 } 668 669 static int 670 vmx_modinit(int ipinum) 671 { 672 int error; 673 uint64_t basic, fixed0, fixed1, feature_control; 674 uint32_t tmp, procbased2_vid_bits; 675 676 /* CPUID.1:ECX[bit 5] must be 1 for processor to support VMX */ 677 if (!(cpu_feature2 & CPUID2_VMX)) { 678 printf("vmx_modinit: processor does not support VMX " 679 "operation\n"); 680 return (ENXIO); 681 } 682 683 /* 684 * Verify that MSR_IA32_FEATURE_CONTROL lock and VMXON enable bits 685 * are set (bits 0 and 2 respectively). 686 */ 687 feature_control = rdmsr(MSR_IA32_FEATURE_CONTROL); 688 if ((feature_control & IA32_FEATURE_CONTROL_LOCK) == 1 && 689 (feature_control & IA32_FEATURE_CONTROL_VMX_EN) == 0) { 690 printf("vmx_modinit: VMX operation disabled by BIOS\n"); 691 return (ENXIO); 692 } 693 694 /* 695 * Verify capabilities MSR_VMX_BASIC: 696 * - bit 54 indicates support for INS/OUTS decoding 697 */ 698 basic = rdmsr(MSR_VMX_BASIC); 699 if ((basic & (1UL << 54)) == 0) { 700 printf("vmx_modinit: processor does not support desired basic " 701 "capabilities\n"); 702 return (EINVAL); 703 } 704 705 /* Check support for primary processor-based VM-execution controls */ 706 error = vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS, 707 MSR_VMX_TRUE_PROCBASED_CTLS, 708 PROCBASED_CTLS_ONE_SETTING, 709 PROCBASED_CTLS_ZERO_SETTING, &procbased_ctls); 710 if (error) { 711 printf("vmx_modinit: processor does not support desired " 712 "primary processor-based controls\n"); 713 return (error); 714 } 715 716 /* Clear the processor-based ctl bits that are set on demand */ 717 procbased_ctls &= ~PROCBASED_CTLS_WINDOW_SETTING; 718 719 /* Check support for secondary processor-based VM-execution controls */ 720 error = vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS2, 721 MSR_VMX_PROCBASED_CTLS2, 722 PROCBASED_CTLS2_ONE_SETTING, 723 PROCBASED_CTLS2_ZERO_SETTING, &procbased_ctls2); 724 if (error) { 725 printf("vmx_modinit: processor does not support desired " 726 "secondary processor-based controls\n"); 727 return (error); 728 } 729 730 /* Check support for VPID */ 731 error = vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS2, MSR_VMX_PROCBASED_CTLS2, 732 PROCBASED2_ENABLE_VPID, 0, &tmp); 733 if (error == 0) 734 procbased_ctls2 |= PROCBASED2_ENABLE_VPID; 735 736 /* Check support for pin-based VM-execution controls */ 737 error = vmx_set_ctlreg(MSR_VMX_PINBASED_CTLS, 738 MSR_VMX_TRUE_PINBASED_CTLS, 739 PINBASED_CTLS_ONE_SETTING, 740 PINBASED_CTLS_ZERO_SETTING, &pinbased_ctls); 741 if (error) { 742 printf("vmx_modinit: processor does not support desired " 743 "pin-based controls\n"); 744 return (error); 745 } 746 747 /* Check support for VM-exit controls */ 748 error = vmx_set_ctlreg(MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS, 749 VM_EXIT_CTLS_ONE_SETTING, 750 VM_EXIT_CTLS_ZERO_SETTING, 751 &exit_ctls); 752 if (error) { 753 printf("vmx_modinit: processor does not support desired " 754 "exit controls\n"); 755 return (error); 756 } 757 758 /* Check support for VM-entry controls */ 759 error = vmx_set_ctlreg(MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS, 760 VM_ENTRY_CTLS_ONE_SETTING, VM_ENTRY_CTLS_ZERO_SETTING, 761 &entry_ctls); 762 if (error) { 763 printf("vmx_modinit: processor does not support desired " 764 "entry controls\n"); 765 return (error); 766 } 767 768 /* 769 * Check support for optional features by testing them 770 * as individual bits 771 */ 772 cap_halt_exit = (vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS, 773 MSR_VMX_TRUE_PROCBASED_CTLS, 774 PROCBASED_HLT_EXITING, 0, 775 &tmp) == 0); 776 777 cap_monitor_trap = (vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS, 778 MSR_VMX_PROCBASED_CTLS, 779 PROCBASED_MTF, 0, 780 &tmp) == 0); 781 782 cap_pause_exit = (vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS, 783 MSR_VMX_TRUE_PROCBASED_CTLS, 784 PROCBASED_PAUSE_EXITING, 0, 785 &tmp) == 0); 786 787 cap_wbinvd_exit = (vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS2, 788 MSR_VMX_PROCBASED_CTLS2, 789 PROCBASED2_WBINVD_EXITING, 790 0, 791 &tmp) == 0); 792 793 /* 794 * Check support for RDPID and/or RDTSCP. 795 * 796 * Support a pass-through-based implementation of these via the 797 * "enable RDTSCP" VM-execution control and the "RDTSC exiting" 798 * VM-execution control. 799 * 800 * The "enable RDTSCP" VM-execution control applies to both RDPID 801 * and RDTSCP (see SDM volume 3, section 25.3, "Changes to 802 * Instruction Behavior in VMX Non-root operation"); this is why 803 * only this VM-execution control needs to be enabled in order to 804 * enable passing through whichever of RDPID and/or RDTSCP are 805 * supported by the host. 806 * 807 * The "RDTSC exiting" VM-execution control applies to both RDTSC 808 * and RDTSCP (again, per SDM volume 3, section 25.3), and is 809 * already set up for RDTSC and RDTSCP pass-through by the current 810 * implementation of RDTSC. 811 * 812 * Although RDPID and RDTSCP are optional capabilities, since there 813 * does not currently seem to be a use case for enabling/disabling 814 * these via libvmmapi, choose not to support this and, instead, 815 * just statically always enable or always disable this support 816 * across all vCPUs on all VMs. (Note that there may be some 817 * complications to providing this functionality, e.g., the MSR 818 * bitmap is currently per-VM rather than per-vCPU while the 819 * capability API wants to be able to control capabilities on a 820 * per-vCPU basis). 821 */ 822 error = vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS2, 823 MSR_VMX_PROCBASED_CTLS2, 824 PROCBASED2_ENABLE_RDTSCP, 0, &tmp); 825 cap_rdpid = error == 0 && host_has_rdpid(); 826 cap_rdtscp = error == 0 && host_has_rdtscp(); 827 if (cap_rdpid || cap_rdtscp) { 828 procbased_ctls2 |= PROCBASED2_ENABLE_RDTSCP; 829 vmx_have_msr_tsc_aux = true; 830 } 831 832 cap_unrestricted_guest = (vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS2, 833 MSR_VMX_PROCBASED_CTLS2, 834 PROCBASED2_UNRESTRICTED_GUEST, 0, 835 &tmp) == 0); 836 837 cap_invpcid = (vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS2, 838 MSR_VMX_PROCBASED_CTLS2, PROCBASED2_ENABLE_INVPCID, 0, 839 &tmp) == 0); 840 841 /* 842 * Check support for TPR shadow. 843 */ 844 error = vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS, 845 MSR_VMX_TRUE_PROCBASED_CTLS, PROCBASED_USE_TPR_SHADOW, 0, 846 &tmp); 847 if (error == 0) { 848 tpr_shadowing = 1; 849 #ifndef BURN_BRIDGES 850 TUNABLE_INT_FETCH("hw.vmm.vmx.use_tpr_shadowing", 851 &tpr_shadowing); 852 #endif 853 TUNABLE_INT_FETCH("hw.vmm.vmx.cap.tpr_shadowing", 854 &tpr_shadowing); 855 } 856 857 if (tpr_shadowing) { 858 procbased_ctls |= PROCBASED_USE_TPR_SHADOW; 859 procbased_ctls &= ~PROCBASED_CR8_LOAD_EXITING; 860 procbased_ctls &= ~PROCBASED_CR8_STORE_EXITING; 861 } 862 863 /* 864 * Check support for virtual interrupt delivery. 865 */ 866 procbased2_vid_bits = (PROCBASED2_VIRTUALIZE_APIC_ACCESSES | 867 PROCBASED2_VIRTUALIZE_X2APIC_MODE | 868 PROCBASED2_APIC_REGISTER_VIRTUALIZATION | 869 PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY); 870 871 error = vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS2, MSR_VMX_PROCBASED_CTLS2, 872 procbased2_vid_bits, 0, &tmp); 873 if (error == 0 && tpr_shadowing) { 874 virtual_interrupt_delivery = 1; 875 #ifndef BURN_BRIDGES 876 TUNABLE_INT_FETCH("hw.vmm.vmx.use_apic_vid", 877 &virtual_interrupt_delivery); 878 #endif 879 TUNABLE_INT_FETCH("hw.vmm.vmx.cap.virtual_interrupt_delivery", 880 &virtual_interrupt_delivery); 881 } 882 883 if (virtual_interrupt_delivery) { 884 procbased_ctls |= PROCBASED_USE_TPR_SHADOW; 885 procbased_ctls2 |= procbased2_vid_bits; 886 procbased_ctls2 &= ~PROCBASED2_VIRTUALIZE_X2APIC_MODE; 887 888 /* 889 * Check for Posted Interrupts only if Virtual Interrupt 890 * Delivery is enabled. 891 */ 892 error = vmx_set_ctlreg(MSR_VMX_PINBASED_CTLS, 893 MSR_VMX_TRUE_PINBASED_CTLS, PINBASED_POSTED_INTERRUPT, 0, 894 &tmp); 895 if (error == 0) { 896 pirvec = lapic_ipi_alloc(pti ? &IDTVEC(justreturn1_pti) : 897 &IDTVEC(justreturn), vmm_justreturn); 898 if (pirvec < 0) { 899 if (bootverbose) { 900 printf("vmx_modinit: unable to " 901 "allocate posted interrupt " 902 "vector\n"); 903 } 904 } else { 905 posted_interrupts = 1; 906 #ifndef BURN_BRIDGES 907 TUNABLE_INT_FETCH("hw.vmm.vmx.use_apic_pir", 908 &posted_interrupts); 909 #endif 910 TUNABLE_INT_FETCH("hw.vmm.vmx.cap.posted_interrupts", 911 &posted_interrupts); 912 } 913 } 914 } 915 916 if (posted_interrupts) 917 pinbased_ctls |= PINBASED_POSTED_INTERRUPT; 918 919 /* Initialize EPT */ 920 error = ept_init(ipinum); 921 if (error) { 922 printf("vmx_modinit: ept initialization failed (%d)\n", error); 923 return (error); 924 } 925 926 guest_l1d_flush = (cpu_ia32_arch_caps & 927 IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY) == 0; 928 #ifndef BURN_BRIDGES 929 TUNABLE_INT_FETCH("hw.vmm.l1d_flush", &guest_l1d_flush); 930 #endif 931 TUNABLE_INT_FETCH("hw.vmm.vmx.l1d_flush", &guest_l1d_flush); 932 933 /* 934 * L1D cache flush is enabled. Use IA32_FLUSH_CMD MSR when 935 * available. Otherwise fall back to the software flush 936 * method which loads enough data from the kernel text to 937 * flush existing L1D content, both on VMX entry and on NMI 938 * return. 939 */ 940 if (guest_l1d_flush) { 941 if ((cpu_stdext_feature3 & CPUID_STDEXT3_L1D_FLUSH) == 0) { 942 guest_l1d_flush_sw = 1; 943 #ifndef BURN_BRIDGES 944 TUNABLE_INT_FETCH("hw.vmm.l1d_flush_sw", 945 &guest_l1d_flush_sw); 946 #endif 947 TUNABLE_INT_FETCH("hw.vmm.vmx.l1d_flush_sw", 948 &guest_l1d_flush_sw); 949 } 950 if (guest_l1d_flush_sw) { 951 if (nmi_flush_l1d_sw <= 1) 952 nmi_flush_l1d_sw = 1; 953 } else { 954 msr_load_list[0].index = MSR_IA32_FLUSH_CMD; 955 msr_load_list[0].val = IA32_FLUSH_CMD_L1D; 956 } 957 } 958 959 /* 960 * Stash the cr0 and cr4 bits that must be fixed to 0 or 1 961 */ 962 fixed0 = rdmsr(MSR_VMX_CR0_FIXED0); 963 fixed1 = rdmsr(MSR_VMX_CR0_FIXED1); 964 cr0_ones_mask = fixed0 & fixed1; 965 cr0_zeros_mask = ~fixed0 & ~fixed1; 966 967 /* 968 * CR0_PE and CR0_PG can be set to zero in VMX non-root operation 969 * if unrestricted guest execution is allowed. 970 */ 971 if (cap_unrestricted_guest) 972 cr0_ones_mask &= ~(CR0_PG | CR0_PE); 973 974 /* 975 * Do not allow the guest to set CR0_NW or CR0_CD. 976 */ 977 cr0_zeros_mask |= (CR0_NW | CR0_CD); 978 979 fixed0 = rdmsr(MSR_VMX_CR4_FIXED0); 980 fixed1 = rdmsr(MSR_VMX_CR4_FIXED1); 981 cr4_ones_mask = fixed0 & fixed1; 982 cr4_zeros_mask = ~fixed0 & ~fixed1; 983 984 vpid_init(); 985 986 vmx_msr_init(); 987 988 /* enable VMX operation */ 989 vmxon_region = kmem_malloc((mp_maxid + 1) * PAGE_SIZE, 990 M_WAITOK | M_ZERO); 991 smp_rendezvous(NULL, vmx_enable, NULL, NULL); 992 993 vmx_initialized = 1; 994 995 return (0); 996 } 997 998 static void 999 vmx_trigger_hostintr(int vector) 1000 { 1001 uintptr_t func; 1002 struct gate_descriptor *gd; 1003 1004 gd = &idt[vector]; 1005 1006 KASSERT(vector >= 32 && vector <= 255, ("vmx_trigger_hostintr: " 1007 "invalid vector %d", vector)); 1008 KASSERT(gd->gd_p == 1, ("gate descriptor for vector %d not present", 1009 vector)); 1010 KASSERT(gd->gd_type == SDT_SYSIGT, ("gate descriptor for vector %d " 1011 "has invalid type %d", vector, gd->gd_type)); 1012 KASSERT(gd->gd_dpl == SEL_KPL, ("gate descriptor for vector %d " 1013 "has invalid dpl %d", vector, gd->gd_dpl)); 1014 KASSERT(gd->gd_selector == GSEL(GCODE_SEL, SEL_KPL), ("gate descriptor " 1015 "for vector %d has invalid selector %d", vector, gd->gd_selector)); 1016 KASSERT(gd->gd_ist == 0, ("gate descriptor for vector %d has invalid " 1017 "IST %d", vector, gd->gd_ist)); 1018 1019 func = ((long)gd->gd_hioffset << 16 | gd->gd_looffset); 1020 vmx_call_isr(func); 1021 } 1022 1023 static int 1024 vmx_setup_cr_shadow(int which, struct vmcs *vmcs, uint32_t initial) 1025 { 1026 int error, mask_ident, shadow_ident; 1027 uint64_t mask_value; 1028 1029 if (which != 0 && which != 4) 1030 panic("vmx_setup_cr_shadow: unknown cr%d", which); 1031 1032 if (which == 0) { 1033 mask_ident = VMCS_CR0_MASK; 1034 mask_value = cr0_ones_mask | cr0_zeros_mask; 1035 shadow_ident = VMCS_CR0_SHADOW; 1036 } else { 1037 mask_ident = VMCS_CR4_MASK; 1038 mask_value = cr4_ones_mask | cr4_zeros_mask; 1039 shadow_ident = VMCS_CR4_SHADOW; 1040 } 1041 1042 error = vmcs_setreg(vmcs, 0, VMCS_IDENT(mask_ident), mask_value); 1043 if (error) 1044 return (error); 1045 1046 error = vmcs_setreg(vmcs, 0, VMCS_IDENT(shadow_ident), initial); 1047 if (error) 1048 return (error); 1049 1050 return (0); 1051 } 1052 #define vmx_setup_cr0_shadow(vmcs,init) vmx_setup_cr_shadow(0, (vmcs), (init)) 1053 #define vmx_setup_cr4_shadow(vmcs,init) vmx_setup_cr_shadow(4, (vmcs), (init)) 1054 1055 static void * 1056 vmx_init(struct vm *vm, pmap_t pmap) 1057 { 1058 int error __diagused; 1059 struct vmx *vmx; 1060 1061 vmx = malloc(sizeof(struct vmx), M_VMX, M_WAITOK | M_ZERO); 1062 vmx->vm = vm; 1063 1064 vmx->eptp = eptp(vtophys((vm_offset_t)pmap->pm_pmltop)); 1065 1066 /* 1067 * Clean up EPTP-tagged guest physical and combined mappings 1068 * 1069 * VMX transitions are not required to invalidate any guest physical 1070 * mappings. So, it may be possible for stale guest physical mappings 1071 * to be present in the processor TLBs. 1072 * 1073 * Combined mappings for this EP4TA are also invalidated for all VPIDs. 1074 */ 1075 ept_invalidate_mappings(vmx->eptp); 1076 1077 vmx->msr_bitmap = malloc_aligned(PAGE_SIZE, PAGE_SIZE, M_VMX, 1078 M_WAITOK | M_ZERO); 1079 msr_bitmap_initialize(vmx->msr_bitmap); 1080 1081 /* 1082 * It is safe to allow direct access to MSR_GSBASE and MSR_FSBASE. 1083 * The guest FSBASE and GSBASE are saved and restored during 1084 * vm-exit and vm-entry respectively. The host FSBASE and GSBASE are 1085 * always restored from the vmcs host state area on vm-exit. 1086 * 1087 * The SYSENTER_CS/ESP/EIP MSRs are identical to FS/GSBASE in 1088 * how they are saved/restored so can be directly accessed by the 1089 * guest. 1090 * 1091 * MSR_EFER is saved and restored in the guest VMCS area on a 1092 * VM exit and entry respectively. It is also restored from the 1093 * host VMCS area on a VM exit. 1094 * 1095 * The TSC MSR is exposed read-only. Writes are disallowed as 1096 * that will impact the host TSC. If the guest does a write 1097 * the "use TSC offsetting" execution control is enabled and the 1098 * difference between the host TSC and the guest TSC is written 1099 * into the TSC offset in the VMCS. 1100 * 1101 * Guest TSC_AUX support is enabled if any of guest RDPID and/or 1102 * guest RDTSCP support are enabled (since, as per Table 2-2 in SDM 1103 * volume 4, TSC_AUX is supported if any of RDPID and/or RDTSCP are 1104 * supported). If guest TSC_AUX support is enabled, TSC_AUX is 1105 * exposed read-only so that the VMM can do one fewer MSR read per 1106 * exit than if this register were exposed read-write; the guest 1107 * restore value can be updated during guest writes (expected to be 1108 * rare) instead of during all exits (common). 1109 */ 1110 if (guest_msr_rw(vmx, MSR_GSBASE) || 1111 guest_msr_rw(vmx, MSR_FSBASE) || 1112 guest_msr_rw(vmx, MSR_SYSENTER_CS_MSR) || 1113 guest_msr_rw(vmx, MSR_SYSENTER_ESP_MSR) || 1114 guest_msr_rw(vmx, MSR_SYSENTER_EIP_MSR) || 1115 guest_msr_rw(vmx, MSR_EFER) || 1116 guest_msr_ro(vmx, MSR_TSC) || 1117 ((cap_rdpid || cap_rdtscp) && guest_msr_ro(vmx, MSR_TSC_AUX))) 1118 panic("vmx_init: error setting guest msr access"); 1119 1120 if (virtual_interrupt_delivery) { 1121 error = vm_map_mmio(vm, DEFAULT_APIC_BASE, PAGE_SIZE, 1122 APIC_ACCESS_ADDRESS); 1123 /* XXX this should really return an error to the caller */ 1124 KASSERT(error == 0, ("vm_map_mmio(apicbase) error %d", error)); 1125 } 1126 1127 vmx->pmap = pmap; 1128 return (vmx); 1129 } 1130 1131 static void * 1132 vmx_vcpu_init(void *vmi, struct vcpu *vcpu1, int vcpuid) 1133 { 1134 struct vmx *vmx = vmi; 1135 struct vmcs *vmcs; 1136 struct vmx_vcpu *vcpu; 1137 uint32_t exc_bitmap; 1138 uint16_t vpid; 1139 int error; 1140 1141 vpid = vpid_alloc(vcpuid); 1142 1143 vcpu = malloc(sizeof(*vcpu), M_VMX, M_WAITOK | M_ZERO); 1144 vcpu->vmx = vmx; 1145 vcpu->vcpu = vcpu1; 1146 vcpu->vcpuid = vcpuid; 1147 vcpu->vmcs = malloc_aligned(sizeof(*vmcs), PAGE_SIZE, M_VMX, 1148 M_WAITOK | M_ZERO); 1149 vcpu->apic_page = malloc_aligned(PAGE_SIZE, PAGE_SIZE, M_VMX, 1150 M_WAITOK | M_ZERO); 1151 vcpu->pir_desc = malloc_aligned(sizeof(*vcpu->pir_desc), 64, M_VMX, 1152 M_WAITOK | M_ZERO); 1153 1154 vmcs = vcpu->vmcs; 1155 vmcs->identifier = vmx_revision(); 1156 error = vmclear(vmcs); 1157 if (error != 0) { 1158 panic("vmx_init: vmclear error %d on vcpu %d\n", 1159 error, vcpuid); 1160 } 1161 1162 vmx_msr_guest_init(vmx, vcpu); 1163 1164 error = vmcs_init(vmcs); 1165 KASSERT(error == 0, ("vmcs_init error %d", error)); 1166 1167 VMPTRLD(vmcs); 1168 error = 0; 1169 error += vmwrite(VMCS_HOST_RSP, (u_long)&vcpu->ctx); 1170 error += vmwrite(VMCS_EPTP, vmx->eptp); 1171 error += vmwrite(VMCS_PIN_BASED_CTLS, pinbased_ctls); 1172 error += vmwrite(VMCS_PRI_PROC_BASED_CTLS, procbased_ctls); 1173 if (vcpu_trap_wbinvd(vcpu->vcpu)) { 1174 KASSERT(cap_wbinvd_exit, ("WBINVD trap not available")); 1175 procbased_ctls2 |= PROCBASED2_WBINVD_EXITING; 1176 } 1177 error += vmwrite(VMCS_SEC_PROC_BASED_CTLS, procbased_ctls2); 1178 error += vmwrite(VMCS_EXIT_CTLS, exit_ctls); 1179 error += vmwrite(VMCS_ENTRY_CTLS, entry_ctls); 1180 error += vmwrite(VMCS_MSR_BITMAP, vtophys(vmx->msr_bitmap)); 1181 error += vmwrite(VMCS_VPID, vpid); 1182 1183 if (guest_l1d_flush && !guest_l1d_flush_sw) { 1184 vmcs_write(VMCS_ENTRY_MSR_LOAD, pmap_kextract( 1185 (vm_offset_t)&msr_load_list[0])); 1186 vmcs_write(VMCS_ENTRY_MSR_LOAD_COUNT, 1187 nitems(msr_load_list)); 1188 vmcs_write(VMCS_EXIT_MSR_STORE, 0); 1189 vmcs_write(VMCS_EXIT_MSR_STORE_COUNT, 0); 1190 } 1191 1192 /* exception bitmap */ 1193 if (vcpu_trace_exceptions(vcpu->vcpu)) 1194 exc_bitmap = 0xffffffff; 1195 else 1196 exc_bitmap = 1 << IDT_MC; 1197 error += vmwrite(VMCS_EXCEPTION_BITMAP, exc_bitmap); 1198 1199 vcpu->ctx.guest_dr6 = DBREG_DR6_RESERVED1; 1200 error += vmwrite(VMCS_GUEST_DR7, DBREG_DR7_RESERVED1); 1201 1202 if (tpr_shadowing) { 1203 error += vmwrite(VMCS_VIRTUAL_APIC, vtophys(vcpu->apic_page)); 1204 } 1205 1206 if (virtual_interrupt_delivery) { 1207 error += vmwrite(VMCS_APIC_ACCESS, APIC_ACCESS_ADDRESS); 1208 error += vmwrite(VMCS_EOI_EXIT0, 0); 1209 error += vmwrite(VMCS_EOI_EXIT1, 0); 1210 error += vmwrite(VMCS_EOI_EXIT2, 0); 1211 error += vmwrite(VMCS_EOI_EXIT3, 0); 1212 } 1213 if (posted_interrupts) { 1214 error += vmwrite(VMCS_PIR_VECTOR, pirvec); 1215 error += vmwrite(VMCS_PIR_DESC, vtophys(vcpu->pir_desc)); 1216 } 1217 VMCLEAR(vmcs); 1218 KASSERT(error == 0, ("vmx_init: error customizing the vmcs")); 1219 1220 vcpu->cap.set = 0; 1221 vcpu->cap.set |= cap_rdpid != 0 ? 1 << VM_CAP_RDPID : 0; 1222 vcpu->cap.set |= cap_rdtscp != 0 ? 1 << VM_CAP_RDTSCP : 0; 1223 vcpu->cap.proc_ctls = procbased_ctls; 1224 vcpu->cap.proc_ctls2 = procbased_ctls2; 1225 vcpu->cap.exc_bitmap = exc_bitmap; 1226 1227 vcpu->state.nextrip = ~0; 1228 vcpu->state.lastcpu = NOCPU; 1229 vcpu->state.vpid = vpid; 1230 1231 /* 1232 * Set up the CR0/4 shadows, and init the read shadow 1233 * to the power-on register value from the Intel Sys Arch. 1234 * CR0 - 0x60000010 1235 * CR4 - 0 1236 */ 1237 error = vmx_setup_cr0_shadow(vmcs, 0x60000010); 1238 if (error != 0) 1239 panic("vmx_setup_cr0_shadow %d", error); 1240 1241 error = vmx_setup_cr4_shadow(vmcs, 0); 1242 if (error != 0) 1243 panic("vmx_setup_cr4_shadow %d", error); 1244 1245 vcpu->ctx.pmap = vmx->pmap; 1246 1247 return (vcpu); 1248 } 1249 1250 static int 1251 vmx_handle_cpuid(struct vmx_vcpu *vcpu, struct vmxctx *vmxctx) 1252 { 1253 int handled; 1254 1255 handled = x86_emulate_cpuid(vcpu->vcpu, (uint64_t *)&vmxctx->guest_rax, 1256 (uint64_t *)&vmxctx->guest_rbx, (uint64_t *)&vmxctx->guest_rcx, 1257 (uint64_t *)&vmxctx->guest_rdx); 1258 return (handled); 1259 } 1260 1261 static __inline void 1262 vmx_run_trace(struct vmx_vcpu *vcpu) 1263 { 1264 VMX_CTR1(vcpu, "Resume execution at %#lx", vmcs_guest_rip()); 1265 } 1266 1267 static __inline void 1268 vmx_exit_trace(struct vmx_vcpu *vcpu, uint64_t rip, uint32_t exit_reason, 1269 int handled) 1270 { 1271 VMX_CTR3(vcpu, "%s %s vmexit at 0x%0lx", 1272 handled ? "handled" : "unhandled", 1273 exit_reason_to_str(exit_reason), rip); 1274 } 1275 1276 static __inline void 1277 vmx_astpending_trace(struct vmx_vcpu *vcpu, uint64_t rip) 1278 { 1279 VMX_CTR1(vcpu, "astpending vmexit at 0x%0lx", rip); 1280 } 1281 1282 static VMM_STAT_INTEL(VCPU_INVVPID_SAVED, "Number of vpid invalidations saved"); 1283 static VMM_STAT_INTEL(VCPU_INVVPID_DONE, "Number of vpid invalidations done"); 1284 1285 /* 1286 * Invalidate guest mappings identified by its vpid from the TLB. 1287 */ 1288 static __inline void 1289 vmx_invvpid(struct vmx *vmx, struct vmx_vcpu *vcpu, pmap_t pmap, int running) 1290 { 1291 struct vmxstate *vmxstate; 1292 struct invvpid_desc invvpid_desc; 1293 1294 vmxstate = &vcpu->state; 1295 if (vmxstate->vpid == 0) 1296 return; 1297 1298 if (!running) { 1299 /* 1300 * Set the 'lastcpu' to an invalid host cpu. 1301 * 1302 * This will invalidate TLB entries tagged with the vcpu's 1303 * vpid the next time it runs via vmx_set_pcpu_defaults(). 1304 */ 1305 vmxstate->lastcpu = NOCPU; 1306 return; 1307 } 1308 1309 KASSERT(curthread->td_critnest > 0, ("%s: vcpu %d running outside " 1310 "critical section", __func__, vcpu->vcpuid)); 1311 1312 /* 1313 * Invalidate all mappings tagged with 'vpid' 1314 * 1315 * We do this because this vcpu was executing on a different host 1316 * cpu when it last ran. We do not track whether it invalidated 1317 * mappings associated with its 'vpid' during that run. So we must 1318 * assume that the mappings associated with 'vpid' on 'curcpu' are 1319 * stale and invalidate them. 1320 * 1321 * Note that we incur this penalty only when the scheduler chooses to 1322 * move the thread associated with this vcpu between host cpus. 1323 * 1324 * Note also that this will invalidate mappings tagged with 'vpid' 1325 * for "all" EP4TAs. 1326 */ 1327 if (atomic_load_long(&pmap->pm_eptgen) == vmx->eptgen[curcpu]) { 1328 invvpid_desc._res1 = 0; 1329 invvpid_desc._res2 = 0; 1330 invvpid_desc.vpid = vmxstate->vpid; 1331 invvpid_desc.linear_addr = 0; 1332 invvpid(INVVPID_TYPE_SINGLE_CONTEXT, invvpid_desc); 1333 vmm_stat_incr(vcpu->vcpu, VCPU_INVVPID_DONE, 1); 1334 } else { 1335 /* 1336 * The invvpid can be skipped if an invept is going to 1337 * be performed before entering the guest. The invept 1338 * will invalidate combined mappings tagged with 1339 * 'vmx->eptp' for all vpids. 1340 */ 1341 vmm_stat_incr(vcpu->vcpu, VCPU_INVVPID_SAVED, 1); 1342 } 1343 } 1344 1345 static void 1346 vmx_set_pcpu_defaults(struct vmx *vmx, struct vmx_vcpu *vcpu, pmap_t pmap) 1347 { 1348 struct vmxstate *vmxstate; 1349 1350 vmxstate = &vcpu->state; 1351 if (vmxstate->lastcpu == curcpu) 1352 return; 1353 1354 vmxstate->lastcpu = curcpu; 1355 1356 vmm_stat_incr(vcpu->vcpu, VCPU_MIGRATIONS, 1); 1357 1358 vmcs_write(VMCS_HOST_TR_BASE, vmm_get_host_trbase()); 1359 vmcs_write(VMCS_HOST_GDTR_BASE, vmm_get_host_gdtrbase()); 1360 vmcs_write(VMCS_HOST_GS_BASE, vmm_get_host_gsbase()); 1361 vmx_invvpid(vmx, vcpu, pmap, 1); 1362 } 1363 1364 /* 1365 * We depend on 'procbased_ctls' to have the Interrupt Window Exiting bit set. 1366 */ 1367 CTASSERT((PROCBASED_CTLS_ONE_SETTING & PROCBASED_INT_WINDOW_EXITING) != 0); 1368 1369 static void __inline 1370 vmx_set_int_window_exiting(struct vmx_vcpu *vcpu) 1371 { 1372 1373 if ((vcpu->cap.proc_ctls & PROCBASED_INT_WINDOW_EXITING) == 0) { 1374 vcpu->cap.proc_ctls |= PROCBASED_INT_WINDOW_EXITING; 1375 vmcs_write(VMCS_PRI_PROC_BASED_CTLS, vcpu->cap.proc_ctls); 1376 VMX_CTR0(vcpu, "Enabling interrupt window exiting"); 1377 } 1378 } 1379 1380 static void __inline 1381 vmx_clear_int_window_exiting(struct vmx_vcpu *vcpu) 1382 { 1383 1384 KASSERT((vcpu->cap.proc_ctls & PROCBASED_INT_WINDOW_EXITING) != 0, 1385 ("intr_window_exiting not set: %#x", vcpu->cap.proc_ctls)); 1386 vcpu->cap.proc_ctls &= ~PROCBASED_INT_WINDOW_EXITING; 1387 vmcs_write(VMCS_PRI_PROC_BASED_CTLS, vcpu->cap.proc_ctls); 1388 VMX_CTR0(vcpu, "Disabling interrupt window exiting"); 1389 } 1390 1391 static void __inline 1392 vmx_set_nmi_window_exiting(struct vmx_vcpu *vcpu) 1393 { 1394 1395 if ((vcpu->cap.proc_ctls & PROCBASED_NMI_WINDOW_EXITING) == 0) { 1396 vcpu->cap.proc_ctls |= PROCBASED_NMI_WINDOW_EXITING; 1397 vmcs_write(VMCS_PRI_PROC_BASED_CTLS, vcpu->cap.proc_ctls); 1398 VMX_CTR0(vcpu, "Enabling NMI window exiting"); 1399 } 1400 } 1401 1402 static void __inline 1403 vmx_clear_nmi_window_exiting(struct vmx_vcpu *vcpu) 1404 { 1405 1406 KASSERT((vcpu->cap.proc_ctls & PROCBASED_NMI_WINDOW_EXITING) != 0, 1407 ("nmi_window_exiting not set %#x", vcpu->cap.proc_ctls)); 1408 vcpu->cap.proc_ctls &= ~PROCBASED_NMI_WINDOW_EXITING; 1409 vmcs_write(VMCS_PRI_PROC_BASED_CTLS, vcpu->cap.proc_ctls); 1410 VMX_CTR0(vcpu, "Disabling NMI window exiting"); 1411 } 1412 1413 int 1414 vmx_set_tsc_offset(struct vmx_vcpu *vcpu, uint64_t offset) 1415 { 1416 int error; 1417 1418 if ((vcpu->cap.proc_ctls & PROCBASED_TSC_OFFSET) == 0) { 1419 vcpu->cap.proc_ctls |= PROCBASED_TSC_OFFSET; 1420 vmcs_write(VMCS_PRI_PROC_BASED_CTLS, vcpu->cap.proc_ctls); 1421 VMX_CTR0(vcpu, "Enabling TSC offsetting"); 1422 } 1423 1424 error = vmwrite(VMCS_TSC_OFFSET, offset); 1425 #ifdef BHYVE_SNAPSHOT 1426 if (error == 0) 1427 vm_set_tsc_offset(vcpu->vcpu, offset); 1428 #endif 1429 return (error); 1430 } 1431 1432 #define NMI_BLOCKING (VMCS_INTERRUPTIBILITY_NMI_BLOCKING | \ 1433 VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING) 1434 #define HWINTR_BLOCKING (VMCS_INTERRUPTIBILITY_STI_BLOCKING | \ 1435 VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING) 1436 1437 static void 1438 vmx_inject_nmi(struct vmx_vcpu *vcpu) 1439 { 1440 uint32_t gi __diagused, info; 1441 1442 gi = vmcs_read(VMCS_GUEST_INTERRUPTIBILITY); 1443 KASSERT((gi & NMI_BLOCKING) == 0, ("vmx_inject_nmi: invalid guest " 1444 "interruptibility-state %#x", gi)); 1445 1446 info = vmcs_read(VMCS_ENTRY_INTR_INFO); 1447 KASSERT((info & VMCS_INTR_VALID) == 0, ("vmx_inject_nmi: invalid " 1448 "VM-entry interruption information %#x", info)); 1449 1450 /* 1451 * Inject the virtual NMI. The vector must be the NMI IDT entry 1452 * or the VMCS entry check will fail. 1453 */ 1454 info = IDT_NMI | VMCS_INTR_T_NMI | VMCS_INTR_VALID; 1455 vmcs_write(VMCS_ENTRY_INTR_INFO, info); 1456 1457 VMX_CTR0(vcpu, "Injecting vNMI"); 1458 1459 /* Clear the request */ 1460 vm_nmi_clear(vcpu->vcpu); 1461 } 1462 1463 static void 1464 vmx_inject_interrupts(struct vmx_vcpu *vcpu, struct vlapic *vlapic, 1465 uint64_t guestrip) 1466 { 1467 int vector, need_nmi_exiting, extint_pending; 1468 uint64_t rflags, entryinfo; 1469 uint32_t gi, info; 1470 1471 if (vcpu->cap.set & (1 << VM_CAP_MASK_HWINTR)) { 1472 return; 1473 } 1474 1475 if (vcpu->state.nextrip != guestrip) { 1476 gi = vmcs_read(VMCS_GUEST_INTERRUPTIBILITY); 1477 if (gi & HWINTR_BLOCKING) { 1478 VMX_CTR2(vcpu, "Guest interrupt blocking " 1479 "cleared due to rip change: %#lx/%#lx", 1480 vcpu->state.nextrip, guestrip); 1481 gi &= ~HWINTR_BLOCKING; 1482 vmcs_write(VMCS_GUEST_INTERRUPTIBILITY, gi); 1483 } 1484 } 1485 1486 if (vm_entry_intinfo(vcpu->vcpu, &entryinfo)) { 1487 KASSERT((entryinfo & VMCS_INTR_VALID) != 0, ("%s: entry " 1488 "intinfo is not valid: %#lx", __func__, entryinfo)); 1489 1490 info = vmcs_read(VMCS_ENTRY_INTR_INFO); 1491 KASSERT((info & VMCS_INTR_VALID) == 0, ("%s: cannot inject " 1492 "pending exception: %#lx/%#x", __func__, entryinfo, info)); 1493 1494 info = entryinfo; 1495 vector = info & 0xff; 1496 if (vector == IDT_BP || vector == IDT_OF) { 1497 /* 1498 * VT-x requires #BP and #OF to be injected as software 1499 * exceptions. 1500 */ 1501 info &= ~VMCS_INTR_T_MASK; 1502 info |= VMCS_INTR_T_SWEXCEPTION; 1503 } 1504 1505 if (info & VMCS_INTR_DEL_ERRCODE) 1506 vmcs_write(VMCS_ENTRY_EXCEPTION_ERROR, entryinfo >> 32); 1507 1508 vmcs_write(VMCS_ENTRY_INTR_INFO, info); 1509 } 1510 1511 if (vm_nmi_pending(vcpu->vcpu)) { 1512 /* 1513 * If there are no conditions blocking NMI injection then 1514 * inject it directly here otherwise enable "NMI window 1515 * exiting" to inject it as soon as we can. 1516 * 1517 * We also check for STI_BLOCKING because some implementations 1518 * don't allow NMI injection in this case. If we are running 1519 * on a processor that doesn't have this restriction it will 1520 * immediately exit and the NMI will be injected in the 1521 * "NMI window exiting" handler. 1522 */ 1523 need_nmi_exiting = 1; 1524 gi = vmcs_read(VMCS_GUEST_INTERRUPTIBILITY); 1525 if ((gi & (HWINTR_BLOCKING | NMI_BLOCKING)) == 0) { 1526 info = vmcs_read(VMCS_ENTRY_INTR_INFO); 1527 if ((info & VMCS_INTR_VALID) == 0) { 1528 vmx_inject_nmi(vcpu); 1529 need_nmi_exiting = 0; 1530 } else { 1531 VMX_CTR1(vcpu, "Cannot inject NMI " 1532 "due to VM-entry intr info %#x", info); 1533 } 1534 } else { 1535 VMX_CTR1(vcpu, "Cannot inject NMI due to " 1536 "Guest Interruptibility-state %#x", gi); 1537 } 1538 1539 if (need_nmi_exiting) 1540 vmx_set_nmi_window_exiting(vcpu); 1541 } 1542 1543 extint_pending = vm_extint_pending(vcpu->vcpu); 1544 1545 if (!extint_pending && virtual_interrupt_delivery) { 1546 vmx_inject_pir(vlapic); 1547 return; 1548 } 1549 1550 /* 1551 * If interrupt-window exiting is already in effect then don't bother 1552 * checking for pending interrupts. This is just an optimization and 1553 * not needed for correctness. 1554 */ 1555 if ((vcpu->cap.proc_ctls & PROCBASED_INT_WINDOW_EXITING) != 0) { 1556 VMX_CTR0(vcpu, "Skip interrupt injection due to " 1557 "pending int_window_exiting"); 1558 return; 1559 } 1560 1561 if (!extint_pending) { 1562 /* Ask the local apic for a vector to inject */ 1563 if (!vlapic_pending_intr(vlapic, &vector)) 1564 return; 1565 1566 /* 1567 * From the Intel SDM, Volume 3, Section "Maskable 1568 * Hardware Interrupts": 1569 * - maskable interrupt vectors [16,255] can be delivered 1570 * through the local APIC. 1571 */ 1572 KASSERT(vector >= 16 && vector <= 255, 1573 ("invalid vector %d from local APIC", vector)); 1574 } else { 1575 /* Ask the legacy pic for a vector to inject */ 1576 vatpic_pending_intr(vcpu->vmx->vm, &vector); 1577 1578 /* 1579 * From the Intel SDM, Volume 3, Section "Maskable 1580 * Hardware Interrupts": 1581 * - maskable interrupt vectors [0,255] can be delivered 1582 * through the INTR pin. 1583 */ 1584 KASSERT(vector >= 0 && vector <= 255, 1585 ("invalid vector %d from INTR", vector)); 1586 } 1587 1588 /* Check RFLAGS.IF and the interruptibility state of the guest */ 1589 rflags = vmcs_read(VMCS_GUEST_RFLAGS); 1590 if ((rflags & PSL_I) == 0) { 1591 VMX_CTR2(vcpu, "Cannot inject vector %d due to " 1592 "rflags %#lx", vector, rflags); 1593 goto cantinject; 1594 } 1595 1596 gi = vmcs_read(VMCS_GUEST_INTERRUPTIBILITY); 1597 if (gi & HWINTR_BLOCKING) { 1598 VMX_CTR2(vcpu, "Cannot inject vector %d due to " 1599 "Guest Interruptibility-state %#x", vector, gi); 1600 goto cantinject; 1601 } 1602 1603 info = vmcs_read(VMCS_ENTRY_INTR_INFO); 1604 if (info & VMCS_INTR_VALID) { 1605 /* 1606 * This is expected and could happen for multiple reasons: 1607 * - A vectoring VM-entry was aborted due to astpending 1608 * - A VM-exit happened during event injection. 1609 * - An exception was injected above. 1610 * - An NMI was injected above or after "NMI window exiting" 1611 */ 1612 VMX_CTR2(vcpu, "Cannot inject vector %d due to " 1613 "VM-entry intr info %#x", vector, info); 1614 goto cantinject; 1615 } 1616 1617 /* Inject the interrupt */ 1618 info = VMCS_INTR_T_HWINTR | VMCS_INTR_VALID; 1619 info |= vector; 1620 vmcs_write(VMCS_ENTRY_INTR_INFO, info); 1621 1622 if (!extint_pending) { 1623 /* Update the Local APIC ISR */ 1624 vlapic_intr_accepted(vlapic, vector); 1625 } else { 1626 vm_extint_clear(vcpu->vcpu); 1627 vatpic_intr_accepted(vcpu->vmx->vm, vector); 1628 1629 /* 1630 * After we accepted the current ExtINT the PIC may 1631 * have posted another one. If that is the case, set 1632 * the Interrupt Window Exiting execution control so 1633 * we can inject that one too. 1634 * 1635 * Also, interrupt window exiting allows us to inject any 1636 * pending APIC vector that was preempted by the ExtINT 1637 * as soon as possible. This applies both for the software 1638 * emulated vlapic and the hardware assisted virtual APIC. 1639 */ 1640 vmx_set_int_window_exiting(vcpu); 1641 } 1642 1643 VMX_CTR1(vcpu, "Injecting hwintr at vector %d", vector); 1644 1645 return; 1646 1647 cantinject: 1648 /* 1649 * Set the Interrupt Window Exiting execution control so we can inject 1650 * the interrupt as soon as blocking condition goes away. 1651 */ 1652 vmx_set_int_window_exiting(vcpu); 1653 } 1654 1655 /* 1656 * If the Virtual NMIs execution control is '1' then the logical processor 1657 * tracks virtual-NMI blocking in the Guest Interruptibility-state field of 1658 * the VMCS. An IRET instruction in VMX non-root operation will remove any 1659 * virtual-NMI blocking. 1660 * 1661 * This unblocking occurs even if the IRET causes a fault. In this case the 1662 * hypervisor needs to restore virtual-NMI blocking before resuming the guest. 1663 */ 1664 static void 1665 vmx_restore_nmi_blocking(struct vmx_vcpu *vcpu) 1666 { 1667 uint32_t gi; 1668 1669 VMX_CTR0(vcpu, "Restore Virtual-NMI blocking"); 1670 gi = vmcs_read(VMCS_GUEST_INTERRUPTIBILITY); 1671 gi |= VMCS_INTERRUPTIBILITY_NMI_BLOCKING; 1672 vmcs_write(VMCS_GUEST_INTERRUPTIBILITY, gi); 1673 } 1674 1675 static void 1676 vmx_clear_nmi_blocking(struct vmx_vcpu *vcpu) 1677 { 1678 uint32_t gi; 1679 1680 VMX_CTR0(vcpu, "Clear Virtual-NMI blocking"); 1681 gi = vmcs_read(VMCS_GUEST_INTERRUPTIBILITY); 1682 gi &= ~VMCS_INTERRUPTIBILITY_NMI_BLOCKING; 1683 vmcs_write(VMCS_GUEST_INTERRUPTIBILITY, gi); 1684 } 1685 1686 static void 1687 vmx_assert_nmi_blocking(struct vmx_vcpu *vcpu) 1688 { 1689 uint32_t gi __diagused; 1690 1691 gi = vmcs_read(VMCS_GUEST_INTERRUPTIBILITY); 1692 KASSERT(gi & VMCS_INTERRUPTIBILITY_NMI_BLOCKING, 1693 ("NMI blocking is not in effect %#x", gi)); 1694 } 1695 1696 static int 1697 vmx_emulate_xsetbv(struct vmx *vmx, struct vmx_vcpu *vcpu, 1698 struct vm_exit *vmexit) 1699 { 1700 struct vmxctx *vmxctx; 1701 uint64_t xcrval; 1702 const struct xsave_limits *limits; 1703 1704 vmxctx = &vcpu->ctx; 1705 limits = vmm_get_xsave_limits(); 1706 1707 /* 1708 * Note that the processor raises a GP# fault on its own if 1709 * xsetbv is executed for CPL != 0, so we do not have to 1710 * emulate that fault here. 1711 */ 1712 1713 /* Only xcr0 is supported. */ 1714 if (vmxctx->guest_rcx != 0) { 1715 vm_inject_gp(vcpu->vcpu); 1716 return (HANDLED); 1717 } 1718 1719 /* We only handle xcr0 if both the host and guest have XSAVE enabled. */ 1720 if (!limits->xsave_enabled || !(vmcs_read(VMCS_GUEST_CR4) & CR4_XSAVE)) { 1721 vm_inject_ud(vcpu->vcpu); 1722 return (HANDLED); 1723 } 1724 1725 xcrval = vmxctx->guest_rdx << 32 | (vmxctx->guest_rax & 0xffffffff); 1726 if ((xcrval & ~limits->xcr0_allowed) != 0) { 1727 vm_inject_gp(vcpu->vcpu); 1728 return (HANDLED); 1729 } 1730 1731 if (!(xcrval & XFEATURE_ENABLED_X87)) { 1732 vm_inject_gp(vcpu->vcpu); 1733 return (HANDLED); 1734 } 1735 1736 /* AVX (YMM_Hi128) requires SSE. */ 1737 if (xcrval & XFEATURE_ENABLED_AVX && 1738 (xcrval & XFEATURE_AVX) != XFEATURE_AVX) { 1739 vm_inject_gp(vcpu->vcpu); 1740 return (HANDLED); 1741 } 1742 1743 /* 1744 * AVX512 requires base AVX (YMM_Hi128) as well as OpMask, 1745 * ZMM_Hi256, and Hi16_ZMM. 1746 */ 1747 if (xcrval & XFEATURE_AVX512 && 1748 (xcrval & (XFEATURE_AVX512 | XFEATURE_AVX)) != 1749 (XFEATURE_AVX512 | XFEATURE_AVX)) { 1750 vm_inject_gp(vcpu->vcpu); 1751 return (HANDLED); 1752 } 1753 1754 /* 1755 * Intel MPX requires both bound register state flags to be 1756 * set. 1757 */ 1758 if (((xcrval & XFEATURE_ENABLED_BNDREGS) != 0) != 1759 ((xcrval & XFEATURE_ENABLED_BNDCSR) != 0)) { 1760 vm_inject_gp(vcpu->vcpu); 1761 return (HANDLED); 1762 } 1763 1764 /* 1765 * This runs "inside" vmrun() with the guest's FPU state, so 1766 * modifying xcr0 directly modifies the guest's xcr0, not the 1767 * host's. 1768 */ 1769 load_xcr(0, xcrval); 1770 return (HANDLED); 1771 } 1772 1773 static uint64_t 1774 vmx_get_guest_reg(struct vmx_vcpu *vcpu, int ident) 1775 { 1776 const struct vmxctx *vmxctx; 1777 1778 vmxctx = &vcpu->ctx; 1779 1780 switch (ident) { 1781 case 0: 1782 return (vmxctx->guest_rax); 1783 case 1: 1784 return (vmxctx->guest_rcx); 1785 case 2: 1786 return (vmxctx->guest_rdx); 1787 case 3: 1788 return (vmxctx->guest_rbx); 1789 case 4: 1790 return (vmcs_read(VMCS_GUEST_RSP)); 1791 case 5: 1792 return (vmxctx->guest_rbp); 1793 case 6: 1794 return (vmxctx->guest_rsi); 1795 case 7: 1796 return (vmxctx->guest_rdi); 1797 case 8: 1798 return (vmxctx->guest_r8); 1799 case 9: 1800 return (vmxctx->guest_r9); 1801 case 10: 1802 return (vmxctx->guest_r10); 1803 case 11: 1804 return (vmxctx->guest_r11); 1805 case 12: 1806 return (vmxctx->guest_r12); 1807 case 13: 1808 return (vmxctx->guest_r13); 1809 case 14: 1810 return (vmxctx->guest_r14); 1811 case 15: 1812 return (vmxctx->guest_r15); 1813 default: 1814 panic("invalid vmx register %d", ident); 1815 } 1816 } 1817 1818 static void 1819 vmx_set_guest_reg(struct vmx_vcpu *vcpu, int ident, uint64_t regval) 1820 { 1821 struct vmxctx *vmxctx; 1822 1823 vmxctx = &vcpu->ctx; 1824 1825 switch (ident) { 1826 case 0: 1827 vmxctx->guest_rax = regval; 1828 break; 1829 case 1: 1830 vmxctx->guest_rcx = regval; 1831 break; 1832 case 2: 1833 vmxctx->guest_rdx = regval; 1834 break; 1835 case 3: 1836 vmxctx->guest_rbx = regval; 1837 break; 1838 case 4: 1839 vmcs_write(VMCS_GUEST_RSP, regval); 1840 break; 1841 case 5: 1842 vmxctx->guest_rbp = regval; 1843 break; 1844 case 6: 1845 vmxctx->guest_rsi = regval; 1846 break; 1847 case 7: 1848 vmxctx->guest_rdi = regval; 1849 break; 1850 case 8: 1851 vmxctx->guest_r8 = regval; 1852 break; 1853 case 9: 1854 vmxctx->guest_r9 = regval; 1855 break; 1856 case 10: 1857 vmxctx->guest_r10 = regval; 1858 break; 1859 case 11: 1860 vmxctx->guest_r11 = regval; 1861 break; 1862 case 12: 1863 vmxctx->guest_r12 = regval; 1864 break; 1865 case 13: 1866 vmxctx->guest_r13 = regval; 1867 break; 1868 case 14: 1869 vmxctx->guest_r14 = regval; 1870 break; 1871 case 15: 1872 vmxctx->guest_r15 = regval; 1873 break; 1874 default: 1875 panic("invalid vmx register %d", ident); 1876 } 1877 } 1878 1879 static int 1880 vmx_emulate_cr0_access(struct vmx_vcpu *vcpu, uint64_t exitqual) 1881 { 1882 uint64_t crval, efer, entry_ctls, regval; 1883 1884 /* We only handle mov to %cr0 at this time */ 1885 if ((exitqual & 0xf0) != 0x00) 1886 return (UNHANDLED); 1887 1888 regval = vmx_get_guest_reg(vcpu, (exitqual >> 8) & 0xf); 1889 1890 vmcs_write(VMCS_CR0_SHADOW, regval); 1891 1892 crval = regval | cr0_ones_mask; 1893 crval &= ~cr0_zeros_mask; 1894 vmcs_write(VMCS_GUEST_CR0, crval); 1895 1896 /* 1897 * Keep EFER.LMA and the IA-32e guest VM-entry control in sync 1898 * with CR0.PG, using the value written to the VMCS (crval). 1899 */ 1900 efer = vmcs_read(VMCS_GUEST_IA32_EFER); 1901 entry_ctls = vmcs_read(VMCS_ENTRY_CTLS); 1902 if ((crval & CR0_PG) != 0 && (efer & EFER_LME) != 0) { 1903 efer |= EFER_LMA; 1904 entry_ctls |= VM_ENTRY_GUEST_LMA; 1905 } else { 1906 efer &= ~EFER_LMA; 1907 entry_ctls &= ~VM_ENTRY_GUEST_LMA; 1908 } 1909 vmcs_write(VMCS_GUEST_IA32_EFER, efer); 1910 vmcs_write(VMCS_ENTRY_CTLS, entry_ctls); 1911 1912 return (HANDLED); 1913 } 1914 1915 static int 1916 vmx_emulate_cr4_access(struct vmx_vcpu *vcpu, uint64_t exitqual) 1917 { 1918 uint64_t crval, regval; 1919 1920 /* We only handle mov to %cr4 at this time */ 1921 if ((exitqual & 0xf0) != 0x00) 1922 return (UNHANDLED); 1923 1924 regval = vmx_get_guest_reg(vcpu, (exitqual >> 8) & 0xf); 1925 1926 vmcs_write(VMCS_CR4_SHADOW, regval); 1927 1928 crval = regval | cr4_ones_mask; 1929 crval &= ~cr4_zeros_mask; 1930 vmcs_write(VMCS_GUEST_CR4, crval); 1931 1932 return (HANDLED); 1933 } 1934 1935 static int 1936 vmx_emulate_cr8_access(struct vmx *vmx, struct vmx_vcpu *vcpu, 1937 uint64_t exitqual) 1938 { 1939 struct vlapic *vlapic; 1940 uint64_t cr8; 1941 int regnum; 1942 1943 /* We only handle mov %cr8 to/from a register at this time. */ 1944 if ((exitqual & 0xe0) != 0x00) { 1945 return (UNHANDLED); 1946 } 1947 1948 vlapic = vm_lapic(vcpu->vcpu); 1949 regnum = (exitqual >> 8) & 0xf; 1950 if (exitqual & 0x10) { 1951 cr8 = vlapic_get_cr8(vlapic); 1952 vmx_set_guest_reg(vcpu, regnum, cr8); 1953 } else { 1954 cr8 = vmx_get_guest_reg(vcpu, regnum); 1955 vlapic_set_cr8(vlapic, cr8); 1956 } 1957 1958 return (HANDLED); 1959 } 1960 1961 /* 1962 * From section "Guest Register State" in the Intel SDM: CPL = SS.DPL 1963 */ 1964 static int 1965 vmx_cpl(void) 1966 { 1967 uint32_t ssar; 1968 1969 ssar = vmcs_read(VMCS_GUEST_SS_ACCESS_RIGHTS); 1970 return ((ssar >> 5) & 0x3); 1971 } 1972 1973 static enum vm_cpu_mode 1974 vmx_cpu_mode(void) 1975 { 1976 uint32_t csar; 1977 1978 if (vmcs_read(VMCS_GUEST_IA32_EFER) & EFER_LMA) { 1979 csar = vmcs_read(VMCS_GUEST_CS_ACCESS_RIGHTS); 1980 if (csar & 0x2000) 1981 return (CPU_MODE_64BIT); /* CS.L = 1 */ 1982 else 1983 return (CPU_MODE_COMPATIBILITY); 1984 } else if (vmcs_read(VMCS_GUEST_CR0) & CR0_PE) { 1985 return (CPU_MODE_PROTECTED); 1986 } else { 1987 return (CPU_MODE_REAL); 1988 } 1989 } 1990 1991 static enum vm_paging_mode 1992 vmx_paging_mode(void) 1993 { 1994 uint64_t cr4; 1995 1996 if (!(vmcs_read(VMCS_GUEST_CR0) & CR0_PG)) 1997 return (PAGING_MODE_FLAT); 1998 cr4 = vmcs_read(VMCS_GUEST_CR4); 1999 if (!(cr4 & CR4_PAE)) 2000 return (PAGING_MODE_32); 2001 if (vmcs_read(VMCS_GUEST_IA32_EFER) & EFER_LME) { 2002 if (!(cr4 & CR4_LA57)) 2003 return (PAGING_MODE_64); 2004 return (PAGING_MODE_64_LA57); 2005 } else 2006 return (PAGING_MODE_PAE); 2007 } 2008 2009 static uint64_t 2010 inout_str_index(struct vmx_vcpu *vcpu, int in) 2011 { 2012 uint64_t val; 2013 int error __diagused; 2014 enum vm_reg_name reg; 2015 2016 reg = in ? VM_REG_GUEST_RDI : VM_REG_GUEST_RSI; 2017 error = vmx_getreg(vcpu, reg, &val); 2018 KASSERT(error == 0, ("%s: vmx_getreg error %d", __func__, error)); 2019 return (val); 2020 } 2021 2022 static uint64_t 2023 inout_str_count(struct vmx_vcpu *vcpu, int rep) 2024 { 2025 uint64_t val; 2026 int error __diagused; 2027 2028 if (rep) { 2029 error = vmx_getreg(vcpu, VM_REG_GUEST_RCX, &val); 2030 KASSERT(!error, ("%s: vmx_getreg error %d", __func__, error)); 2031 } else { 2032 val = 1; 2033 } 2034 return (val); 2035 } 2036 2037 static int 2038 inout_str_addrsize(uint32_t inst_info) 2039 { 2040 uint32_t size; 2041 2042 size = (inst_info >> 7) & 0x7; 2043 switch (size) { 2044 case 0: 2045 return (2); /* 16 bit */ 2046 case 1: 2047 return (4); /* 32 bit */ 2048 case 2: 2049 return (8); /* 64 bit */ 2050 default: 2051 panic("%s: invalid size encoding %d", __func__, size); 2052 } 2053 } 2054 2055 static void 2056 inout_str_seginfo(struct vmx_vcpu *vcpu, uint32_t inst_info, int in, 2057 struct vm_inout_str *vis) 2058 { 2059 int error __diagused, s; 2060 2061 if (in) { 2062 vis->seg_name = VM_REG_GUEST_ES; 2063 } else { 2064 s = (inst_info >> 15) & 0x7; 2065 vis->seg_name = vm_segment_name(s); 2066 } 2067 2068 error = vmx_getdesc(vcpu, vis->seg_name, &vis->seg_desc); 2069 KASSERT(error == 0, ("%s: vmx_getdesc error %d", __func__, error)); 2070 } 2071 2072 static void 2073 vmx_paging_info(struct vm_guest_paging *paging) 2074 { 2075 paging->cr3 = vmcs_guest_cr3(); 2076 paging->cpl = vmx_cpl(); 2077 paging->cpu_mode = vmx_cpu_mode(); 2078 paging->paging_mode = vmx_paging_mode(); 2079 } 2080 2081 static void 2082 vmexit_inst_emul(struct vm_exit *vmexit, uint64_t gpa, uint64_t gla) 2083 { 2084 struct vm_guest_paging *paging; 2085 uint32_t csar; 2086 2087 paging = &vmexit->u.inst_emul.paging; 2088 2089 vmexit->exitcode = VM_EXITCODE_INST_EMUL; 2090 vmexit->inst_length = 0; 2091 vmexit->u.inst_emul.gpa = gpa; 2092 vmexit->u.inst_emul.gla = gla; 2093 vmx_paging_info(paging); 2094 switch (paging->cpu_mode) { 2095 case CPU_MODE_REAL: 2096 vmexit->u.inst_emul.cs_base = vmcs_read(VMCS_GUEST_CS_BASE); 2097 vmexit->u.inst_emul.cs_d = 0; 2098 break; 2099 case CPU_MODE_PROTECTED: 2100 case CPU_MODE_COMPATIBILITY: 2101 vmexit->u.inst_emul.cs_base = vmcs_read(VMCS_GUEST_CS_BASE); 2102 csar = vmcs_read(VMCS_GUEST_CS_ACCESS_RIGHTS); 2103 vmexit->u.inst_emul.cs_d = SEG_DESC_DEF32(csar); 2104 break; 2105 default: 2106 vmexit->u.inst_emul.cs_base = 0; 2107 vmexit->u.inst_emul.cs_d = 0; 2108 break; 2109 } 2110 vie_init(&vmexit->u.inst_emul.vie, NULL, 0); 2111 } 2112 2113 static int 2114 ept_fault_type(uint64_t ept_qual) 2115 { 2116 int fault_type; 2117 2118 if (ept_qual & EPT_VIOLATION_DATA_WRITE) 2119 fault_type = VM_PROT_WRITE; 2120 else if (ept_qual & EPT_VIOLATION_INST_FETCH) 2121 fault_type = VM_PROT_EXECUTE; 2122 else 2123 fault_type= VM_PROT_READ; 2124 2125 return (fault_type); 2126 } 2127 2128 static bool 2129 ept_emulation_fault(uint64_t ept_qual) 2130 { 2131 int read, write; 2132 2133 /* EPT fault on an instruction fetch doesn't make sense here */ 2134 if (ept_qual & EPT_VIOLATION_INST_FETCH) 2135 return (false); 2136 2137 /* EPT fault must be a read fault or a write fault */ 2138 read = ept_qual & EPT_VIOLATION_DATA_READ ? 1 : 0; 2139 write = ept_qual & EPT_VIOLATION_DATA_WRITE ? 1 : 0; 2140 if ((read | write) == 0) 2141 return (false); 2142 2143 /* 2144 * The EPT violation must have been caused by accessing a 2145 * guest-physical address that is a translation of a guest-linear 2146 * address. 2147 */ 2148 if ((ept_qual & EPT_VIOLATION_GLA_VALID) == 0 || 2149 (ept_qual & EPT_VIOLATION_XLAT_VALID) == 0) { 2150 return (false); 2151 } 2152 2153 return (true); 2154 } 2155 2156 static __inline int 2157 apic_access_virtualization(struct vmx_vcpu *vcpu) 2158 { 2159 uint32_t proc_ctls2; 2160 2161 proc_ctls2 = vcpu->cap.proc_ctls2; 2162 return ((proc_ctls2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES) ? 1 : 0); 2163 } 2164 2165 static __inline int 2166 x2apic_virtualization(struct vmx_vcpu *vcpu) 2167 { 2168 uint32_t proc_ctls2; 2169 2170 proc_ctls2 = vcpu->cap.proc_ctls2; 2171 return ((proc_ctls2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE) ? 1 : 0); 2172 } 2173 2174 static int 2175 vmx_handle_apic_write(struct vmx_vcpu *vcpu, struct vlapic *vlapic, 2176 uint64_t qual) 2177 { 2178 int error, handled, offset; 2179 uint32_t *apic_regs, vector; 2180 bool retu; 2181 2182 handled = HANDLED; 2183 offset = APIC_WRITE_OFFSET(qual); 2184 2185 if (!apic_access_virtualization(vcpu)) { 2186 /* 2187 * In general there should not be any APIC write VM-exits 2188 * unless APIC-access virtualization is enabled. 2189 * 2190 * However self-IPI virtualization can legitimately trigger 2191 * an APIC-write VM-exit so treat it specially. 2192 */ 2193 if (x2apic_virtualization(vcpu) && 2194 offset == APIC_OFFSET_SELF_IPI) { 2195 apic_regs = (uint32_t *)(vlapic->apic_page); 2196 vector = apic_regs[APIC_OFFSET_SELF_IPI / 4]; 2197 vlapic_self_ipi_handler(vlapic, vector); 2198 return (HANDLED); 2199 } else 2200 return (UNHANDLED); 2201 } 2202 2203 switch (offset) { 2204 case APIC_OFFSET_ID: 2205 vlapic_id_write_handler(vlapic); 2206 break; 2207 case APIC_OFFSET_LDR: 2208 vlapic_ldr_write_handler(vlapic); 2209 break; 2210 case APIC_OFFSET_DFR: 2211 vlapic_dfr_write_handler(vlapic); 2212 break; 2213 case APIC_OFFSET_SVR: 2214 vlapic_svr_write_handler(vlapic); 2215 break; 2216 case APIC_OFFSET_ESR: 2217 vlapic_esr_write_handler(vlapic); 2218 break; 2219 case APIC_OFFSET_ICR_LOW: 2220 retu = false; 2221 error = vlapic_icrlo_write_handler(vlapic, &retu); 2222 if (error != 0 || retu) 2223 handled = UNHANDLED; 2224 break; 2225 case APIC_OFFSET_CMCI_LVT: 2226 case APIC_OFFSET_TIMER_LVT ... APIC_OFFSET_ERROR_LVT: 2227 vlapic_lvt_write_handler(vlapic, offset); 2228 break; 2229 case APIC_OFFSET_TIMER_ICR: 2230 vlapic_icrtmr_write_handler(vlapic); 2231 break; 2232 case APIC_OFFSET_TIMER_DCR: 2233 vlapic_dcr_write_handler(vlapic); 2234 break; 2235 default: 2236 handled = UNHANDLED; 2237 break; 2238 } 2239 return (handled); 2240 } 2241 2242 static bool 2243 apic_access_fault(struct vmx_vcpu *vcpu, uint64_t gpa) 2244 { 2245 2246 if (apic_access_virtualization(vcpu) && 2247 (gpa >= DEFAULT_APIC_BASE && gpa < DEFAULT_APIC_BASE + PAGE_SIZE)) 2248 return (true); 2249 else 2250 return (false); 2251 } 2252 2253 static int 2254 vmx_handle_apic_access(struct vmx_vcpu *vcpu, struct vm_exit *vmexit) 2255 { 2256 uint64_t qual; 2257 int access_type, offset, allowed; 2258 2259 if (!apic_access_virtualization(vcpu)) 2260 return (UNHANDLED); 2261 2262 qual = vmexit->u.vmx.exit_qualification; 2263 access_type = APIC_ACCESS_TYPE(qual); 2264 offset = APIC_ACCESS_OFFSET(qual); 2265 2266 allowed = 0; 2267 if (access_type == 0) { 2268 /* 2269 * Read data access to the following registers is expected. 2270 */ 2271 switch (offset) { 2272 case APIC_OFFSET_APR: 2273 case APIC_OFFSET_PPR: 2274 case APIC_OFFSET_RRR: 2275 case APIC_OFFSET_CMCI_LVT: 2276 case APIC_OFFSET_TIMER_CCR: 2277 allowed = 1; 2278 break; 2279 default: 2280 break; 2281 } 2282 } else if (access_type == 1) { 2283 /* 2284 * Write data access to the following registers is expected. 2285 */ 2286 switch (offset) { 2287 case APIC_OFFSET_VER: 2288 case APIC_OFFSET_APR: 2289 case APIC_OFFSET_PPR: 2290 case APIC_OFFSET_RRR: 2291 case APIC_OFFSET_ISR0 ... APIC_OFFSET_ISR7: 2292 case APIC_OFFSET_TMR0 ... APIC_OFFSET_TMR7: 2293 case APIC_OFFSET_IRR0 ... APIC_OFFSET_IRR7: 2294 case APIC_OFFSET_CMCI_LVT: 2295 case APIC_OFFSET_TIMER_CCR: 2296 allowed = 1; 2297 break; 2298 default: 2299 break; 2300 } 2301 } 2302 2303 if (allowed) { 2304 vmexit_inst_emul(vmexit, DEFAULT_APIC_BASE + offset, 2305 VIE_INVALID_GLA); 2306 } 2307 2308 /* 2309 * Regardless of whether the APIC-access is allowed this handler 2310 * always returns UNHANDLED: 2311 * - if the access is allowed then it is handled by emulating the 2312 * instruction that caused the VM-exit (outside the critical section) 2313 * - if the access is not allowed then it will be converted to an 2314 * exitcode of VM_EXITCODE_VMX and will be dealt with in userland. 2315 */ 2316 return (UNHANDLED); 2317 } 2318 2319 static enum task_switch_reason 2320 vmx_task_switch_reason(uint64_t qual) 2321 { 2322 int reason; 2323 2324 reason = (qual >> 30) & 0x3; 2325 switch (reason) { 2326 case 0: 2327 return (TSR_CALL); 2328 case 1: 2329 return (TSR_IRET); 2330 case 2: 2331 return (TSR_JMP); 2332 case 3: 2333 return (TSR_IDT_GATE); 2334 default: 2335 panic("%s: invalid reason %d", __func__, reason); 2336 } 2337 } 2338 2339 static int 2340 emulate_wrmsr(struct vmx_vcpu *vcpu, u_int num, uint64_t val, bool *retu) 2341 { 2342 int error; 2343 2344 if (lapic_msr(num)) 2345 error = lapic_wrmsr(vcpu->vcpu, num, val, retu); 2346 else 2347 error = vmx_wrmsr(vcpu, num, val, retu); 2348 2349 return (error); 2350 } 2351 2352 static int 2353 emulate_rdmsr(struct vmx_vcpu *vcpu, u_int num, bool *retu) 2354 { 2355 struct vmxctx *vmxctx; 2356 uint64_t result; 2357 uint32_t eax, edx; 2358 int error; 2359 2360 if (lapic_msr(num)) 2361 error = lapic_rdmsr(vcpu->vcpu, num, &result, retu); 2362 else 2363 error = vmx_rdmsr(vcpu, num, &result, retu); 2364 2365 if (error == 0) { 2366 eax = result; 2367 vmxctx = &vcpu->ctx; 2368 error = vmxctx_setreg(vmxctx, VM_REG_GUEST_RAX, eax); 2369 KASSERT(error == 0, ("vmxctx_setreg(rax) error %d", error)); 2370 2371 edx = result >> 32; 2372 error = vmxctx_setreg(vmxctx, VM_REG_GUEST_RDX, edx); 2373 KASSERT(error == 0, ("vmxctx_setreg(rdx) error %d", error)); 2374 } 2375 2376 return (error); 2377 } 2378 2379 static int 2380 vmx_exit_process(struct vmx *vmx, struct vmx_vcpu *vcpu, struct vm_exit *vmexit) 2381 { 2382 int error, errcode, errcode_valid, handled, in; 2383 struct vmxctx *vmxctx; 2384 struct vlapic *vlapic; 2385 struct vm_inout_str *vis; 2386 struct vm_task_switch *ts; 2387 uint32_t eax, ecx, edx, idtvec_info, idtvec_err, intr_info, inst_info; 2388 uint32_t intr_type, intr_vec, reason; 2389 uint64_t exitintinfo, qual, gpa; 2390 #ifdef KDTRACE_HOOKS 2391 int vcpuid; 2392 #endif 2393 bool retu; 2394 2395 CTASSERT((PINBASED_CTLS_ONE_SETTING & PINBASED_VIRTUAL_NMI) != 0); 2396 CTASSERT((PINBASED_CTLS_ONE_SETTING & PINBASED_NMI_EXITING) != 0); 2397 2398 handled = UNHANDLED; 2399 vmxctx = &vcpu->ctx; 2400 #ifdef KDTRACE_HOOKS 2401 vcpuid = vcpu->vcpuid; 2402 #endif 2403 2404 qual = vmexit->u.vmx.exit_qualification; 2405 reason = vmexit->u.vmx.exit_reason; 2406 vmexit->exitcode = VM_EXITCODE_BOGUS; 2407 2408 vmm_stat_incr(vcpu->vcpu, VMEXIT_COUNT, 1); 2409 SDT_PROBE3(vmm, vmx, exit, entry, vmx, vcpuid, vmexit); 2410 2411 /* 2412 * VM-entry failures during or after loading guest state. 2413 * 2414 * These VM-exits are uncommon but must be handled specially 2415 * as most VM-exit fields are not populated as usual. 2416 */ 2417 if (__predict_false(reason == EXIT_REASON_MCE_DURING_ENTRY)) { 2418 VMX_CTR0(vcpu, "Handling MCE during VM-entry"); 2419 __asm __volatile("int $18"); 2420 return (1); 2421 } 2422 2423 /* 2424 * VM exits that can be triggered during event delivery need to 2425 * be handled specially by re-injecting the event if the IDT 2426 * vectoring information field's valid bit is set. 2427 * 2428 * See "Information for VM Exits During Event Delivery" in Intel SDM 2429 * for details. 2430 */ 2431 idtvec_info = vmcs_idt_vectoring_info(); 2432 if (idtvec_info & VMCS_IDT_VEC_VALID) { 2433 idtvec_info &= ~(1 << 12); /* clear undefined bit */ 2434 exitintinfo = idtvec_info; 2435 if (idtvec_info & VMCS_IDT_VEC_ERRCODE_VALID) { 2436 idtvec_err = vmcs_idt_vectoring_err(); 2437 exitintinfo |= (uint64_t)idtvec_err << 32; 2438 } 2439 error = vm_exit_intinfo(vcpu->vcpu, exitintinfo); 2440 KASSERT(error == 0, ("%s: vm_set_intinfo error %d", 2441 __func__, error)); 2442 2443 /* 2444 * If 'virtual NMIs' are being used and the VM-exit 2445 * happened while injecting an NMI during the previous 2446 * VM-entry, then clear "blocking by NMI" in the 2447 * Guest Interruptibility-State so the NMI can be 2448 * reinjected on the subsequent VM-entry. 2449 * 2450 * However, if the NMI was being delivered through a task 2451 * gate, then the new task must start execution with NMIs 2452 * blocked so don't clear NMI blocking in this case. 2453 */ 2454 intr_type = idtvec_info & VMCS_INTR_T_MASK; 2455 if (intr_type == VMCS_INTR_T_NMI) { 2456 if (reason != EXIT_REASON_TASK_SWITCH) 2457 vmx_clear_nmi_blocking(vcpu); 2458 else 2459 vmx_assert_nmi_blocking(vcpu); 2460 } 2461 2462 /* 2463 * Update VM-entry instruction length if the event being 2464 * delivered was a software interrupt or software exception. 2465 */ 2466 if (intr_type == VMCS_INTR_T_SWINTR || 2467 intr_type == VMCS_INTR_T_PRIV_SWEXCEPTION || 2468 intr_type == VMCS_INTR_T_SWEXCEPTION) { 2469 vmcs_write(VMCS_ENTRY_INST_LENGTH, vmexit->inst_length); 2470 } 2471 } 2472 2473 switch (reason) { 2474 case EXIT_REASON_TRIPLE_FAULT: 2475 (void)vm_suspend(vmx->vm, VM_SUSPEND_TRIPLEFAULT); 2476 handled = HANDLED; 2477 break; 2478 case EXIT_REASON_TASK_SWITCH: 2479 ts = &vmexit->u.task_switch; 2480 ts->tsssel = qual & 0xffff; 2481 ts->reason = vmx_task_switch_reason(qual); 2482 ts->ext = 0; 2483 ts->errcode_valid = 0; 2484 vmx_paging_info(&ts->paging); 2485 /* 2486 * If the task switch was due to a CALL, JMP, IRET, software 2487 * interrupt (INT n) or software exception (INT3, INTO), 2488 * then the saved %rip references the instruction that caused 2489 * the task switch. The instruction length field in the VMCS 2490 * is valid in this case. 2491 * 2492 * In all other cases (e.g., NMI, hardware exception) the 2493 * saved %rip is one that would have been saved in the old TSS 2494 * had the task switch completed normally so the instruction 2495 * length field is not needed in this case and is explicitly 2496 * set to 0. 2497 */ 2498 if (ts->reason == TSR_IDT_GATE) { 2499 KASSERT(idtvec_info & VMCS_IDT_VEC_VALID, 2500 ("invalid idtvec_info %#x for IDT task switch", 2501 idtvec_info)); 2502 intr_type = idtvec_info & VMCS_INTR_T_MASK; 2503 if (intr_type != VMCS_INTR_T_SWINTR && 2504 intr_type != VMCS_INTR_T_SWEXCEPTION && 2505 intr_type != VMCS_INTR_T_PRIV_SWEXCEPTION) { 2506 /* Task switch triggered by external event */ 2507 ts->ext = 1; 2508 vmexit->inst_length = 0; 2509 if (idtvec_info & VMCS_IDT_VEC_ERRCODE_VALID) { 2510 ts->errcode_valid = 1; 2511 ts->errcode = vmcs_idt_vectoring_err(); 2512 } 2513 } 2514 } 2515 vmexit->exitcode = VM_EXITCODE_TASK_SWITCH; 2516 SDT_PROBE4(vmm, vmx, exit, taskswitch, vmx, vcpuid, vmexit, ts); 2517 VMX_CTR4(vcpu, "task switch reason %d, tss 0x%04x, " 2518 "%s errcode 0x%016lx", ts->reason, ts->tsssel, 2519 ts->ext ? "external" : "internal", 2520 ((uint64_t)ts->errcode << 32) | ts->errcode_valid); 2521 break; 2522 case EXIT_REASON_CR_ACCESS: 2523 vmm_stat_incr(vcpu->vcpu, VMEXIT_CR_ACCESS, 1); 2524 SDT_PROBE4(vmm, vmx, exit, craccess, vmx, vcpuid, vmexit, qual); 2525 switch (qual & 0xf) { 2526 case 0: 2527 handled = vmx_emulate_cr0_access(vcpu, qual); 2528 break; 2529 case 4: 2530 handled = vmx_emulate_cr4_access(vcpu, qual); 2531 break; 2532 case 8: 2533 handled = vmx_emulate_cr8_access(vmx, vcpu, qual); 2534 break; 2535 } 2536 break; 2537 case EXIT_REASON_RDMSR: 2538 vmm_stat_incr(vcpu->vcpu, VMEXIT_RDMSR, 1); 2539 retu = false; 2540 ecx = vmxctx->guest_rcx; 2541 VMX_CTR1(vcpu, "rdmsr 0x%08x", ecx); 2542 SDT_PROBE4(vmm, vmx, exit, rdmsr, vmx, vcpuid, vmexit, ecx); 2543 error = emulate_rdmsr(vcpu, ecx, &retu); 2544 if (error) { 2545 vmexit->exitcode = VM_EXITCODE_RDMSR; 2546 vmexit->u.msr.code = ecx; 2547 } else if (!retu) { 2548 handled = HANDLED; 2549 } else { 2550 /* Return to userspace with a valid exitcode */ 2551 KASSERT(vmexit->exitcode != VM_EXITCODE_BOGUS, 2552 ("emulate_rdmsr retu with bogus exitcode")); 2553 } 2554 break; 2555 case EXIT_REASON_WRMSR: 2556 vmm_stat_incr(vcpu->vcpu, VMEXIT_WRMSR, 1); 2557 retu = false; 2558 eax = vmxctx->guest_rax; 2559 ecx = vmxctx->guest_rcx; 2560 edx = vmxctx->guest_rdx; 2561 VMX_CTR2(vcpu, "wrmsr 0x%08x value 0x%016lx", 2562 ecx, (uint64_t)edx << 32 | eax); 2563 SDT_PROBE5(vmm, vmx, exit, wrmsr, vmx, vmexit, vcpuid, ecx, 2564 (uint64_t)edx << 32 | eax); 2565 error = emulate_wrmsr(vcpu, ecx, (uint64_t)edx << 32 | eax, 2566 &retu); 2567 if (error) { 2568 vmexit->exitcode = VM_EXITCODE_WRMSR; 2569 vmexit->u.msr.code = ecx; 2570 vmexit->u.msr.wval = (uint64_t)edx << 32 | eax; 2571 } else if (!retu) { 2572 handled = HANDLED; 2573 } else { 2574 /* Return to userspace with a valid exitcode */ 2575 KASSERT(vmexit->exitcode != VM_EXITCODE_BOGUS, 2576 ("emulate_wrmsr retu with bogus exitcode")); 2577 } 2578 break; 2579 case EXIT_REASON_HLT: 2580 vmm_stat_incr(vcpu->vcpu, VMEXIT_HLT, 1); 2581 SDT_PROBE3(vmm, vmx, exit, halt, vmx, vcpuid, vmexit); 2582 vmexit->exitcode = VM_EXITCODE_HLT; 2583 vmexit->u.hlt.rflags = vmcs_read(VMCS_GUEST_RFLAGS); 2584 if (virtual_interrupt_delivery) 2585 vmexit->u.hlt.intr_status = 2586 vmcs_read(VMCS_GUEST_INTR_STATUS); 2587 else 2588 vmexit->u.hlt.intr_status = 0; 2589 break; 2590 case EXIT_REASON_MTF: 2591 vmm_stat_incr(vcpu->vcpu, VMEXIT_MTRAP, 1); 2592 SDT_PROBE3(vmm, vmx, exit, mtrap, vmx, vcpuid, vmexit); 2593 vmexit->exitcode = VM_EXITCODE_MTRAP; 2594 vmexit->inst_length = 0; 2595 break; 2596 case EXIT_REASON_PAUSE: 2597 vmm_stat_incr(vcpu->vcpu, VMEXIT_PAUSE, 1); 2598 SDT_PROBE3(vmm, vmx, exit, pause, vmx, vcpuid, vmexit); 2599 vmexit->exitcode = VM_EXITCODE_PAUSE; 2600 break; 2601 case EXIT_REASON_INTR_WINDOW: 2602 vmm_stat_incr(vcpu->vcpu, VMEXIT_INTR_WINDOW, 1); 2603 SDT_PROBE3(vmm, vmx, exit, intrwindow, vmx, vcpuid, vmexit); 2604 vmx_clear_int_window_exiting(vcpu); 2605 return (1); 2606 case EXIT_REASON_EXT_INTR: 2607 /* 2608 * External interrupts serve only to cause VM exits and allow 2609 * the host interrupt handler to run. 2610 * 2611 * If this external interrupt triggers a virtual interrupt 2612 * to a VM, then that state will be recorded by the 2613 * host interrupt handler in the VM's softc. We will inject 2614 * this virtual interrupt during the subsequent VM enter. 2615 */ 2616 intr_info = vmcs_read(VMCS_EXIT_INTR_INFO); 2617 SDT_PROBE4(vmm, vmx, exit, interrupt, 2618 vmx, vcpuid, vmexit, intr_info); 2619 2620 /* 2621 * XXX: Ignore this exit if VMCS_INTR_VALID is not set. 2622 * This appears to be a bug in VMware Fusion? 2623 */ 2624 if (!(intr_info & VMCS_INTR_VALID)) 2625 return (1); 2626 KASSERT((intr_info & VMCS_INTR_VALID) != 0 && 2627 (intr_info & VMCS_INTR_T_MASK) == VMCS_INTR_T_HWINTR, 2628 ("VM exit interruption info invalid: %#x", intr_info)); 2629 vmx_trigger_hostintr(intr_info & 0xff); 2630 2631 /* 2632 * This is special. We want to treat this as an 'handled' 2633 * VM-exit but not increment the instruction pointer. 2634 */ 2635 vmm_stat_incr(vcpu->vcpu, VMEXIT_EXTINT, 1); 2636 return (1); 2637 case EXIT_REASON_NMI_WINDOW: 2638 SDT_PROBE3(vmm, vmx, exit, nmiwindow, vmx, vcpuid, vmexit); 2639 /* Exit to allow the pending virtual NMI to be injected */ 2640 if (vm_nmi_pending(vcpu->vcpu)) 2641 vmx_inject_nmi(vcpu); 2642 vmx_clear_nmi_window_exiting(vcpu); 2643 vmm_stat_incr(vcpu->vcpu, VMEXIT_NMI_WINDOW, 1); 2644 return (1); 2645 case EXIT_REASON_INOUT: 2646 vmm_stat_incr(vcpu->vcpu, VMEXIT_INOUT, 1); 2647 vmexit->exitcode = VM_EXITCODE_INOUT; 2648 vmexit->u.inout.bytes = (qual & 0x7) + 1; 2649 vmexit->u.inout.in = in = (qual & 0x8) ? 1 : 0; 2650 vmexit->u.inout.string = (qual & 0x10) ? 1 : 0; 2651 vmexit->u.inout.rep = (qual & 0x20) ? 1 : 0; 2652 vmexit->u.inout.port = (uint16_t)(qual >> 16); 2653 vmexit->u.inout.eax = (uint32_t)(vmxctx->guest_rax); 2654 if (vmexit->u.inout.string) { 2655 inst_info = vmcs_read(VMCS_EXIT_INSTRUCTION_INFO); 2656 vmexit->exitcode = VM_EXITCODE_INOUT_STR; 2657 vis = &vmexit->u.inout_str; 2658 vmx_paging_info(&vis->paging); 2659 vis->rflags = vmcs_read(VMCS_GUEST_RFLAGS); 2660 vis->cr0 = vmcs_read(VMCS_GUEST_CR0); 2661 vis->index = inout_str_index(vcpu, in); 2662 vis->count = inout_str_count(vcpu, vis->inout.rep); 2663 vis->addrsize = inout_str_addrsize(inst_info); 2664 vis->cs_d = 0; 2665 vis->cs_base = 0; 2666 inout_str_seginfo(vcpu, inst_info, in, vis); 2667 } 2668 SDT_PROBE3(vmm, vmx, exit, inout, vmx, vcpuid, vmexit); 2669 break; 2670 case EXIT_REASON_CPUID: 2671 vmm_stat_incr(vcpu->vcpu, VMEXIT_CPUID, 1); 2672 SDT_PROBE3(vmm, vmx, exit, cpuid, vmx, vcpuid, vmexit); 2673 handled = vmx_handle_cpuid(vcpu, vmxctx); 2674 break; 2675 case EXIT_REASON_EXCEPTION: 2676 vmm_stat_incr(vcpu->vcpu, VMEXIT_EXCEPTION, 1); 2677 intr_info = vmcs_read(VMCS_EXIT_INTR_INFO); 2678 KASSERT((intr_info & VMCS_INTR_VALID) != 0, 2679 ("VM exit interruption info invalid: %#x", intr_info)); 2680 2681 intr_vec = intr_info & 0xff; 2682 intr_type = intr_info & VMCS_INTR_T_MASK; 2683 2684 /* 2685 * If Virtual NMIs control is 1 and the VM-exit is due to a 2686 * fault encountered during the execution of IRET then we must 2687 * restore the state of "virtual-NMI blocking" before resuming 2688 * the guest. 2689 * 2690 * See "Resuming Guest Software after Handling an Exception". 2691 * See "Information for VM Exits Due to Vectored Events". 2692 */ 2693 if ((idtvec_info & VMCS_IDT_VEC_VALID) == 0 && 2694 (intr_vec != IDT_DF) && 2695 (intr_info & EXIT_QUAL_NMIUDTI) != 0) 2696 vmx_restore_nmi_blocking(vcpu); 2697 2698 /* 2699 * The NMI has already been handled in vmx_exit_handle_nmi(). 2700 */ 2701 if (intr_type == VMCS_INTR_T_NMI) 2702 return (1); 2703 2704 /* 2705 * Call the machine check handler by hand. Also don't reflect 2706 * the machine check back into the guest. 2707 */ 2708 if (intr_vec == IDT_MC) { 2709 VMX_CTR0(vcpu, "Vectoring to MCE handler"); 2710 __asm __volatile("int $18"); 2711 return (1); 2712 } 2713 2714 /* 2715 * If the hypervisor has requested user exits for 2716 * debug exceptions, bounce them out to userland. 2717 */ 2718 if (intr_type == VMCS_INTR_T_SWEXCEPTION && intr_vec == IDT_BP && 2719 (vcpu->cap.set & (1 << VM_CAP_BPT_EXIT))) { 2720 vmexit->exitcode = VM_EXITCODE_BPT; 2721 vmexit->u.bpt.inst_length = vmexit->inst_length; 2722 vmexit->inst_length = 0; 2723 break; 2724 } 2725 2726 if (intr_vec == IDT_PF) { 2727 error = vmxctx_setreg(vmxctx, VM_REG_GUEST_CR2, qual); 2728 KASSERT(error == 0, ("%s: vmxctx_setreg(cr2) error %d", 2729 __func__, error)); 2730 } 2731 2732 /* 2733 * Software exceptions exhibit trap-like behavior. This in 2734 * turn requires populating the VM-entry instruction length 2735 * so that the %rip in the trap frame is past the INT3/INTO 2736 * instruction. 2737 */ 2738 if (intr_type == VMCS_INTR_T_SWEXCEPTION) 2739 vmcs_write(VMCS_ENTRY_INST_LENGTH, vmexit->inst_length); 2740 2741 /* Reflect all other exceptions back into the guest */ 2742 errcode_valid = errcode = 0; 2743 if (intr_info & VMCS_INTR_DEL_ERRCODE) { 2744 errcode_valid = 1; 2745 errcode = vmcs_read(VMCS_EXIT_INTR_ERRCODE); 2746 } 2747 VMX_CTR2(vcpu, "Reflecting exception %d/%#x into " 2748 "the guest", intr_vec, errcode); 2749 SDT_PROBE5(vmm, vmx, exit, exception, 2750 vmx, vcpuid, vmexit, intr_vec, errcode); 2751 error = vm_inject_exception(vcpu->vcpu, intr_vec, 2752 errcode_valid, errcode, 0); 2753 KASSERT(error == 0, ("%s: vm_inject_exception error %d", 2754 __func__, error)); 2755 return (1); 2756 2757 case EXIT_REASON_EPT_FAULT: 2758 /* 2759 * If 'gpa' lies within the address space allocated to 2760 * memory then this must be a nested page fault otherwise 2761 * this must be an instruction that accesses MMIO space. 2762 */ 2763 gpa = vmcs_gpa(); 2764 if (vm_mem_allocated(vcpu->vcpu, gpa) || 2765 ppt_is_mmio(vmx->vm, gpa) || apic_access_fault(vcpu, gpa)) { 2766 vmexit->exitcode = VM_EXITCODE_PAGING; 2767 vmexit->inst_length = 0; 2768 vmexit->u.paging.gpa = gpa; 2769 vmexit->u.paging.fault_type = ept_fault_type(qual); 2770 vmm_stat_incr(vcpu->vcpu, VMEXIT_NESTED_FAULT, 1); 2771 SDT_PROBE5(vmm, vmx, exit, nestedfault, 2772 vmx, vcpuid, vmexit, gpa, qual); 2773 } else if (ept_emulation_fault(qual)) { 2774 vmexit_inst_emul(vmexit, gpa, vmcs_gla()); 2775 vmm_stat_incr(vcpu->vcpu, VMEXIT_INST_EMUL, 1); 2776 SDT_PROBE4(vmm, vmx, exit, mmiofault, 2777 vmx, vcpuid, vmexit, gpa); 2778 } 2779 /* 2780 * If Virtual NMIs control is 1 and the VM-exit is due to an 2781 * EPT fault during the execution of IRET then we must restore 2782 * the state of "virtual-NMI blocking" before resuming. 2783 * 2784 * See description of "NMI unblocking due to IRET" in 2785 * "Exit Qualification for EPT Violations". 2786 */ 2787 if ((idtvec_info & VMCS_IDT_VEC_VALID) == 0 && 2788 (qual & EXIT_QUAL_NMIUDTI) != 0) 2789 vmx_restore_nmi_blocking(vcpu); 2790 break; 2791 case EXIT_REASON_VIRTUALIZED_EOI: 2792 vmexit->exitcode = VM_EXITCODE_IOAPIC_EOI; 2793 vmexit->u.ioapic_eoi.vector = qual & 0xFF; 2794 SDT_PROBE3(vmm, vmx, exit, eoi, vmx, vcpuid, vmexit); 2795 vmexit->inst_length = 0; /* trap-like */ 2796 break; 2797 case EXIT_REASON_APIC_ACCESS: 2798 SDT_PROBE3(vmm, vmx, exit, apicaccess, vmx, vcpuid, vmexit); 2799 handled = vmx_handle_apic_access(vcpu, vmexit); 2800 break; 2801 case EXIT_REASON_APIC_WRITE: 2802 /* 2803 * APIC-write VM exit is trap-like so the %rip is already 2804 * pointing to the next instruction. 2805 */ 2806 vmexit->inst_length = 0; 2807 vlapic = vm_lapic(vcpu->vcpu); 2808 SDT_PROBE4(vmm, vmx, exit, apicwrite, 2809 vmx, vcpuid, vmexit, vlapic); 2810 handled = vmx_handle_apic_write(vcpu, vlapic, qual); 2811 break; 2812 case EXIT_REASON_XSETBV: 2813 SDT_PROBE3(vmm, vmx, exit, xsetbv, vmx, vcpuid, vmexit); 2814 handled = vmx_emulate_xsetbv(vmx, vcpu, vmexit); 2815 break; 2816 case EXIT_REASON_MONITOR: 2817 SDT_PROBE3(vmm, vmx, exit, monitor, vmx, vcpuid, vmexit); 2818 vmexit->exitcode = VM_EXITCODE_MONITOR; 2819 break; 2820 case EXIT_REASON_MWAIT: 2821 SDT_PROBE3(vmm, vmx, exit, mwait, vmx, vcpuid, vmexit); 2822 vmexit->exitcode = VM_EXITCODE_MWAIT; 2823 break; 2824 case EXIT_REASON_TPR: 2825 vlapic = vm_lapic(vcpu->vcpu); 2826 vlapic_sync_tpr(vlapic); 2827 vmexit->inst_length = 0; 2828 handled = HANDLED; 2829 break; 2830 case EXIT_REASON_VMCALL: 2831 case EXIT_REASON_VMCLEAR: 2832 case EXIT_REASON_VMLAUNCH: 2833 case EXIT_REASON_VMPTRLD: 2834 case EXIT_REASON_VMPTRST: 2835 case EXIT_REASON_VMREAD: 2836 case EXIT_REASON_VMRESUME: 2837 case EXIT_REASON_VMWRITE: 2838 case EXIT_REASON_VMXOFF: 2839 case EXIT_REASON_VMXON: 2840 SDT_PROBE3(vmm, vmx, exit, vminsn, vmx, vcpuid, vmexit); 2841 vmexit->exitcode = VM_EXITCODE_VMINSN; 2842 break; 2843 case EXIT_REASON_INVD: 2844 case EXIT_REASON_WBINVD: 2845 /* ignore exit */ 2846 handled = HANDLED; 2847 break; 2848 default: 2849 SDT_PROBE4(vmm, vmx, exit, unknown, 2850 vmx, vcpuid, vmexit, reason); 2851 vmm_stat_incr(vcpu->vcpu, VMEXIT_UNKNOWN, 1); 2852 break; 2853 } 2854 2855 if (handled) { 2856 /* 2857 * It is possible that control is returned to userland 2858 * even though we were able to handle the VM exit in the 2859 * kernel. 2860 * 2861 * In such a case we want to make sure that the userland 2862 * restarts guest execution at the instruction *after* 2863 * the one we just processed. Therefore we update the 2864 * guest rip in the VMCS and in 'vmexit'. 2865 */ 2866 vmexit->rip += vmexit->inst_length; 2867 vmexit->inst_length = 0; 2868 vmcs_write(VMCS_GUEST_RIP, vmexit->rip); 2869 } else { 2870 if (vmexit->exitcode == VM_EXITCODE_BOGUS) { 2871 /* 2872 * If this VM exit was not claimed by anybody then 2873 * treat it as a generic VMX exit. 2874 */ 2875 vmexit->exitcode = VM_EXITCODE_VMX; 2876 vmexit->u.vmx.status = VM_SUCCESS; 2877 vmexit->u.vmx.inst_type = 0; 2878 vmexit->u.vmx.inst_error = 0; 2879 } else { 2880 /* 2881 * The exitcode and collateral have been populated. 2882 * The VM exit will be processed further in userland. 2883 */ 2884 } 2885 } 2886 2887 SDT_PROBE4(vmm, vmx, exit, return, 2888 vmx, vcpuid, vmexit, handled); 2889 return (handled); 2890 } 2891 2892 static __inline void 2893 vmx_exit_inst_error(struct vmxctx *vmxctx, int rc, struct vm_exit *vmexit) 2894 { 2895 2896 KASSERT(vmxctx->inst_fail_status != VM_SUCCESS, 2897 ("vmx_exit_inst_error: invalid inst_fail_status %d", 2898 vmxctx->inst_fail_status)); 2899 2900 vmexit->inst_length = 0; 2901 vmexit->exitcode = VM_EXITCODE_VMX; 2902 vmexit->u.vmx.status = vmxctx->inst_fail_status; 2903 vmexit->u.vmx.inst_error = vmcs_instruction_error(); 2904 vmexit->u.vmx.exit_reason = ~0; 2905 vmexit->u.vmx.exit_qualification = ~0; 2906 2907 switch (rc) { 2908 case VMX_VMRESUME_ERROR: 2909 case VMX_VMLAUNCH_ERROR: 2910 vmexit->u.vmx.inst_type = rc; 2911 break; 2912 default: 2913 panic("vm_exit_inst_error: vmx_enter_guest returned %d", rc); 2914 } 2915 } 2916 2917 /* 2918 * If the NMI-exiting VM execution control is set to '1' then an NMI in 2919 * non-root operation causes a VM-exit. NMI blocking is in effect so it is 2920 * sufficient to simply vector to the NMI handler via a software interrupt. 2921 * However, this must be done before maskable interrupts are enabled 2922 * otherwise the "iret" issued by an interrupt handler will incorrectly 2923 * clear NMI blocking. 2924 */ 2925 static __inline void 2926 vmx_exit_handle_nmi(struct vmx_vcpu *vcpu, struct vm_exit *vmexit) 2927 { 2928 uint32_t intr_info; 2929 2930 KASSERT((read_rflags() & PSL_I) == 0, ("interrupts enabled")); 2931 2932 if (vmexit->u.vmx.exit_reason != EXIT_REASON_EXCEPTION) 2933 return; 2934 2935 intr_info = vmcs_read(VMCS_EXIT_INTR_INFO); 2936 KASSERT((intr_info & VMCS_INTR_VALID) != 0, 2937 ("VM exit interruption info invalid: %#x", intr_info)); 2938 2939 if ((intr_info & VMCS_INTR_T_MASK) == VMCS_INTR_T_NMI) { 2940 KASSERT((intr_info & 0xff) == IDT_NMI, ("VM exit due " 2941 "to NMI has invalid vector: %#x", intr_info)); 2942 VMX_CTR0(vcpu, "Vectoring to NMI handler"); 2943 __asm __volatile("int $2"); 2944 } 2945 } 2946 2947 static __inline void 2948 vmx_dr_enter_guest(struct vmxctx *vmxctx) 2949 { 2950 register_t rflags; 2951 2952 /* Save host control debug registers. */ 2953 vmxctx->host_dr7 = rdr7(); 2954 vmxctx->host_debugctl = rdmsr(MSR_DEBUGCTLMSR); 2955 2956 /* 2957 * Disable debugging in DR7 and DEBUGCTL to avoid triggering 2958 * exceptions in the host based on the guest DRx values. The 2959 * guest DR7 and DEBUGCTL are saved/restored in the VMCS. 2960 */ 2961 load_dr7(0); 2962 wrmsr(MSR_DEBUGCTLMSR, 0); 2963 2964 /* 2965 * Disable single stepping the kernel to avoid corrupting the 2966 * guest DR6. A debugger might still be able to corrupt the 2967 * guest DR6 by setting a breakpoint after this point and then 2968 * single stepping. 2969 */ 2970 rflags = read_rflags(); 2971 vmxctx->host_tf = rflags & PSL_T; 2972 write_rflags(rflags & ~PSL_T); 2973 2974 /* Save host debug registers. */ 2975 vmxctx->host_dr0 = rdr0(); 2976 vmxctx->host_dr1 = rdr1(); 2977 vmxctx->host_dr2 = rdr2(); 2978 vmxctx->host_dr3 = rdr3(); 2979 vmxctx->host_dr6 = rdr6(); 2980 2981 /* Restore guest debug registers. */ 2982 load_dr0(vmxctx->guest_dr0); 2983 load_dr1(vmxctx->guest_dr1); 2984 load_dr2(vmxctx->guest_dr2); 2985 load_dr3(vmxctx->guest_dr3); 2986 load_dr6(vmxctx->guest_dr6); 2987 } 2988 2989 static __inline void 2990 vmx_dr_leave_guest(struct vmxctx *vmxctx) 2991 { 2992 2993 /* Save guest debug registers. */ 2994 vmxctx->guest_dr0 = rdr0(); 2995 vmxctx->guest_dr1 = rdr1(); 2996 vmxctx->guest_dr2 = rdr2(); 2997 vmxctx->guest_dr3 = rdr3(); 2998 vmxctx->guest_dr6 = rdr6(); 2999 3000 /* 3001 * Restore host debug registers. Restore DR7, DEBUGCTL, and 3002 * PSL_T last. 3003 */ 3004 load_dr0(vmxctx->host_dr0); 3005 load_dr1(vmxctx->host_dr1); 3006 load_dr2(vmxctx->host_dr2); 3007 load_dr3(vmxctx->host_dr3); 3008 load_dr6(vmxctx->host_dr6); 3009 wrmsr(MSR_DEBUGCTLMSR, vmxctx->host_debugctl); 3010 load_dr7(vmxctx->host_dr7); 3011 write_rflags(read_rflags() | vmxctx->host_tf); 3012 } 3013 3014 static __inline void 3015 vmx_pmap_activate(struct vmx *vmx, pmap_t pmap) 3016 { 3017 long eptgen; 3018 int cpu; 3019 3020 cpu = curcpu; 3021 3022 CPU_SET_ATOMIC(cpu, &pmap->pm_active); 3023 smr_enter(pmap->pm_eptsmr); 3024 eptgen = atomic_load_long(&pmap->pm_eptgen); 3025 if (eptgen != vmx->eptgen[cpu]) { 3026 vmx->eptgen[cpu] = eptgen; 3027 invept(INVEPT_TYPE_SINGLE_CONTEXT, 3028 (struct invept_desc){ .eptp = vmx->eptp, ._res = 0 }); 3029 } 3030 } 3031 3032 static __inline void 3033 vmx_pmap_deactivate(struct vmx *vmx, pmap_t pmap) 3034 { 3035 smr_exit(pmap->pm_eptsmr); 3036 CPU_CLR_ATOMIC(curcpu, &pmap->pm_active); 3037 } 3038 3039 static int 3040 vmx_run(void *vcpui, register_t rip, pmap_t pmap, struct vm_eventinfo *evinfo) 3041 { 3042 int rc, handled, launched; 3043 struct vmx *vmx; 3044 struct vmx_vcpu *vcpu; 3045 struct vmxctx *vmxctx; 3046 struct vmcs *vmcs; 3047 struct vm_exit *vmexit; 3048 struct vlapic *vlapic; 3049 uint32_t exit_reason; 3050 struct region_descriptor gdtr, idtr; 3051 uint16_t ldt_sel; 3052 3053 vcpu = vcpui; 3054 vmx = vcpu->vmx; 3055 vmcs = vcpu->vmcs; 3056 vmxctx = &vcpu->ctx; 3057 vlapic = vm_lapic(vcpu->vcpu); 3058 vmexit = vm_exitinfo(vcpu->vcpu); 3059 launched = 0; 3060 3061 KASSERT(vmxctx->pmap == pmap, 3062 ("pmap %p different than ctx pmap %p", pmap, vmxctx->pmap)); 3063 3064 vmx_msr_guest_enter(vcpu); 3065 3066 VMPTRLD(vmcs); 3067 3068 /* 3069 * XXX 3070 * We do this every time because we may setup the virtual machine 3071 * from a different process than the one that actually runs it. 3072 * 3073 * If the life of a virtual machine was spent entirely in the context 3074 * of a single process we could do this once in vmx_init(). 3075 */ 3076 vmcs_write(VMCS_HOST_CR3, rcr3()); 3077 3078 vmcs_write(VMCS_GUEST_RIP, rip); 3079 vmx_set_pcpu_defaults(vmx, vcpu, pmap); 3080 do { 3081 KASSERT(vmcs_guest_rip() == rip, ("%s: vmcs guest rip mismatch " 3082 "%#lx/%#lx", __func__, vmcs_guest_rip(), rip)); 3083 3084 handled = UNHANDLED; 3085 /* 3086 * Interrupts are disabled from this point on until the 3087 * guest starts executing. This is done for the following 3088 * reasons: 3089 * 3090 * If an AST is asserted on this thread after the check below, 3091 * then the IPI_AST notification will not be lost, because it 3092 * will cause a VM exit due to external interrupt as soon as 3093 * the guest state is loaded. 3094 * 3095 * A posted interrupt after 'vmx_inject_interrupts()' will 3096 * not be "lost" because it will be held pending in the host 3097 * APIC because interrupts are disabled. The pending interrupt 3098 * will be recognized as soon as the guest state is loaded. 3099 * 3100 * The same reasoning applies to the IPI generated by 3101 * pmap_invalidate_ept(). 3102 */ 3103 disable_intr(); 3104 vmx_inject_interrupts(vcpu, vlapic, rip); 3105 3106 /* 3107 * Check for vcpu suspension after injecting events because 3108 * vmx_inject_interrupts() can suspend the vcpu due to a 3109 * triple fault. 3110 */ 3111 if (vcpu_suspended(evinfo)) { 3112 enable_intr(); 3113 vm_exit_suspended(vcpu->vcpu, rip); 3114 break; 3115 } 3116 3117 if (vcpu_rendezvous_pending(vcpu->vcpu, evinfo)) { 3118 enable_intr(); 3119 vm_exit_rendezvous(vcpu->vcpu, rip); 3120 break; 3121 } 3122 3123 if (vcpu_reqidle(evinfo)) { 3124 enable_intr(); 3125 vm_exit_reqidle(vcpu->vcpu, rip); 3126 break; 3127 } 3128 3129 if (vcpu_should_yield(vcpu->vcpu)) { 3130 enable_intr(); 3131 vm_exit_astpending(vcpu->vcpu, rip); 3132 vmx_astpending_trace(vcpu, rip); 3133 handled = HANDLED; 3134 break; 3135 } 3136 3137 if (vcpu_debugged(vcpu->vcpu)) { 3138 enable_intr(); 3139 vm_exit_debug(vcpu->vcpu, rip); 3140 break; 3141 } 3142 3143 /* 3144 * If TPR Shadowing is enabled, the TPR Threshold 3145 * must be updated right before entering the guest. 3146 */ 3147 if (tpr_shadowing && !virtual_interrupt_delivery) { 3148 if ((vcpu->cap.proc_ctls & PROCBASED_USE_TPR_SHADOW) != 0) { 3149 vmcs_write(VMCS_TPR_THRESHOLD, vlapic_get_cr8(vlapic)); 3150 } 3151 } 3152 3153 /* 3154 * VM exits restore the base address but not the 3155 * limits of GDTR and IDTR. The VMCS only stores the 3156 * base address, so VM exits set the limits to 0xffff. 3157 * Save and restore the full GDTR and IDTR to restore 3158 * the limits. 3159 * 3160 * The VMCS does not save the LDTR at all, and VM 3161 * exits clear LDTR as if a NULL selector were loaded. 3162 * The userspace hypervisor probably doesn't use a 3163 * LDT, but save and restore it to be safe. 3164 */ 3165 sgdt(&gdtr); 3166 sidt(&idtr); 3167 ldt_sel = sldt(); 3168 3169 /* 3170 * The TSC_AUX MSR must be saved/restored while interrupts 3171 * are disabled so that it is not possible for the guest 3172 * TSC_AUX MSR value to be overwritten by the resume 3173 * portion of the IPI_SUSPEND codepath. This is why the 3174 * transition of this MSR is handled separately from those 3175 * handled by vmx_msr_guest_{enter,exit}(), which are ok to 3176 * be transitioned with preemption disabled but interrupts 3177 * enabled. 3178 * 3179 * These vmx_msr_guest_{enter,exit}_tsc_aux() calls can be 3180 * anywhere in this loop so long as they happen with 3181 * interrupts disabled. This location is chosen for 3182 * simplicity. 3183 */ 3184 vmx_msr_guest_enter_tsc_aux(vmx, vcpu); 3185 3186 vmx_dr_enter_guest(vmxctx); 3187 3188 /* 3189 * Mark the EPT as active on this host CPU and invalidate 3190 * EPTP-tagged TLB entries if required. 3191 */ 3192 vmx_pmap_activate(vmx, pmap); 3193 3194 vmx_run_trace(vcpu); 3195 rc = vmx_enter_guest(vmxctx, vmx, launched); 3196 3197 vmx_pmap_deactivate(vmx, pmap); 3198 vmx_dr_leave_guest(vmxctx); 3199 vmx_msr_guest_exit_tsc_aux(vmx, vcpu); 3200 3201 bare_lgdt(&gdtr); 3202 lidt(&idtr); 3203 lldt(ldt_sel); 3204 3205 /* Collect some information for VM exit processing */ 3206 vmexit->rip = rip = vmcs_guest_rip(); 3207 vmexit->inst_length = vmexit_instruction_length(); 3208 vmexit->u.vmx.exit_reason = exit_reason = vmcs_exit_reason(); 3209 vmexit->u.vmx.exit_qualification = vmcs_exit_qualification(); 3210 3211 /* Update 'nextrip' */ 3212 vcpu->state.nextrip = rip; 3213 3214 if (rc == VMX_GUEST_VMEXIT) { 3215 vmx_exit_handle_nmi(vcpu, vmexit); 3216 enable_intr(); 3217 handled = vmx_exit_process(vmx, vcpu, vmexit); 3218 } else { 3219 enable_intr(); 3220 vmx_exit_inst_error(vmxctx, rc, vmexit); 3221 } 3222 launched = 1; 3223 vmx_exit_trace(vcpu, rip, exit_reason, handled); 3224 rip = vmexit->rip; 3225 } while (handled); 3226 3227 /* 3228 * If a VM exit has been handled then the exitcode must be BOGUS 3229 * If a VM exit is not handled then the exitcode must not be BOGUS 3230 */ 3231 if ((handled && vmexit->exitcode != VM_EXITCODE_BOGUS) || 3232 (!handled && vmexit->exitcode == VM_EXITCODE_BOGUS)) { 3233 panic("Mismatch between handled (%d) and exitcode (%d)", 3234 handled, vmexit->exitcode); 3235 } 3236 3237 VMX_CTR1(vcpu, "returning from vmx_run: exitcode %d", 3238 vmexit->exitcode); 3239 3240 VMCLEAR(vmcs); 3241 vmx_msr_guest_exit(vcpu); 3242 3243 return (0); 3244 } 3245 3246 static void 3247 vmx_vcpu_cleanup(void *vcpui) 3248 { 3249 struct vmx_vcpu *vcpu = vcpui; 3250 3251 vpid_free(vcpu->state.vpid); 3252 free(vcpu->pir_desc, M_VMX); 3253 free(vcpu->apic_page, M_VMX); 3254 free(vcpu->vmcs, M_VMX); 3255 free(vcpu, M_VMX); 3256 } 3257 3258 static void 3259 vmx_cleanup(void *vmi) 3260 { 3261 struct vmx *vmx = vmi; 3262 3263 if (virtual_interrupt_delivery) 3264 vm_unmap_mmio(vmx->vm, DEFAULT_APIC_BASE, PAGE_SIZE); 3265 3266 free(vmx->msr_bitmap, M_VMX); 3267 free(vmx, M_VMX); 3268 3269 return; 3270 } 3271 3272 static register_t * 3273 vmxctx_regptr(struct vmxctx *vmxctx, int reg) 3274 { 3275 3276 switch (reg) { 3277 case VM_REG_GUEST_RAX: 3278 return (&vmxctx->guest_rax); 3279 case VM_REG_GUEST_RBX: 3280 return (&vmxctx->guest_rbx); 3281 case VM_REG_GUEST_RCX: 3282 return (&vmxctx->guest_rcx); 3283 case VM_REG_GUEST_RDX: 3284 return (&vmxctx->guest_rdx); 3285 case VM_REG_GUEST_RSI: 3286 return (&vmxctx->guest_rsi); 3287 case VM_REG_GUEST_RDI: 3288 return (&vmxctx->guest_rdi); 3289 case VM_REG_GUEST_RBP: 3290 return (&vmxctx->guest_rbp); 3291 case VM_REG_GUEST_R8: 3292 return (&vmxctx->guest_r8); 3293 case VM_REG_GUEST_R9: 3294 return (&vmxctx->guest_r9); 3295 case VM_REG_GUEST_R10: 3296 return (&vmxctx->guest_r10); 3297 case VM_REG_GUEST_R11: 3298 return (&vmxctx->guest_r11); 3299 case VM_REG_GUEST_R12: 3300 return (&vmxctx->guest_r12); 3301 case VM_REG_GUEST_R13: 3302 return (&vmxctx->guest_r13); 3303 case VM_REG_GUEST_R14: 3304 return (&vmxctx->guest_r14); 3305 case VM_REG_GUEST_R15: 3306 return (&vmxctx->guest_r15); 3307 case VM_REG_GUEST_CR2: 3308 return (&vmxctx->guest_cr2); 3309 case VM_REG_GUEST_DR0: 3310 return (&vmxctx->guest_dr0); 3311 case VM_REG_GUEST_DR1: 3312 return (&vmxctx->guest_dr1); 3313 case VM_REG_GUEST_DR2: 3314 return (&vmxctx->guest_dr2); 3315 case VM_REG_GUEST_DR3: 3316 return (&vmxctx->guest_dr3); 3317 case VM_REG_GUEST_DR6: 3318 return (&vmxctx->guest_dr6); 3319 default: 3320 break; 3321 } 3322 return (NULL); 3323 } 3324 3325 static int 3326 vmxctx_getreg(struct vmxctx *vmxctx, int reg, uint64_t *retval) 3327 { 3328 register_t *regp; 3329 3330 if ((regp = vmxctx_regptr(vmxctx, reg)) != NULL) { 3331 *retval = *regp; 3332 return (0); 3333 } else 3334 return (EINVAL); 3335 } 3336 3337 static int 3338 vmxctx_setreg(struct vmxctx *vmxctx, int reg, uint64_t val) 3339 { 3340 register_t *regp; 3341 3342 if ((regp = vmxctx_regptr(vmxctx, reg)) != NULL) { 3343 *regp = val; 3344 return (0); 3345 } else 3346 return (EINVAL); 3347 } 3348 3349 static int 3350 vmx_get_intr_shadow(struct vmx_vcpu *vcpu, int running, uint64_t *retval) 3351 { 3352 uint64_t gi; 3353 int error; 3354 3355 error = vmcs_getreg(vcpu->vmcs, running, 3356 VMCS_IDENT(VMCS_GUEST_INTERRUPTIBILITY), &gi); 3357 *retval = (gi & HWINTR_BLOCKING) ? 1 : 0; 3358 return (error); 3359 } 3360 3361 static int 3362 vmx_modify_intr_shadow(struct vmx_vcpu *vcpu, int running, uint64_t val) 3363 { 3364 struct vmcs *vmcs; 3365 uint64_t gi; 3366 int error, ident; 3367 3368 /* 3369 * Forcing the vcpu into an interrupt shadow is not supported. 3370 */ 3371 if (val) { 3372 error = EINVAL; 3373 goto done; 3374 } 3375 3376 vmcs = vcpu->vmcs; 3377 ident = VMCS_IDENT(VMCS_GUEST_INTERRUPTIBILITY); 3378 error = vmcs_getreg(vmcs, running, ident, &gi); 3379 if (error == 0) { 3380 gi &= ~HWINTR_BLOCKING; 3381 error = vmcs_setreg(vmcs, running, ident, gi); 3382 } 3383 done: 3384 VMX_CTR2(vcpu, "Setting intr_shadow to %#lx %s", val, 3385 error ? "failed" : "succeeded"); 3386 return (error); 3387 } 3388 3389 static int 3390 vmx_shadow_reg(int reg) 3391 { 3392 int shreg; 3393 3394 shreg = -1; 3395 3396 switch (reg) { 3397 case VM_REG_GUEST_CR0: 3398 shreg = VMCS_CR0_SHADOW; 3399 break; 3400 case VM_REG_GUEST_CR4: 3401 shreg = VMCS_CR4_SHADOW; 3402 break; 3403 default: 3404 break; 3405 } 3406 3407 return (shreg); 3408 } 3409 3410 static int 3411 vmx_getreg(void *vcpui, int reg, uint64_t *retval) 3412 { 3413 int running, hostcpu; 3414 struct vmx_vcpu *vcpu = vcpui; 3415 struct vmx *vmx = vcpu->vmx; 3416 3417 running = vcpu_is_running(vcpu->vcpu, &hostcpu); 3418 if (running && hostcpu != curcpu) 3419 panic("vmx_getreg: %s%d is running", vm_name(vmx->vm), 3420 vcpu->vcpuid); 3421 3422 switch (reg) { 3423 case VM_REG_GUEST_INTR_SHADOW: 3424 return (vmx_get_intr_shadow(vcpu, running, retval)); 3425 case VM_REG_GUEST_KGS_BASE: 3426 *retval = vcpu->guest_msrs[IDX_MSR_KGSBASE]; 3427 return (0); 3428 case VM_REG_GUEST_TPR: 3429 *retval = vlapic_get_cr8(vm_lapic(vcpu->vcpu)); 3430 return (0); 3431 } 3432 3433 if (vmxctx_getreg(&vcpu->ctx, reg, retval) == 0) 3434 return (0); 3435 3436 return (vmcs_getreg(vcpu->vmcs, running, reg, retval)); 3437 } 3438 3439 static int 3440 vmx_setreg(void *vcpui, int reg, uint64_t val) 3441 { 3442 int error, hostcpu, running, shadow; 3443 uint64_t ctls; 3444 pmap_t pmap; 3445 struct vmx_vcpu *vcpu = vcpui; 3446 struct vmx *vmx = vcpu->vmx; 3447 3448 running = vcpu_is_running(vcpu->vcpu, &hostcpu); 3449 if (running && hostcpu != curcpu) 3450 panic("vmx_setreg: %s%d is running", vm_name(vmx->vm), 3451 vcpu->vcpuid); 3452 3453 if (reg == VM_REG_GUEST_INTR_SHADOW) 3454 return (vmx_modify_intr_shadow(vcpu, running, val)); 3455 3456 if (vmxctx_setreg(&vcpu->ctx, reg, val) == 0) 3457 return (0); 3458 3459 /* Do not permit user write access to VMCS fields by offset. */ 3460 if (reg < 0) 3461 return (EINVAL); 3462 3463 error = vmcs_setreg(vcpu->vmcs, running, reg, val); 3464 3465 if (error == 0) { 3466 /* 3467 * If the "load EFER" VM-entry control is 1 then the 3468 * value of EFER.LMA must be identical to "IA-32e mode guest" 3469 * bit in the VM-entry control. 3470 */ 3471 if ((entry_ctls & VM_ENTRY_LOAD_EFER) != 0 && 3472 (reg == VM_REG_GUEST_EFER)) { 3473 vmcs_getreg(vcpu->vmcs, running, 3474 VMCS_IDENT(VMCS_ENTRY_CTLS), &ctls); 3475 if (val & EFER_LMA) 3476 ctls |= VM_ENTRY_GUEST_LMA; 3477 else 3478 ctls &= ~VM_ENTRY_GUEST_LMA; 3479 vmcs_setreg(vcpu->vmcs, running, 3480 VMCS_IDENT(VMCS_ENTRY_CTLS), ctls); 3481 } 3482 3483 shadow = vmx_shadow_reg(reg); 3484 if (shadow > 0) { 3485 /* 3486 * Store the unmodified value in the shadow 3487 */ 3488 error = vmcs_setreg(vcpu->vmcs, running, 3489 VMCS_IDENT(shadow), val); 3490 } 3491 3492 if (reg == VM_REG_GUEST_CR3) { 3493 /* 3494 * Invalidate the guest vcpu's TLB mappings to emulate 3495 * the behavior of updating %cr3. 3496 * 3497 * XXX the processor retains global mappings when %cr3 3498 * is updated but vmx_invvpid() does not. 3499 */ 3500 pmap = vcpu->ctx.pmap; 3501 vmx_invvpid(vmx, vcpu, pmap, running); 3502 } 3503 } 3504 3505 return (error); 3506 } 3507 3508 static int 3509 vmx_getdesc(void *vcpui, int reg, struct seg_desc *desc) 3510 { 3511 int hostcpu, running; 3512 struct vmx_vcpu *vcpu = vcpui; 3513 struct vmx *vmx = vcpu->vmx; 3514 3515 running = vcpu_is_running(vcpu->vcpu, &hostcpu); 3516 if (running && hostcpu != curcpu) 3517 panic("vmx_getdesc: %s%d is running", vm_name(vmx->vm), 3518 vcpu->vcpuid); 3519 3520 return (vmcs_getdesc(vcpu->vmcs, running, reg, desc)); 3521 } 3522 3523 static int 3524 vmx_setdesc(void *vcpui, int reg, struct seg_desc *desc) 3525 { 3526 int hostcpu, running; 3527 struct vmx_vcpu *vcpu = vcpui; 3528 struct vmx *vmx = vcpu->vmx; 3529 3530 running = vcpu_is_running(vcpu->vcpu, &hostcpu); 3531 if (running && hostcpu != curcpu) 3532 panic("vmx_setdesc: %s%d is running", vm_name(vmx->vm), 3533 vcpu->vcpuid); 3534 3535 return (vmcs_setdesc(vcpu->vmcs, running, reg, desc)); 3536 } 3537 3538 static int 3539 vmx_getcap(void *vcpui, int type, int *retval) 3540 { 3541 struct vmx_vcpu *vcpu = vcpui; 3542 int vcap; 3543 int ret; 3544 3545 ret = ENOENT; 3546 3547 vcap = vcpu->cap.set; 3548 3549 switch (type) { 3550 case VM_CAP_HALT_EXIT: 3551 if (cap_halt_exit) 3552 ret = 0; 3553 break; 3554 case VM_CAP_PAUSE_EXIT: 3555 if (cap_pause_exit) 3556 ret = 0; 3557 break; 3558 case VM_CAP_MTRAP_EXIT: 3559 if (cap_monitor_trap) 3560 ret = 0; 3561 break; 3562 case VM_CAP_RDPID: 3563 if (cap_rdpid) 3564 ret = 0; 3565 break; 3566 case VM_CAP_RDTSCP: 3567 if (cap_rdtscp) 3568 ret = 0; 3569 break; 3570 case VM_CAP_UNRESTRICTED_GUEST: 3571 if (cap_unrestricted_guest) 3572 ret = 0; 3573 break; 3574 case VM_CAP_ENABLE_INVPCID: 3575 if (cap_invpcid) 3576 ret = 0; 3577 break; 3578 case VM_CAP_BPT_EXIT: 3579 case VM_CAP_IPI_EXIT: 3580 ret = 0; 3581 break; 3582 default: 3583 break; 3584 } 3585 3586 if (ret == 0) 3587 *retval = (vcap & (1 << type)) ? 1 : 0; 3588 3589 return (ret); 3590 } 3591 3592 static int 3593 vmx_setcap(void *vcpui, int type, int val) 3594 { 3595 struct vmx_vcpu *vcpu = vcpui; 3596 struct vmcs *vmcs = vcpu->vmcs; 3597 struct vlapic *vlapic; 3598 uint32_t baseval; 3599 uint32_t *pptr; 3600 int error; 3601 int flag; 3602 int reg; 3603 int retval; 3604 3605 retval = ENOENT; 3606 pptr = NULL; 3607 3608 switch (type) { 3609 case VM_CAP_HALT_EXIT: 3610 if (cap_halt_exit) { 3611 retval = 0; 3612 pptr = &vcpu->cap.proc_ctls; 3613 baseval = *pptr; 3614 flag = PROCBASED_HLT_EXITING; 3615 reg = VMCS_PRI_PROC_BASED_CTLS; 3616 } 3617 break; 3618 case VM_CAP_MTRAP_EXIT: 3619 if (cap_monitor_trap) { 3620 retval = 0; 3621 pptr = &vcpu->cap.proc_ctls; 3622 baseval = *pptr; 3623 flag = PROCBASED_MTF; 3624 reg = VMCS_PRI_PROC_BASED_CTLS; 3625 } 3626 break; 3627 case VM_CAP_PAUSE_EXIT: 3628 if (cap_pause_exit) { 3629 retval = 0; 3630 pptr = &vcpu->cap.proc_ctls; 3631 baseval = *pptr; 3632 flag = PROCBASED_PAUSE_EXITING; 3633 reg = VMCS_PRI_PROC_BASED_CTLS; 3634 } 3635 break; 3636 case VM_CAP_RDPID: 3637 case VM_CAP_RDTSCP: 3638 if (cap_rdpid || cap_rdtscp) 3639 /* 3640 * Choose not to support enabling/disabling 3641 * RDPID/RDTSCP via libvmmapi since, as per the 3642 * discussion in vmx_modinit(), RDPID/RDTSCP are 3643 * either always enabled or always disabled. 3644 */ 3645 error = EOPNOTSUPP; 3646 break; 3647 case VM_CAP_UNRESTRICTED_GUEST: 3648 if (cap_unrestricted_guest) { 3649 retval = 0; 3650 pptr = &vcpu->cap.proc_ctls2; 3651 baseval = *pptr; 3652 flag = PROCBASED2_UNRESTRICTED_GUEST; 3653 reg = VMCS_SEC_PROC_BASED_CTLS; 3654 } 3655 break; 3656 case VM_CAP_ENABLE_INVPCID: 3657 if (cap_invpcid) { 3658 retval = 0; 3659 pptr = &vcpu->cap.proc_ctls2; 3660 baseval = *pptr; 3661 flag = PROCBASED2_ENABLE_INVPCID; 3662 reg = VMCS_SEC_PROC_BASED_CTLS; 3663 } 3664 break; 3665 case VM_CAP_BPT_EXIT: 3666 retval = 0; 3667 3668 /* Don't change the bitmap if we are tracing all exceptions. */ 3669 if (vcpu->cap.exc_bitmap != 0xffffffff) { 3670 pptr = &vcpu->cap.exc_bitmap; 3671 baseval = *pptr; 3672 flag = (1 << IDT_BP); 3673 reg = VMCS_EXCEPTION_BITMAP; 3674 } 3675 break; 3676 case VM_CAP_IPI_EXIT: 3677 retval = 0; 3678 3679 vlapic = vm_lapic(vcpu->vcpu); 3680 vlapic->ipi_exit = val; 3681 break; 3682 case VM_CAP_MASK_HWINTR: 3683 retval = 0; 3684 break; 3685 default: 3686 break; 3687 } 3688 3689 if (retval) 3690 return (retval); 3691 3692 if (pptr != NULL) { 3693 if (val) { 3694 baseval |= flag; 3695 } else { 3696 baseval &= ~flag; 3697 } 3698 VMPTRLD(vmcs); 3699 error = vmwrite(reg, baseval); 3700 VMCLEAR(vmcs); 3701 3702 if (error) 3703 return (error); 3704 3705 /* 3706 * Update optional stored flags, and record 3707 * setting 3708 */ 3709 *pptr = baseval; 3710 } 3711 3712 if (val) { 3713 vcpu->cap.set |= (1 << type); 3714 } else { 3715 vcpu->cap.set &= ~(1 << type); 3716 } 3717 3718 return (0); 3719 } 3720 3721 static struct vmspace * 3722 vmx_vmspace_alloc(vm_offset_t min, vm_offset_t max) 3723 { 3724 return (ept_vmspace_alloc(min, max)); 3725 } 3726 3727 static void 3728 vmx_vmspace_free(struct vmspace *vmspace) 3729 { 3730 ept_vmspace_free(vmspace); 3731 } 3732 3733 struct vlapic_vtx { 3734 struct vlapic vlapic; 3735 struct pir_desc *pir_desc; 3736 struct vmx_vcpu *vcpu; 3737 u_int pending_prio; 3738 }; 3739 3740 #define VPR_PRIO_BIT(vpr) (1 << ((vpr) >> 4)) 3741 3742 #define VMX_CTR_PIR(vlapic, pir_desc, notify, vector, level, msg) \ 3743 do { \ 3744 VLAPIC_CTR2(vlapic, msg " assert %s-triggered vector %d", \ 3745 level ? "level" : "edge", vector); \ 3746 VLAPIC_CTR1(vlapic, msg " pir0 0x%016lx", pir_desc->pir[0]); \ 3747 VLAPIC_CTR1(vlapic, msg " pir1 0x%016lx", pir_desc->pir[1]); \ 3748 VLAPIC_CTR1(vlapic, msg " pir2 0x%016lx", pir_desc->pir[2]); \ 3749 VLAPIC_CTR1(vlapic, msg " pir3 0x%016lx", pir_desc->pir[3]); \ 3750 VLAPIC_CTR1(vlapic, msg " notify: %s", notify ? "yes" : "no"); \ 3751 } while (0) 3752 3753 /* 3754 * vlapic->ops handlers that utilize the APICv hardware assist described in 3755 * Chapter 29 of the Intel SDM. 3756 */ 3757 static int 3758 vmx_set_intr_ready(struct vlapic *vlapic, int vector, bool level) 3759 { 3760 struct vlapic_vtx *vlapic_vtx; 3761 struct pir_desc *pir_desc; 3762 uint64_t mask; 3763 int idx, notify = 0; 3764 3765 vlapic_vtx = (struct vlapic_vtx *)vlapic; 3766 pir_desc = vlapic_vtx->pir_desc; 3767 3768 /* 3769 * Keep track of interrupt requests in the PIR descriptor. This is 3770 * because the virtual APIC page pointed to by the VMCS cannot be 3771 * modified if the vcpu is running. 3772 */ 3773 idx = vector / 64; 3774 mask = 1UL << (vector % 64); 3775 atomic_set_long(&pir_desc->pir[idx], mask); 3776 3777 /* 3778 * A notification is required whenever the 'pending' bit makes a 3779 * transition from 0->1. 3780 * 3781 * Even if the 'pending' bit is already asserted, notification about 3782 * the incoming interrupt may still be necessary. For example, if a 3783 * vCPU is HLTed with a high PPR, a low priority interrupt would cause 3784 * the 0->1 'pending' transition with a notification, but the vCPU 3785 * would ignore the interrupt for the time being. The same vCPU would 3786 * need to then be notified if a high-priority interrupt arrived which 3787 * satisfied the PPR. 3788 * 3789 * The priorities of interrupts injected while 'pending' is asserted 3790 * are tracked in a custom bitfield 'pending_prio'. Should the 3791 * to-be-injected interrupt exceed the priorities already present, the 3792 * notification is sent. The priorities recorded in 'pending_prio' are 3793 * cleared whenever the 'pending' bit makes another 0->1 transition. 3794 */ 3795 if (atomic_cmpset_long(&pir_desc->pending, 0, 1) != 0) { 3796 notify = 1; 3797 vlapic_vtx->pending_prio = 0; 3798 } else { 3799 const u_int old_prio = vlapic_vtx->pending_prio; 3800 const u_int prio_bit = VPR_PRIO_BIT(vector & APIC_TPR_INT); 3801 3802 if ((old_prio & prio_bit) == 0 && prio_bit > old_prio) { 3803 atomic_set_int(&vlapic_vtx->pending_prio, prio_bit); 3804 notify = 1; 3805 } 3806 } 3807 3808 VMX_CTR_PIR(vlapic, pir_desc, notify, vector, level, 3809 "vmx_set_intr_ready"); 3810 return (notify); 3811 } 3812 3813 static int 3814 vmx_pending_intr(struct vlapic *vlapic, int *vecptr) 3815 { 3816 struct vlapic_vtx *vlapic_vtx; 3817 struct pir_desc *pir_desc; 3818 struct LAPIC *lapic; 3819 uint64_t pending, pirval; 3820 uint8_t ppr, vpr, rvi; 3821 struct vm_exit *vmexit; 3822 int i; 3823 3824 /* 3825 * This function is only expected to be called from the 'HLT' exit 3826 * handler which does not care about the vector that is pending. 3827 */ 3828 KASSERT(vecptr == NULL, ("vmx_pending_intr: vecptr must be NULL")); 3829 3830 vlapic_vtx = (struct vlapic_vtx *)vlapic; 3831 pir_desc = vlapic_vtx->pir_desc; 3832 lapic = vlapic->apic_page; 3833 3834 /* 3835 * While a virtual interrupt may have already been 3836 * processed the actual delivery maybe pending the 3837 * interruptibility of the guest. Recognize a pending 3838 * interrupt by reevaluating virtual interrupts 3839 * following Section 30.2.1 in the Intel SDM Volume 3. 3840 */ 3841 vmexit = vm_exitinfo(vlapic->vcpu); 3842 KASSERT(vmexit->exitcode == VM_EXITCODE_HLT, 3843 ("vmx_pending_intr: exitcode not 'HLT'")); 3844 rvi = vmexit->u.hlt.intr_status & APIC_TPR_INT; 3845 ppr = lapic->ppr & APIC_TPR_INT; 3846 if (rvi > ppr) 3847 return (1); 3848 3849 pending = atomic_load_acq_long(&pir_desc->pending); 3850 if (!pending) 3851 return (0); 3852 3853 /* 3854 * If there is an interrupt pending then it will be recognized only 3855 * if its priority is greater than the processor priority. 3856 * 3857 * Special case: if the processor priority is zero then any pending 3858 * interrupt will be recognized. 3859 */ 3860 if (ppr == 0) 3861 return (1); 3862 3863 VLAPIC_CTR1(vlapic, "HLT with non-zero PPR %d", lapic->ppr); 3864 3865 vpr = 0; 3866 for (i = 3; i >= 0; i--) { 3867 pirval = pir_desc->pir[i]; 3868 if (pirval != 0) { 3869 vpr = (i * 64 + flsl(pirval) - 1) & APIC_TPR_INT; 3870 break; 3871 } 3872 } 3873 3874 /* 3875 * If the highest-priority pending interrupt falls short of the 3876 * processor priority of this vCPU, ensure that 'pending_prio' does not 3877 * have any stale bits which would preclude a higher-priority interrupt 3878 * from incurring a notification later. 3879 */ 3880 if (vpr <= ppr) { 3881 const u_int prio_bit = VPR_PRIO_BIT(vpr); 3882 const u_int old = vlapic_vtx->pending_prio; 3883 3884 if (old > prio_bit && (old & prio_bit) == 0) { 3885 vlapic_vtx->pending_prio = prio_bit; 3886 } 3887 return (0); 3888 } 3889 return (1); 3890 } 3891 3892 static void 3893 vmx_intr_accepted(struct vlapic *vlapic, int vector) 3894 { 3895 3896 panic("vmx_intr_accepted: not expected to be called"); 3897 } 3898 3899 static void 3900 vmx_set_tmr(struct vlapic *vlapic, int vector, bool level) 3901 { 3902 struct vlapic_vtx *vlapic_vtx; 3903 struct vmcs *vmcs; 3904 uint64_t mask, val; 3905 3906 KASSERT(vector >= 0 && vector <= 255, ("invalid vector %d", vector)); 3907 KASSERT(!vcpu_is_running(vlapic->vcpu, NULL), 3908 ("vmx_set_tmr: vcpu cannot be running")); 3909 3910 vlapic_vtx = (struct vlapic_vtx *)vlapic; 3911 vmcs = vlapic_vtx->vcpu->vmcs; 3912 mask = 1UL << (vector % 64); 3913 3914 VMPTRLD(vmcs); 3915 val = vmcs_read(VMCS_EOI_EXIT(vector)); 3916 if (level) 3917 val |= mask; 3918 else 3919 val &= ~mask; 3920 vmcs_write(VMCS_EOI_EXIT(vector), val); 3921 VMCLEAR(vmcs); 3922 } 3923 3924 static void 3925 vmx_enable_x2apic_mode_ts(struct vlapic *vlapic) 3926 { 3927 struct vlapic_vtx *vlapic_vtx; 3928 struct vmx_vcpu *vcpu; 3929 struct vmcs *vmcs; 3930 uint32_t proc_ctls; 3931 3932 vlapic_vtx = (struct vlapic_vtx *)vlapic; 3933 vcpu = vlapic_vtx->vcpu; 3934 vmcs = vcpu->vmcs; 3935 3936 proc_ctls = vcpu->cap.proc_ctls; 3937 proc_ctls &= ~PROCBASED_USE_TPR_SHADOW; 3938 proc_ctls |= PROCBASED_CR8_LOAD_EXITING; 3939 proc_ctls |= PROCBASED_CR8_STORE_EXITING; 3940 vcpu->cap.proc_ctls = proc_ctls; 3941 3942 VMPTRLD(vmcs); 3943 vmcs_write(VMCS_PRI_PROC_BASED_CTLS, proc_ctls); 3944 VMCLEAR(vmcs); 3945 } 3946 3947 static void 3948 vmx_enable_x2apic_mode_vid(struct vlapic *vlapic) 3949 { 3950 struct vlapic_vtx *vlapic_vtx; 3951 struct vmx *vmx; 3952 struct vmx_vcpu *vcpu; 3953 struct vmcs *vmcs; 3954 uint32_t proc_ctls2; 3955 int error __diagused; 3956 3957 vlapic_vtx = (struct vlapic_vtx *)vlapic; 3958 vcpu = vlapic_vtx->vcpu; 3959 vmx = vcpu->vmx; 3960 vmcs = vcpu->vmcs; 3961 3962 proc_ctls2 = vcpu->cap.proc_ctls2; 3963 KASSERT((proc_ctls2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES) != 0, 3964 ("%s: invalid proc_ctls2 %#x", __func__, proc_ctls2)); 3965 3966 proc_ctls2 &= ~PROCBASED2_VIRTUALIZE_APIC_ACCESSES; 3967 proc_ctls2 |= PROCBASED2_VIRTUALIZE_X2APIC_MODE; 3968 vcpu->cap.proc_ctls2 = proc_ctls2; 3969 3970 VMPTRLD(vmcs); 3971 vmcs_write(VMCS_SEC_PROC_BASED_CTLS, proc_ctls2); 3972 VMCLEAR(vmcs); 3973 3974 if (vlapic->vcpuid == 0) { 3975 /* 3976 * The nested page table mappings are shared by all vcpus 3977 * so unmap the APIC access page just once. 3978 */ 3979 error = vm_unmap_mmio(vmx->vm, DEFAULT_APIC_BASE, PAGE_SIZE); 3980 KASSERT(error == 0, ("%s: vm_unmap_mmio error %d", 3981 __func__, error)); 3982 3983 /* 3984 * The MSR bitmap is shared by all vcpus so modify it only 3985 * once in the context of vcpu 0. 3986 */ 3987 error = vmx_allow_x2apic_msrs(vmx); 3988 KASSERT(error == 0, ("%s: vmx_allow_x2apic_msrs error %d", 3989 __func__, error)); 3990 } 3991 } 3992 3993 static void 3994 vmx_post_intr(struct vlapic *vlapic, int hostcpu) 3995 { 3996 3997 ipi_cpu(hostcpu, pirvec); 3998 } 3999 4000 /* 4001 * Transfer the pending interrupts in the PIR descriptor to the IRR 4002 * in the virtual APIC page. 4003 */ 4004 static void 4005 vmx_inject_pir(struct vlapic *vlapic) 4006 { 4007 struct vlapic_vtx *vlapic_vtx; 4008 struct pir_desc *pir_desc; 4009 struct LAPIC *lapic; 4010 uint64_t val, pirval; 4011 int rvi, pirbase = -1; 4012 uint16_t intr_status_old, intr_status_new; 4013 4014 vlapic_vtx = (struct vlapic_vtx *)vlapic; 4015 pir_desc = vlapic_vtx->pir_desc; 4016 if (atomic_cmpset_long(&pir_desc->pending, 1, 0) == 0) { 4017 VLAPIC_CTR0(vlapic, "vmx_inject_pir: " 4018 "no posted interrupt pending"); 4019 return; 4020 } 4021 4022 pirval = 0; 4023 pirbase = -1; 4024 lapic = vlapic->apic_page; 4025 4026 val = atomic_readandclear_long(&pir_desc->pir[0]); 4027 if (val != 0) { 4028 lapic->irr0 |= val; 4029 lapic->irr1 |= val >> 32; 4030 pirbase = 0; 4031 pirval = val; 4032 } 4033 4034 val = atomic_readandclear_long(&pir_desc->pir[1]); 4035 if (val != 0) { 4036 lapic->irr2 |= val; 4037 lapic->irr3 |= val >> 32; 4038 pirbase = 64; 4039 pirval = val; 4040 } 4041 4042 val = atomic_readandclear_long(&pir_desc->pir[2]); 4043 if (val != 0) { 4044 lapic->irr4 |= val; 4045 lapic->irr5 |= val >> 32; 4046 pirbase = 128; 4047 pirval = val; 4048 } 4049 4050 val = atomic_readandclear_long(&pir_desc->pir[3]); 4051 if (val != 0) { 4052 lapic->irr6 |= val; 4053 lapic->irr7 |= val >> 32; 4054 pirbase = 192; 4055 pirval = val; 4056 } 4057 4058 VLAPIC_CTR_IRR(vlapic, "vmx_inject_pir"); 4059 4060 /* 4061 * Update RVI so the processor can evaluate pending virtual 4062 * interrupts on VM-entry. 4063 * 4064 * It is possible for pirval to be 0 here, even though the 4065 * pending bit has been set. The scenario is: 4066 * CPU-Y is sending a posted interrupt to CPU-X, which 4067 * is running a guest and processing posted interrupts in h/w. 4068 * CPU-X will eventually exit and the state seen in s/w is 4069 * the pending bit set, but no PIR bits set. 4070 * 4071 * CPU-X CPU-Y 4072 * (vm running) (host running) 4073 * rx posted interrupt 4074 * CLEAR pending bit 4075 * SET PIR bit 4076 * READ/CLEAR PIR bits 4077 * SET pending bit 4078 * (vm exit) 4079 * pending bit set, PIR 0 4080 */ 4081 if (pirval != 0) { 4082 rvi = pirbase + flsl(pirval) - 1; 4083 intr_status_old = vmcs_read(VMCS_GUEST_INTR_STATUS); 4084 intr_status_new = (intr_status_old & 0xFF00) | rvi; 4085 if (intr_status_new > intr_status_old) { 4086 vmcs_write(VMCS_GUEST_INTR_STATUS, intr_status_new); 4087 VLAPIC_CTR2(vlapic, "vmx_inject_pir: " 4088 "guest_intr_status changed from 0x%04x to 0x%04x", 4089 intr_status_old, intr_status_new); 4090 } 4091 } 4092 } 4093 4094 static struct vlapic * 4095 vmx_vlapic_init(void *vcpui) 4096 { 4097 struct vmx *vmx; 4098 struct vmx_vcpu *vcpu; 4099 struct vlapic *vlapic; 4100 struct vlapic_vtx *vlapic_vtx; 4101 4102 vcpu = vcpui; 4103 vmx = vcpu->vmx; 4104 4105 vlapic = malloc(sizeof(struct vlapic_vtx), M_VLAPIC, M_WAITOK | M_ZERO); 4106 vlapic->vm = vmx->vm; 4107 vlapic->vcpu = vcpu->vcpu; 4108 vlapic->vcpuid = vcpu->vcpuid; 4109 vlapic->apic_page = (struct LAPIC *)vcpu->apic_page; 4110 4111 vlapic_vtx = (struct vlapic_vtx *)vlapic; 4112 vlapic_vtx->pir_desc = vcpu->pir_desc; 4113 vlapic_vtx->vcpu = vcpu; 4114 4115 if (tpr_shadowing) { 4116 vlapic->ops.enable_x2apic_mode = vmx_enable_x2apic_mode_ts; 4117 } 4118 4119 if (virtual_interrupt_delivery) { 4120 vlapic->ops.set_intr_ready = vmx_set_intr_ready; 4121 vlapic->ops.pending_intr = vmx_pending_intr; 4122 vlapic->ops.intr_accepted = vmx_intr_accepted; 4123 vlapic->ops.set_tmr = vmx_set_tmr; 4124 vlapic->ops.enable_x2apic_mode = vmx_enable_x2apic_mode_vid; 4125 } 4126 4127 if (posted_interrupts) 4128 vlapic->ops.post_intr = vmx_post_intr; 4129 4130 vlapic_init(vlapic); 4131 4132 return (vlapic); 4133 } 4134 4135 static void 4136 vmx_vlapic_cleanup(struct vlapic *vlapic) 4137 { 4138 4139 vlapic_cleanup(vlapic); 4140 free(vlapic, M_VLAPIC); 4141 } 4142 4143 #ifdef BHYVE_SNAPSHOT 4144 static int 4145 vmx_vcpu_snapshot(void *vcpui, struct vm_snapshot_meta *meta) 4146 { 4147 struct vmcs *vmcs; 4148 struct vmx *vmx; 4149 struct vmx_vcpu *vcpu; 4150 struct vmxctx *vmxctx; 4151 int err, run, hostcpu; 4152 4153 err = 0; 4154 vcpu = vcpui; 4155 vmx = vcpu->vmx; 4156 vmcs = vcpu->vmcs; 4157 4158 run = vcpu_is_running(vcpu->vcpu, &hostcpu); 4159 if (run && hostcpu != curcpu) { 4160 printf("%s: %s%d is running", __func__, vm_name(vmx->vm), 4161 vcpu->vcpuid); 4162 return (EINVAL); 4163 } 4164 4165 err += vmcs_snapshot_reg(vmcs, run, VM_REG_GUEST_CR0, meta); 4166 err += vmcs_snapshot_reg(vmcs, run, VM_REG_GUEST_CR3, meta); 4167 err += vmcs_snapshot_reg(vmcs, run, VM_REG_GUEST_CR4, meta); 4168 err += vmcs_snapshot_reg(vmcs, run, VM_REG_GUEST_DR7, meta); 4169 err += vmcs_snapshot_reg(vmcs, run, VM_REG_GUEST_RSP, meta); 4170 err += vmcs_snapshot_reg(vmcs, run, VM_REG_GUEST_RIP, meta); 4171 err += vmcs_snapshot_reg(vmcs, run, VM_REG_GUEST_RFLAGS, meta); 4172 4173 /* Guest segments */ 4174 err += vmcs_snapshot_reg(vmcs, run, VM_REG_GUEST_ES, meta); 4175 err += vmcs_snapshot_desc(vmcs, run, VM_REG_GUEST_ES, meta); 4176 4177 err += vmcs_snapshot_reg(vmcs, run, VM_REG_GUEST_CS, meta); 4178 err += vmcs_snapshot_desc(vmcs, run, VM_REG_GUEST_CS, meta); 4179 4180 err += vmcs_snapshot_reg(vmcs, run, VM_REG_GUEST_SS, meta); 4181 err += vmcs_snapshot_desc(vmcs, run, VM_REG_GUEST_SS, meta); 4182 4183 err += vmcs_snapshot_reg(vmcs, run, VM_REG_GUEST_DS, meta); 4184 err += vmcs_snapshot_desc(vmcs, run, VM_REG_GUEST_DS, meta); 4185 4186 err += vmcs_snapshot_reg(vmcs, run, VM_REG_GUEST_FS, meta); 4187 err += vmcs_snapshot_desc(vmcs, run, VM_REG_GUEST_FS, meta); 4188 4189 err += vmcs_snapshot_reg(vmcs, run, VM_REG_GUEST_GS, meta); 4190 err += vmcs_snapshot_desc(vmcs, run, VM_REG_GUEST_GS, meta); 4191 4192 err += vmcs_snapshot_reg(vmcs, run, VM_REG_GUEST_TR, meta); 4193 err += vmcs_snapshot_desc(vmcs, run, VM_REG_GUEST_TR, meta); 4194 4195 err += vmcs_snapshot_reg(vmcs, run, VM_REG_GUEST_LDTR, meta); 4196 err += vmcs_snapshot_desc(vmcs, run, VM_REG_GUEST_LDTR, meta); 4197 4198 err += vmcs_snapshot_reg(vmcs, run, VM_REG_GUEST_EFER, meta); 4199 4200 err += vmcs_snapshot_desc(vmcs, run, VM_REG_GUEST_IDTR, meta); 4201 err += vmcs_snapshot_desc(vmcs, run, VM_REG_GUEST_GDTR, meta); 4202 4203 /* Guest page tables */ 4204 err += vmcs_snapshot_reg(vmcs, run, VM_REG_GUEST_PDPTE0, meta); 4205 err += vmcs_snapshot_reg(vmcs, run, VM_REG_GUEST_PDPTE1, meta); 4206 err += vmcs_snapshot_reg(vmcs, run, VM_REG_GUEST_PDPTE2, meta); 4207 err += vmcs_snapshot_reg(vmcs, run, VM_REG_GUEST_PDPTE3, meta); 4208 4209 /* Other guest state */ 4210 err += vmcs_snapshot_any(vmcs, run, VMCS_GUEST_IA32_SYSENTER_CS, meta); 4211 err += vmcs_snapshot_any(vmcs, run, VMCS_GUEST_IA32_SYSENTER_ESP, meta); 4212 err += vmcs_snapshot_any(vmcs, run, VMCS_GUEST_IA32_SYSENTER_EIP, meta); 4213 err += vmcs_snapshot_any(vmcs, run, VMCS_GUEST_INTERRUPTIBILITY, meta); 4214 err += vmcs_snapshot_any(vmcs, run, VMCS_GUEST_ACTIVITY, meta); 4215 err += vmcs_snapshot_any(vmcs, run, VMCS_ENTRY_CTLS, meta); 4216 err += vmcs_snapshot_any(vmcs, run, VMCS_EXIT_CTLS, meta); 4217 if (err != 0) 4218 goto done; 4219 4220 SNAPSHOT_BUF_OR_LEAVE(vcpu->guest_msrs, 4221 sizeof(vcpu->guest_msrs), meta, err, done); 4222 4223 SNAPSHOT_BUF_OR_LEAVE(vcpu->pir_desc, 4224 sizeof(*vcpu->pir_desc), meta, err, done); 4225 4226 SNAPSHOT_BUF_OR_LEAVE(&vcpu->mtrr, 4227 sizeof(vcpu->mtrr), meta, err, done); 4228 4229 vmxctx = &vcpu->ctx; 4230 SNAPSHOT_VAR_OR_LEAVE(vmxctx->guest_rdi, meta, err, done); 4231 SNAPSHOT_VAR_OR_LEAVE(vmxctx->guest_rsi, meta, err, done); 4232 SNAPSHOT_VAR_OR_LEAVE(vmxctx->guest_rdx, meta, err, done); 4233 SNAPSHOT_VAR_OR_LEAVE(vmxctx->guest_rcx, meta, err, done); 4234 SNAPSHOT_VAR_OR_LEAVE(vmxctx->guest_r8, meta, err, done); 4235 SNAPSHOT_VAR_OR_LEAVE(vmxctx->guest_r9, meta, err, done); 4236 SNAPSHOT_VAR_OR_LEAVE(vmxctx->guest_rax, meta, err, done); 4237 SNAPSHOT_VAR_OR_LEAVE(vmxctx->guest_rbx, meta, err, done); 4238 SNAPSHOT_VAR_OR_LEAVE(vmxctx->guest_rbp, meta, err, done); 4239 SNAPSHOT_VAR_OR_LEAVE(vmxctx->guest_r10, meta, err, done); 4240 SNAPSHOT_VAR_OR_LEAVE(vmxctx->guest_r11, meta, err, done); 4241 SNAPSHOT_VAR_OR_LEAVE(vmxctx->guest_r12, meta, err, done); 4242 SNAPSHOT_VAR_OR_LEAVE(vmxctx->guest_r13, meta, err, done); 4243 SNAPSHOT_VAR_OR_LEAVE(vmxctx->guest_r14, meta, err, done); 4244 SNAPSHOT_VAR_OR_LEAVE(vmxctx->guest_r15, meta, err, done); 4245 SNAPSHOT_VAR_OR_LEAVE(vmxctx->guest_cr2, meta, err, done); 4246 SNAPSHOT_VAR_OR_LEAVE(vmxctx->guest_dr0, meta, err, done); 4247 SNAPSHOT_VAR_OR_LEAVE(vmxctx->guest_dr1, meta, err, done); 4248 SNAPSHOT_VAR_OR_LEAVE(vmxctx->guest_dr2, meta, err, done); 4249 SNAPSHOT_VAR_OR_LEAVE(vmxctx->guest_dr3, meta, err, done); 4250 SNAPSHOT_VAR_OR_LEAVE(vmxctx->guest_dr6, meta, err, done); 4251 4252 done: 4253 return (err); 4254 } 4255 4256 static int 4257 vmx_restore_tsc(void *vcpui, uint64_t offset) 4258 { 4259 struct vmx_vcpu *vcpu = vcpui; 4260 struct vmcs *vmcs; 4261 struct vmx *vmx; 4262 int error, running, hostcpu; 4263 4264 vmx = vcpu->vmx; 4265 vmcs = vcpu->vmcs; 4266 4267 running = vcpu_is_running(vcpu->vcpu, &hostcpu); 4268 if (running && hostcpu != curcpu) { 4269 printf("%s: %s%d is running", __func__, vm_name(vmx->vm), 4270 vcpu->vcpuid); 4271 return (EINVAL); 4272 } 4273 4274 if (!running) 4275 VMPTRLD(vmcs); 4276 4277 error = vmx_set_tsc_offset(vcpu, offset); 4278 4279 if (!running) 4280 VMCLEAR(vmcs); 4281 return (error); 4282 } 4283 #endif 4284 4285 const struct vmm_ops vmm_ops_intel = { 4286 .modinit = vmx_modinit, 4287 .modcleanup = vmx_modcleanup, 4288 .modsuspend = vmx_modsuspend, 4289 .modresume = vmx_modresume, 4290 .init = vmx_init, 4291 .run = vmx_run, 4292 .cleanup = vmx_cleanup, 4293 .vcpu_init = vmx_vcpu_init, 4294 .vcpu_cleanup = vmx_vcpu_cleanup, 4295 .getreg = vmx_getreg, 4296 .setreg = vmx_setreg, 4297 .getdesc = vmx_getdesc, 4298 .setdesc = vmx_setdesc, 4299 .getcap = vmx_getcap, 4300 .setcap = vmx_setcap, 4301 .vmspace_alloc = vmx_vmspace_alloc, 4302 .vmspace_free = vmx_vmspace_free, 4303 .vlapic_init = vmx_vlapic_init, 4304 .vlapic_cleanup = vmx_vlapic_cleanup, 4305 #ifdef BHYVE_SNAPSHOT 4306 .vcpu_snapshot = vmx_vcpu_snapshot, 4307 .restore_tsc = vmx_restore_tsc, 4308 #endif 4309 }; 4310