1 /*- 2 * Copyright (c) 2011 NetApp, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/smp.h> 35 #include <sys/kernel.h> 36 #include <sys/malloc.h> 37 #include <sys/pcpu.h> 38 #include <sys/proc.h> 39 #include <sys/sysctl.h> 40 41 #include <vm/vm.h> 42 #include <vm/pmap.h> 43 44 #include <machine/psl.h> 45 #include <machine/cpufunc.h> 46 #include <machine/md_var.h> 47 #include <machine/segments.h> 48 #include <machine/smp.h> 49 #include <machine/specialreg.h> 50 #include <machine/vmparam.h> 51 52 #include <machine/vmm.h> 53 #include "vmm_host.h" 54 #include "vmm_ipi.h" 55 #include "vmm_msr.h" 56 #include "vmm_ktr.h" 57 #include "vmm_stat.h" 58 #include "vlapic.h" 59 #include "vlapic_priv.h" 60 61 #include "vmx_msr.h" 62 #include "ept.h" 63 #include "vmx_cpufunc.h" 64 #include "vmx.h" 65 #include "x86.h" 66 #include "vmx_controls.h" 67 68 #define PINBASED_CTLS_ONE_SETTING \ 69 (PINBASED_EXTINT_EXITING | \ 70 PINBASED_NMI_EXITING | \ 71 PINBASED_VIRTUAL_NMI) 72 #define PINBASED_CTLS_ZERO_SETTING 0 73 74 #define PROCBASED_CTLS_WINDOW_SETTING \ 75 (PROCBASED_INT_WINDOW_EXITING | \ 76 PROCBASED_NMI_WINDOW_EXITING) 77 78 #define PROCBASED_CTLS_ONE_SETTING \ 79 (PROCBASED_SECONDARY_CONTROLS | \ 80 PROCBASED_IO_EXITING | \ 81 PROCBASED_MSR_BITMAPS | \ 82 PROCBASED_CTLS_WINDOW_SETTING) 83 #define PROCBASED_CTLS_ZERO_SETTING \ 84 (PROCBASED_CR3_LOAD_EXITING | \ 85 PROCBASED_CR3_STORE_EXITING | \ 86 PROCBASED_IO_BITMAPS) 87 88 #define PROCBASED_CTLS2_ONE_SETTING PROCBASED2_ENABLE_EPT 89 #define PROCBASED_CTLS2_ZERO_SETTING 0 90 91 #define VM_EXIT_CTLS_ONE_SETTING_NO_PAT \ 92 (VM_EXIT_HOST_LMA | \ 93 VM_EXIT_SAVE_EFER | \ 94 VM_EXIT_LOAD_EFER) 95 96 #define VM_EXIT_CTLS_ONE_SETTING \ 97 (VM_EXIT_CTLS_ONE_SETTING_NO_PAT | \ 98 VM_EXIT_ACKNOWLEDGE_INTERRUPT | \ 99 VM_EXIT_SAVE_PAT | \ 100 VM_EXIT_LOAD_PAT) 101 #define VM_EXIT_CTLS_ZERO_SETTING VM_EXIT_SAVE_DEBUG_CONTROLS 102 103 #define VM_ENTRY_CTLS_ONE_SETTING_NO_PAT VM_ENTRY_LOAD_EFER 104 105 #define VM_ENTRY_CTLS_ONE_SETTING \ 106 (VM_ENTRY_CTLS_ONE_SETTING_NO_PAT | \ 107 VM_ENTRY_LOAD_PAT) 108 #define VM_ENTRY_CTLS_ZERO_SETTING \ 109 (VM_ENTRY_LOAD_DEBUG_CONTROLS | \ 110 VM_ENTRY_INTO_SMM | \ 111 VM_ENTRY_DEACTIVATE_DUAL_MONITOR) 112 113 #define guest_msr_rw(vmx, msr) \ 114 msr_bitmap_change_access((vmx)->msr_bitmap, (msr), MSR_BITMAP_ACCESS_RW) 115 116 #define HANDLED 1 117 #define UNHANDLED 0 118 119 static MALLOC_DEFINE(M_VMX, "vmx", "vmx"); 120 static MALLOC_DEFINE(M_VLAPIC, "vlapic", "vlapic"); 121 122 SYSCTL_DECL(_hw_vmm); 123 SYSCTL_NODE(_hw_vmm, OID_AUTO, vmx, CTLFLAG_RW, NULL, NULL); 124 125 int vmxon_enabled[MAXCPU]; 126 static char vmxon_region[MAXCPU][PAGE_SIZE] __aligned(PAGE_SIZE); 127 128 static uint32_t pinbased_ctls, procbased_ctls, procbased_ctls2; 129 static uint32_t exit_ctls, entry_ctls; 130 131 static uint64_t cr0_ones_mask, cr0_zeros_mask; 132 SYSCTL_ULONG(_hw_vmm_vmx, OID_AUTO, cr0_ones_mask, CTLFLAG_RD, 133 &cr0_ones_mask, 0, NULL); 134 SYSCTL_ULONG(_hw_vmm_vmx, OID_AUTO, cr0_zeros_mask, CTLFLAG_RD, 135 &cr0_zeros_mask, 0, NULL); 136 137 static uint64_t cr4_ones_mask, cr4_zeros_mask; 138 SYSCTL_ULONG(_hw_vmm_vmx, OID_AUTO, cr4_ones_mask, CTLFLAG_RD, 139 &cr4_ones_mask, 0, NULL); 140 SYSCTL_ULONG(_hw_vmm_vmx, OID_AUTO, cr4_zeros_mask, CTLFLAG_RD, 141 &cr4_zeros_mask, 0, NULL); 142 143 static int vmx_no_patmsr; 144 145 static int vmx_initialized; 146 SYSCTL_INT(_hw_vmm_vmx, OID_AUTO, initialized, CTLFLAG_RD, 147 &vmx_initialized, 0, "Intel VMX initialized"); 148 149 /* 150 * Optional capabilities 151 */ 152 static int cap_halt_exit; 153 static int cap_pause_exit; 154 static int cap_unrestricted_guest; 155 static int cap_monitor_trap; 156 static int cap_invpcid; 157 158 static int virtual_interrupt_delivery; 159 SYSCTL_INT(_hw_vmm_vmx, OID_AUTO, virtual_interrupt_delivery, CTLFLAG_RD, 160 &virtual_interrupt_delivery, 0, "APICv virtual interrupt delivery support"); 161 162 static int posted_interrupts; 163 SYSCTL_INT(_hw_vmm_vmx, OID_AUTO, posted_interrupts, CTLFLAG_RD, 164 &posted_interrupts, 0, "APICv posted interrupt support"); 165 166 static int pirvec; 167 SYSCTL_INT(_hw_vmm_vmx, OID_AUTO, posted_interrupt_vector, CTLFLAG_RD, 168 &pirvec, 0, "APICv posted interrupt vector"); 169 170 static struct unrhdr *vpid_unr; 171 static u_int vpid_alloc_failed; 172 SYSCTL_UINT(_hw_vmm_vmx, OID_AUTO, vpid_alloc_failed, CTLFLAG_RD, 173 &vpid_alloc_failed, 0, NULL); 174 175 /* 176 * Use the last page below 4GB as the APIC access address. This address is 177 * occupied by the boot firmware so it is guaranteed that it will not conflict 178 * with a page in system memory. 179 */ 180 #define APIC_ACCESS_ADDRESS 0xFFFFF000 181 182 static void vmx_inject_pir(struct vlapic *vlapic); 183 184 #ifdef KTR 185 static const char * 186 exit_reason_to_str(int reason) 187 { 188 static char reasonbuf[32]; 189 190 switch (reason) { 191 case EXIT_REASON_EXCEPTION: 192 return "exception"; 193 case EXIT_REASON_EXT_INTR: 194 return "extint"; 195 case EXIT_REASON_TRIPLE_FAULT: 196 return "triplefault"; 197 case EXIT_REASON_INIT: 198 return "init"; 199 case EXIT_REASON_SIPI: 200 return "sipi"; 201 case EXIT_REASON_IO_SMI: 202 return "iosmi"; 203 case EXIT_REASON_SMI: 204 return "smi"; 205 case EXIT_REASON_INTR_WINDOW: 206 return "intrwindow"; 207 case EXIT_REASON_NMI_WINDOW: 208 return "nmiwindow"; 209 case EXIT_REASON_TASK_SWITCH: 210 return "taskswitch"; 211 case EXIT_REASON_CPUID: 212 return "cpuid"; 213 case EXIT_REASON_GETSEC: 214 return "getsec"; 215 case EXIT_REASON_HLT: 216 return "hlt"; 217 case EXIT_REASON_INVD: 218 return "invd"; 219 case EXIT_REASON_INVLPG: 220 return "invlpg"; 221 case EXIT_REASON_RDPMC: 222 return "rdpmc"; 223 case EXIT_REASON_RDTSC: 224 return "rdtsc"; 225 case EXIT_REASON_RSM: 226 return "rsm"; 227 case EXIT_REASON_VMCALL: 228 return "vmcall"; 229 case EXIT_REASON_VMCLEAR: 230 return "vmclear"; 231 case EXIT_REASON_VMLAUNCH: 232 return "vmlaunch"; 233 case EXIT_REASON_VMPTRLD: 234 return "vmptrld"; 235 case EXIT_REASON_VMPTRST: 236 return "vmptrst"; 237 case EXIT_REASON_VMREAD: 238 return "vmread"; 239 case EXIT_REASON_VMRESUME: 240 return "vmresume"; 241 case EXIT_REASON_VMWRITE: 242 return "vmwrite"; 243 case EXIT_REASON_VMXOFF: 244 return "vmxoff"; 245 case EXIT_REASON_VMXON: 246 return "vmxon"; 247 case EXIT_REASON_CR_ACCESS: 248 return "craccess"; 249 case EXIT_REASON_DR_ACCESS: 250 return "draccess"; 251 case EXIT_REASON_INOUT: 252 return "inout"; 253 case EXIT_REASON_RDMSR: 254 return "rdmsr"; 255 case EXIT_REASON_WRMSR: 256 return "wrmsr"; 257 case EXIT_REASON_INVAL_VMCS: 258 return "invalvmcs"; 259 case EXIT_REASON_INVAL_MSR: 260 return "invalmsr"; 261 case EXIT_REASON_MWAIT: 262 return "mwait"; 263 case EXIT_REASON_MTF: 264 return "mtf"; 265 case EXIT_REASON_MONITOR: 266 return "monitor"; 267 case EXIT_REASON_PAUSE: 268 return "pause"; 269 case EXIT_REASON_MCE: 270 return "mce"; 271 case EXIT_REASON_TPR: 272 return "tpr"; 273 case EXIT_REASON_APIC_ACCESS: 274 return "apic-access"; 275 case EXIT_REASON_GDTR_IDTR: 276 return "gdtridtr"; 277 case EXIT_REASON_LDTR_TR: 278 return "ldtrtr"; 279 case EXIT_REASON_EPT_FAULT: 280 return "eptfault"; 281 case EXIT_REASON_EPT_MISCONFIG: 282 return "eptmisconfig"; 283 case EXIT_REASON_INVEPT: 284 return "invept"; 285 case EXIT_REASON_RDTSCP: 286 return "rdtscp"; 287 case EXIT_REASON_VMX_PREEMPT: 288 return "vmxpreempt"; 289 case EXIT_REASON_INVVPID: 290 return "invvpid"; 291 case EXIT_REASON_WBINVD: 292 return "wbinvd"; 293 case EXIT_REASON_XSETBV: 294 return "xsetbv"; 295 case EXIT_REASON_APIC_WRITE: 296 return "apic-write"; 297 default: 298 snprintf(reasonbuf, sizeof(reasonbuf), "%d", reason); 299 return (reasonbuf); 300 } 301 } 302 #endif /* KTR */ 303 304 u_long 305 vmx_fix_cr0(u_long cr0) 306 { 307 308 return ((cr0 | cr0_ones_mask) & ~cr0_zeros_mask); 309 } 310 311 u_long 312 vmx_fix_cr4(u_long cr4) 313 { 314 315 return ((cr4 | cr4_ones_mask) & ~cr4_zeros_mask); 316 } 317 318 static void 319 vpid_free(int vpid) 320 { 321 if (vpid < 0 || vpid > 0xffff) 322 panic("vpid_free: invalid vpid %d", vpid); 323 324 /* 325 * VPIDs [0,VM_MAXCPU] are special and are not allocated from 326 * the unit number allocator. 327 */ 328 329 if (vpid > VM_MAXCPU) 330 free_unr(vpid_unr, vpid); 331 } 332 333 static void 334 vpid_alloc(uint16_t *vpid, int num) 335 { 336 int i, x; 337 338 if (num <= 0 || num > VM_MAXCPU) 339 panic("invalid number of vpids requested: %d", num); 340 341 /* 342 * If the "enable vpid" execution control is not enabled then the 343 * VPID is required to be 0 for all vcpus. 344 */ 345 if ((procbased_ctls2 & PROCBASED2_ENABLE_VPID) == 0) { 346 for (i = 0; i < num; i++) 347 vpid[i] = 0; 348 return; 349 } 350 351 /* 352 * Allocate a unique VPID for each vcpu from the unit number allocator. 353 */ 354 for (i = 0; i < num; i++) { 355 x = alloc_unr(vpid_unr); 356 if (x == -1) 357 break; 358 else 359 vpid[i] = x; 360 } 361 362 if (i < num) { 363 atomic_add_int(&vpid_alloc_failed, 1); 364 365 /* 366 * If the unit number allocator does not have enough unique 367 * VPIDs then we need to allocate from the [1,VM_MAXCPU] range. 368 * 369 * These VPIDs are not be unique across VMs but this does not 370 * affect correctness because the combined mappings are also 371 * tagged with the EP4TA which is unique for each VM. 372 * 373 * It is still sub-optimal because the invvpid will invalidate 374 * combined mappings for a particular VPID across all EP4TAs. 375 */ 376 while (i-- > 0) 377 vpid_free(vpid[i]); 378 379 for (i = 0; i < num; i++) 380 vpid[i] = i + 1; 381 } 382 } 383 384 static void 385 vpid_init(void) 386 { 387 /* 388 * VPID 0 is required when the "enable VPID" execution control is 389 * disabled. 390 * 391 * VPIDs [1,VM_MAXCPU] are used as the "overflow namespace" when the 392 * unit number allocator does not have sufficient unique VPIDs to 393 * satisfy the allocation. 394 * 395 * The remaining VPIDs are managed by the unit number allocator. 396 */ 397 vpid_unr = new_unrhdr(VM_MAXCPU + 1, 0xffff, NULL); 398 } 399 400 static void 401 msr_save_area_init(struct msr_entry *g_area, int *g_count) 402 { 403 int cnt; 404 405 static struct msr_entry guest_msrs[] = { 406 { MSR_KGSBASE, 0, 0 }, 407 }; 408 409 cnt = sizeof(guest_msrs) / sizeof(guest_msrs[0]); 410 if (cnt > GUEST_MSR_MAX_ENTRIES) 411 panic("guest msr save area overrun"); 412 bcopy(guest_msrs, g_area, sizeof(guest_msrs)); 413 *g_count = cnt; 414 } 415 416 static void 417 vmx_disable(void *arg __unused) 418 { 419 struct invvpid_desc invvpid_desc = { 0 }; 420 struct invept_desc invept_desc = { 0 }; 421 422 if (vmxon_enabled[curcpu]) { 423 /* 424 * See sections 25.3.3.3 and 25.3.3.4 in Intel Vol 3b. 425 * 426 * VMXON or VMXOFF are not required to invalidate any TLB 427 * caching structures. This prevents potential retention of 428 * cached information in the TLB between distinct VMX episodes. 429 */ 430 invvpid(INVVPID_TYPE_ALL_CONTEXTS, invvpid_desc); 431 invept(INVEPT_TYPE_ALL_CONTEXTS, invept_desc); 432 vmxoff(); 433 } 434 load_cr4(rcr4() & ~CR4_VMXE); 435 } 436 437 static int 438 vmx_cleanup(void) 439 { 440 441 if (pirvec != 0) 442 vmm_ipi_free(pirvec); 443 444 if (vpid_unr != NULL) { 445 delete_unrhdr(vpid_unr); 446 vpid_unr = NULL; 447 } 448 449 smp_rendezvous(NULL, vmx_disable, NULL, NULL); 450 451 return (0); 452 } 453 454 static void 455 vmx_enable(void *arg __unused) 456 { 457 int error; 458 459 load_cr4(rcr4() | CR4_VMXE); 460 461 *(uint32_t *)vmxon_region[curcpu] = vmx_revision(); 462 error = vmxon(vmxon_region[curcpu]); 463 if (error == 0) 464 vmxon_enabled[curcpu] = 1; 465 } 466 467 static void 468 vmx_restore(void) 469 { 470 471 if (vmxon_enabled[curcpu]) 472 vmxon(vmxon_region[curcpu]); 473 } 474 475 static int 476 vmx_init(int ipinum) 477 { 478 int error, use_tpr_shadow; 479 uint64_t fixed0, fixed1, feature_control; 480 uint32_t tmp, procbased2_vid_bits; 481 482 /* CPUID.1:ECX[bit 5] must be 1 for processor to support VMX */ 483 if (!(cpu_feature2 & CPUID2_VMX)) { 484 printf("vmx_init: processor does not support VMX operation\n"); 485 return (ENXIO); 486 } 487 488 /* 489 * Verify that MSR_IA32_FEATURE_CONTROL lock and VMXON enable bits 490 * are set (bits 0 and 2 respectively). 491 */ 492 feature_control = rdmsr(MSR_IA32_FEATURE_CONTROL); 493 if ((feature_control & IA32_FEATURE_CONTROL_LOCK) == 0 || 494 (feature_control & IA32_FEATURE_CONTROL_VMX_EN) == 0) { 495 printf("vmx_init: VMX operation disabled by BIOS\n"); 496 return (ENXIO); 497 } 498 499 /* Check support for primary processor-based VM-execution controls */ 500 error = vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS, 501 MSR_VMX_TRUE_PROCBASED_CTLS, 502 PROCBASED_CTLS_ONE_SETTING, 503 PROCBASED_CTLS_ZERO_SETTING, &procbased_ctls); 504 if (error) { 505 printf("vmx_init: processor does not support desired primary " 506 "processor-based controls\n"); 507 return (error); 508 } 509 510 /* Clear the processor-based ctl bits that are set on demand */ 511 procbased_ctls &= ~PROCBASED_CTLS_WINDOW_SETTING; 512 513 /* Check support for secondary processor-based VM-execution controls */ 514 error = vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS2, 515 MSR_VMX_PROCBASED_CTLS2, 516 PROCBASED_CTLS2_ONE_SETTING, 517 PROCBASED_CTLS2_ZERO_SETTING, &procbased_ctls2); 518 if (error) { 519 printf("vmx_init: processor does not support desired secondary " 520 "processor-based controls\n"); 521 return (error); 522 } 523 524 /* Check support for VPID */ 525 error = vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS2, MSR_VMX_PROCBASED_CTLS2, 526 PROCBASED2_ENABLE_VPID, 0, &tmp); 527 if (error == 0) 528 procbased_ctls2 |= PROCBASED2_ENABLE_VPID; 529 530 /* Check support for pin-based VM-execution controls */ 531 error = vmx_set_ctlreg(MSR_VMX_PINBASED_CTLS, 532 MSR_VMX_TRUE_PINBASED_CTLS, 533 PINBASED_CTLS_ONE_SETTING, 534 PINBASED_CTLS_ZERO_SETTING, &pinbased_ctls); 535 if (error) { 536 printf("vmx_init: processor does not support desired " 537 "pin-based controls\n"); 538 return (error); 539 } 540 541 /* Check support for VM-exit controls */ 542 error = vmx_set_ctlreg(MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS, 543 VM_EXIT_CTLS_ONE_SETTING, 544 VM_EXIT_CTLS_ZERO_SETTING, 545 &exit_ctls); 546 if (error) { 547 /* Try again without the PAT MSR bits */ 548 error = vmx_set_ctlreg(MSR_VMX_EXIT_CTLS, 549 MSR_VMX_TRUE_EXIT_CTLS, 550 VM_EXIT_CTLS_ONE_SETTING_NO_PAT, 551 VM_EXIT_CTLS_ZERO_SETTING, 552 &exit_ctls); 553 if (error) { 554 printf("vmx_init: processor does not support desired " 555 "exit controls\n"); 556 return (error); 557 } else { 558 if (bootverbose) 559 printf("vmm: PAT MSR access not supported\n"); 560 guest_msr_valid(MSR_PAT); 561 vmx_no_patmsr = 1; 562 } 563 } 564 565 /* Check support for VM-entry controls */ 566 if (!vmx_no_patmsr) { 567 error = vmx_set_ctlreg(MSR_VMX_ENTRY_CTLS, 568 MSR_VMX_TRUE_ENTRY_CTLS, 569 VM_ENTRY_CTLS_ONE_SETTING, 570 VM_ENTRY_CTLS_ZERO_SETTING, 571 &entry_ctls); 572 } else { 573 error = vmx_set_ctlreg(MSR_VMX_ENTRY_CTLS, 574 MSR_VMX_TRUE_ENTRY_CTLS, 575 VM_ENTRY_CTLS_ONE_SETTING_NO_PAT, 576 VM_ENTRY_CTLS_ZERO_SETTING, 577 &entry_ctls); 578 } 579 580 if (error) { 581 printf("vmx_init: processor does not support desired " 582 "entry controls\n"); 583 return (error); 584 } 585 586 /* 587 * Check support for optional features by testing them 588 * as individual bits 589 */ 590 cap_halt_exit = (vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS, 591 MSR_VMX_TRUE_PROCBASED_CTLS, 592 PROCBASED_HLT_EXITING, 0, 593 &tmp) == 0); 594 595 cap_monitor_trap = (vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS, 596 MSR_VMX_PROCBASED_CTLS, 597 PROCBASED_MTF, 0, 598 &tmp) == 0); 599 600 cap_pause_exit = (vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS, 601 MSR_VMX_TRUE_PROCBASED_CTLS, 602 PROCBASED_PAUSE_EXITING, 0, 603 &tmp) == 0); 604 605 cap_unrestricted_guest = (vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS2, 606 MSR_VMX_PROCBASED_CTLS2, 607 PROCBASED2_UNRESTRICTED_GUEST, 0, 608 &tmp) == 0); 609 610 cap_invpcid = (vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS2, 611 MSR_VMX_PROCBASED_CTLS2, PROCBASED2_ENABLE_INVPCID, 0, 612 &tmp) == 0); 613 614 /* 615 * Check support for virtual interrupt delivery. 616 */ 617 procbased2_vid_bits = (PROCBASED2_VIRTUALIZE_APIC_ACCESSES | 618 PROCBASED2_VIRTUALIZE_X2APIC_MODE | 619 PROCBASED2_APIC_REGISTER_VIRTUALIZATION | 620 PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY); 621 622 use_tpr_shadow = (vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS, 623 MSR_VMX_TRUE_PROCBASED_CTLS, PROCBASED_USE_TPR_SHADOW, 0, 624 &tmp) == 0); 625 626 error = vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS2, MSR_VMX_PROCBASED_CTLS2, 627 procbased2_vid_bits, 0, &tmp); 628 if (error == 0 && use_tpr_shadow) { 629 virtual_interrupt_delivery = 1; 630 TUNABLE_INT_FETCH("hw.vmm.vmx.use_apic_vid", 631 &virtual_interrupt_delivery); 632 } 633 634 if (virtual_interrupt_delivery) { 635 procbased_ctls |= PROCBASED_USE_TPR_SHADOW; 636 procbased_ctls2 |= procbased2_vid_bits; 637 procbased_ctls2 &= ~PROCBASED2_VIRTUALIZE_X2APIC_MODE; 638 639 /* 640 * Check for Posted Interrupts only if Virtual Interrupt 641 * Delivery is enabled. 642 */ 643 error = vmx_set_ctlreg(MSR_VMX_PINBASED_CTLS, 644 MSR_VMX_TRUE_PINBASED_CTLS, PINBASED_POSTED_INTERRUPT, 0, 645 &tmp); 646 if (error == 0) { 647 pirvec = vmm_ipi_alloc(); 648 if (pirvec == 0) { 649 if (bootverbose) { 650 printf("vmx_init: unable to allocate " 651 "posted interrupt vector\n"); 652 } 653 } else { 654 posted_interrupts = 1; 655 TUNABLE_INT_FETCH("hw.vmm.vmx.use_apic_pir", 656 &posted_interrupts); 657 } 658 } 659 } 660 661 if (posted_interrupts) 662 pinbased_ctls |= PINBASED_POSTED_INTERRUPT; 663 664 /* Initialize EPT */ 665 error = ept_init(ipinum); 666 if (error) { 667 printf("vmx_init: ept initialization failed (%d)\n", error); 668 return (error); 669 } 670 671 /* 672 * Stash the cr0 and cr4 bits that must be fixed to 0 or 1 673 */ 674 fixed0 = rdmsr(MSR_VMX_CR0_FIXED0); 675 fixed1 = rdmsr(MSR_VMX_CR0_FIXED1); 676 cr0_ones_mask = fixed0 & fixed1; 677 cr0_zeros_mask = ~fixed0 & ~fixed1; 678 679 /* 680 * CR0_PE and CR0_PG can be set to zero in VMX non-root operation 681 * if unrestricted guest execution is allowed. 682 */ 683 if (cap_unrestricted_guest) 684 cr0_ones_mask &= ~(CR0_PG | CR0_PE); 685 686 /* 687 * Do not allow the guest to set CR0_NW or CR0_CD. 688 */ 689 cr0_zeros_mask |= (CR0_NW | CR0_CD); 690 691 fixed0 = rdmsr(MSR_VMX_CR4_FIXED0); 692 fixed1 = rdmsr(MSR_VMX_CR4_FIXED1); 693 cr4_ones_mask = fixed0 & fixed1; 694 cr4_zeros_mask = ~fixed0 & ~fixed1; 695 696 vpid_init(); 697 698 /* enable VMX operation */ 699 smp_rendezvous(NULL, vmx_enable, NULL, NULL); 700 701 vmx_initialized = 1; 702 703 return (0); 704 } 705 706 static void 707 vmx_trigger_hostintr(int vector) 708 { 709 uintptr_t func; 710 struct gate_descriptor *gd; 711 712 gd = &idt[vector]; 713 714 KASSERT(vector >= 32 && vector <= 255, ("vmx_trigger_hostintr: " 715 "invalid vector %d", vector)); 716 KASSERT(gd->gd_p == 1, ("gate descriptor for vector %d not present", 717 vector)); 718 KASSERT(gd->gd_type == SDT_SYSIGT, ("gate descriptor for vector %d " 719 "has invalid type %d", vector, gd->gd_type)); 720 KASSERT(gd->gd_dpl == SEL_KPL, ("gate descriptor for vector %d " 721 "has invalid dpl %d", vector, gd->gd_dpl)); 722 KASSERT(gd->gd_selector == GSEL(GCODE_SEL, SEL_KPL), ("gate descriptor " 723 "for vector %d has invalid selector %d", vector, gd->gd_selector)); 724 KASSERT(gd->gd_ist == 0, ("gate descriptor for vector %d has invalid " 725 "IST %d", vector, gd->gd_ist)); 726 727 func = ((long)gd->gd_hioffset << 16 | gd->gd_looffset); 728 vmx_call_isr(func); 729 } 730 731 static int 732 vmx_setup_cr_shadow(int which, struct vmcs *vmcs, uint32_t initial) 733 { 734 int error, mask_ident, shadow_ident; 735 uint64_t mask_value; 736 737 if (which != 0 && which != 4) 738 panic("vmx_setup_cr_shadow: unknown cr%d", which); 739 740 if (which == 0) { 741 mask_ident = VMCS_CR0_MASK; 742 mask_value = cr0_ones_mask | cr0_zeros_mask; 743 shadow_ident = VMCS_CR0_SHADOW; 744 } else { 745 mask_ident = VMCS_CR4_MASK; 746 mask_value = cr4_ones_mask | cr4_zeros_mask; 747 shadow_ident = VMCS_CR4_SHADOW; 748 } 749 750 error = vmcs_setreg(vmcs, 0, VMCS_IDENT(mask_ident), mask_value); 751 if (error) 752 return (error); 753 754 error = vmcs_setreg(vmcs, 0, VMCS_IDENT(shadow_ident), initial); 755 if (error) 756 return (error); 757 758 return (0); 759 } 760 #define vmx_setup_cr0_shadow(vmcs,init) vmx_setup_cr_shadow(0, (vmcs), (init)) 761 #define vmx_setup_cr4_shadow(vmcs,init) vmx_setup_cr_shadow(4, (vmcs), (init)) 762 763 static void * 764 vmx_vminit(struct vm *vm, pmap_t pmap) 765 { 766 uint16_t vpid[VM_MAXCPU]; 767 int i, error, guest_msr_count; 768 struct vmx *vmx; 769 struct vmcs *vmcs; 770 771 vmx = malloc(sizeof(struct vmx), M_VMX, M_WAITOK | M_ZERO); 772 if ((uintptr_t)vmx & PAGE_MASK) { 773 panic("malloc of struct vmx not aligned on %d byte boundary", 774 PAGE_SIZE); 775 } 776 vmx->vm = vm; 777 778 vmx->eptp = eptp(vtophys((vm_offset_t)pmap->pm_pml4)); 779 780 /* 781 * Clean up EPTP-tagged guest physical and combined mappings 782 * 783 * VMX transitions are not required to invalidate any guest physical 784 * mappings. So, it may be possible for stale guest physical mappings 785 * to be present in the processor TLBs. 786 * 787 * Combined mappings for this EP4TA are also invalidated for all VPIDs. 788 */ 789 ept_invalidate_mappings(vmx->eptp); 790 791 msr_bitmap_initialize(vmx->msr_bitmap); 792 793 /* 794 * It is safe to allow direct access to MSR_GSBASE and MSR_FSBASE. 795 * The guest FSBASE and GSBASE are saved and restored during 796 * vm-exit and vm-entry respectively. The host FSBASE and GSBASE are 797 * always restored from the vmcs host state area on vm-exit. 798 * 799 * The SYSENTER_CS/ESP/EIP MSRs are identical to FS/GSBASE in 800 * how they are saved/restored so can be directly accessed by the 801 * guest. 802 * 803 * Guest KGSBASE is saved and restored in the guest MSR save area. 804 * Host KGSBASE is restored before returning to userland from the pcb. 805 * There will be a window of time when we are executing in the host 806 * kernel context with a value of KGSBASE from the guest. This is ok 807 * because the value of KGSBASE is inconsequential in kernel context. 808 * 809 * MSR_EFER is saved and restored in the guest VMCS area on a 810 * VM exit and entry respectively. It is also restored from the 811 * host VMCS area on a VM exit. 812 */ 813 if (guest_msr_rw(vmx, MSR_GSBASE) || 814 guest_msr_rw(vmx, MSR_FSBASE) || 815 guest_msr_rw(vmx, MSR_SYSENTER_CS_MSR) || 816 guest_msr_rw(vmx, MSR_SYSENTER_ESP_MSR) || 817 guest_msr_rw(vmx, MSR_SYSENTER_EIP_MSR) || 818 guest_msr_rw(vmx, MSR_KGSBASE) || 819 guest_msr_rw(vmx, MSR_EFER)) 820 panic("vmx_vminit: error setting guest msr access"); 821 822 /* 823 * MSR_PAT is saved and restored in the guest VMCS are on a VM exit 824 * and entry respectively. It is also restored from the host VMCS 825 * area on a VM exit. However, if running on a system with no 826 * MSR_PAT save/restore support, leave access disabled so accesses 827 * will be trapped. 828 */ 829 if (!vmx_no_patmsr && guest_msr_rw(vmx, MSR_PAT)) 830 panic("vmx_vminit: error setting guest pat msr access"); 831 832 vpid_alloc(vpid, VM_MAXCPU); 833 834 if (virtual_interrupt_delivery) { 835 error = vm_map_mmio(vm, DEFAULT_APIC_BASE, PAGE_SIZE, 836 APIC_ACCESS_ADDRESS); 837 /* XXX this should really return an error to the caller */ 838 KASSERT(error == 0, ("vm_map_mmio(apicbase) error %d", error)); 839 } 840 841 for (i = 0; i < VM_MAXCPU; i++) { 842 vmcs = &vmx->vmcs[i]; 843 vmcs->identifier = vmx_revision(); 844 error = vmclear(vmcs); 845 if (error != 0) { 846 panic("vmx_vminit: vmclear error %d on vcpu %d\n", 847 error, i); 848 } 849 850 error = vmcs_init(vmcs); 851 KASSERT(error == 0, ("vmcs_init error %d", error)); 852 853 VMPTRLD(vmcs); 854 error = 0; 855 error += vmwrite(VMCS_HOST_RSP, (u_long)&vmx->ctx[i]); 856 error += vmwrite(VMCS_EPTP, vmx->eptp); 857 error += vmwrite(VMCS_PIN_BASED_CTLS, pinbased_ctls); 858 error += vmwrite(VMCS_PRI_PROC_BASED_CTLS, procbased_ctls); 859 error += vmwrite(VMCS_SEC_PROC_BASED_CTLS, procbased_ctls2); 860 error += vmwrite(VMCS_EXIT_CTLS, exit_ctls); 861 error += vmwrite(VMCS_ENTRY_CTLS, entry_ctls); 862 error += vmwrite(VMCS_MSR_BITMAP, vtophys(vmx->msr_bitmap)); 863 error += vmwrite(VMCS_VPID, vpid[i]); 864 if (virtual_interrupt_delivery) { 865 error += vmwrite(VMCS_APIC_ACCESS, APIC_ACCESS_ADDRESS); 866 error += vmwrite(VMCS_VIRTUAL_APIC, 867 vtophys(&vmx->apic_page[i])); 868 error += vmwrite(VMCS_EOI_EXIT0, 0); 869 error += vmwrite(VMCS_EOI_EXIT1, 0); 870 error += vmwrite(VMCS_EOI_EXIT2, 0); 871 error += vmwrite(VMCS_EOI_EXIT3, 0); 872 } 873 if (posted_interrupts) { 874 error += vmwrite(VMCS_PIR_VECTOR, pirvec); 875 error += vmwrite(VMCS_PIR_DESC, 876 vtophys(&vmx->pir_desc[i])); 877 } 878 VMCLEAR(vmcs); 879 KASSERT(error == 0, ("vmx_vminit: error customizing the vmcs")); 880 881 vmx->cap[i].set = 0; 882 vmx->cap[i].proc_ctls = procbased_ctls; 883 vmx->cap[i].proc_ctls2 = procbased_ctls2; 884 885 vmx->state[i].lastcpu = -1; 886 vmx->state[i].vpid = vpid[i]; 887 888 msr_save_area_init(vmx->guest_msrs[i], &guest_msr_count); 889 890 error = vmcs_set_msr_save(vmcs, vtophys(vmx->guest_msrs[i]), 891 guest_msr_count); 892 if (error != 0) 893 panic("vmcs_set_msr_save error %d", error); 894 895 /* 896 * Set up the CR0/4 shadows, and init the read shadow 897 * to the power-on register value from the Intel Sys Arch. 898 * CR0 - 0x60000010 899 * CR4 - 0 900 */ 901 error = vmx_setup_cr0_shadow(vmcs, 0x60000010); 902 if (error != 0) 903 panic("vmx_setup_cr0_shadow %d", error); 904 905 error = vmx_setup_cr4_shadow(vmcs, 0); 906 if (error != 0) 907 panic("vmx_setup_cr4_shadow %d", error); 908 909 vmx->ctx[i].pmap = pmap; 910 vmx->ctx[i].eptp = vmx->eptp; 911 } 912 913 return (vmx); 914 } 915 916 static int 917 vmx_handle_cpuid(struct vm *vm, int vcpu, struct vmxctx *vmxctx) 918 { 919 int handled, func; 920 921 func = vmxctx->guest_rax; 922 923 handled = x86_emulate_cpuid(vm, vcpu, 924 (uint32_t*)(&vmxctx->guest_rax), 925 (uint32_t*)(&vmxctx->guest_rbx), 926 (uint32_t*)(&vmxctx->guest_rcx), 927 (uint32_t*)(&vmxctx->guest_rdx)); 928 return (handled); 929 } 930 931 static __inline void 932 vmx_run_trace(struct vmx *vmx, int vcpu) 933 { 934 #ifdef KTR 935 VCPU_CTR1(vmx->vm, vcpu, "Resume execution at %#lx", vmcs_guest_rip()); 936 #endif 937 } 938 939 static __inline void 940 vmx_exit_trace(struct vmx *vmx, int vcpu, uint64_t rip, uint32_t exit_reason, 941 int handled) 942 { 943 #ifdef KTR 944 VCPU_CTR3(vmx->vm, vcpu, "%s %s vmexit at 0x%0lx", 945 handled ? "handled" : "unhandled", 946 exit_reason_to_str(exit_reason), rip); 947 #endif 948 } 949 950 static __inline void 951 vmx_astpending_trace(struct vmx *vmx, int vcpu, uint64_t rip) 952 { 953 #ifdef KTR 954 VCPU_CTR1(vmx->vm, vcpu, "astpending vmexit at 0x%0lx", rip); 955 #endif 956 } 957 958 static void 959 vmx_set_pcpu_defaults(struct vmx *vmx, int vcpu) 960 { 961 int lastcpu; 962 struct vmxstate *vmxstate; 963 struct invvpid_desc invvpid_desc = { 0 }; 964 965 vmxstate = &vmx->state[vcpu]; 966 lastcpu = vmxstate->lastcpu; 967 vmxstate->lastcpu = curcpu; 968 969 if (lastcpu == curcpu) 970 return; 971 972 vmm_stat_incr(vmx->vm, vcpu, VCPU_MIGRATIONS, 1); 973 974 vmcs_write(VMCS_HOST_TR_BASE, vmm_get_host_trbase()); 975 vmcs_write(VMCS_HOST_GDTR_BASE, vmm_get_host_gdtrbase()); 976 vmcs_write(VMCS_HOST_GS_BASE, vmm_get_host_gsbase()); 977 978 /* 979 * If we are using VPIDs then invalidate all mappings tagged with 'vpid' 980 * 981 * We do this because this vcpu was executing on a different host 982 * cpu when it last ran. We do not track whether it invalidated 983 * mappings associated with its 'vpid' during that run. So we must 984 * assume that the mappings associated with 'vpid' on 'curcpu' are 985 * stale and invalidate them. 986 * 987 * Note that we incur this penalty only when the scheduler chooses to 988 * move the thread associated with this vcpu between host cpus. 989 * 990 * Note also that this will invalidate mappings tagged with 'vpid' 991 * for "all" EP4TAs. 992 */ 993 if (vmxstate->vpid != 0) { 994 invvpid_desc.vpid = vmxstate->vpid; 995 invvpid(INVVPID_TYPE_SINGLE_CONTEXT, invvpid_desc); 996 } 997 } 998 999 /* 1000 * We depend on 'procbased_ctls' to have the Interrupt Window Exiting bit set. 1001 */ 1002 CTASSERT((PROCBASED_CTLS_ONE_SETTING & PROCBASED_INT_WINDOW_EXITING) != 0); 1003 1004 static void __inline 1005 vmx_set_int_window_exiting(struct vmx *vmx, int vcpu) 1006 { 1007 1008 if ((vmx->cap[vcpu].proc_ctls & PROCBASED_INT_WINDOW_EXITING) == 0) { 1009 vmx->cap[vcpu].proc_ctls |= PROCBASED_INT_WINDOW_EXITING; 1010 vmcs_write(VMCS_PRI_PROC_BASED_CTLS, vmx->cap[vcpu].proc_ctls); 1011 VCPU_CTR0(vmx->vm, vcpu, "Enabling interrupt window exiting"); 1012 } 1013 } 1014 1015 static void __inline 1016 vmx_clear_int_window_exiting(struct vmx *vmx, int vcpu) 1017 { 1018 1019 KASSERT((vmx->cap[vcpu].proc_ctls & PROCBASED_INT_WINDOW_EXITING) != 0, 1020 ("intr_window_exiting not set: %#x", vmx->cap[vcpu].proc_ctls)); 1021 vmx->cap[vcpu].proc_ctls &= ~PROCBASED_INT_WINDOW_EXITING; 1022 vmcs_write(VMCS_PRI_PROC_BASED_CTLS, vmx->cap[vcpu].proc_ctls); 1023 VCPU_CTR0(vmx->vm, vcpu, "Disabling interrupt window exiting"); 1024 } 1025 1026 static void __inline 1027 vmx_set_nmi_window_exiting(struct vmx *vmx, int vcpu) 1028 { 1029 1030 if ((vmx->cap[vcpu].proc_ctls & PROCBASED_NMI_WINDOW_EXITING) == 0) { 1031 vmx->cap[vcpu].proc_ctls |= PROCBASED_NMI_WINDOW_EXITING; 1032 vmcs_write(VMCS_PRI_PROC_BASED_CTLS, vmx->cap[vcpu].proc_ctls); 1033 VCPU_CTR0(vmx->vm, vcpu, "Enabling NMI window exiting"); 1034 } 1035 } 1036 1037 static void __inline 1038 vmx_clear_nmi_window_exiting(struct vmx *vmx, int vcpu) 1039 { 1040 1041 KASSERT((vmx->cap[vcpu].proc_ctls & PROCBASED_NMI_WINDOW_EXITING) != 0, 1042 ("nmi_window_exiting not set %#x", vmx->cap[vcpu].proc_ctls)); 1043 vmx->cap[vcpu].proc_ctls &= ~PROCBASED_NMI_WINDOW_EXITING; 1044 vmcs_write(VMCS_PRI_PROC_BASED_CTLS, vmx->cap[vcpu].proc_ctls); 1045 VCPU_CTR0(vmx->vm, vcpu, "Disabling NMI window exiting"); 1046 } 1047 1048 #define NMI_BLOCKING (VMCS_INTERRUPTIBILITY_NMI_BLOCKING | \ 1049 VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING) 1050 #define HWINTR_BLOCKING (VMCS_INTERRUPTIBILITY_STI_BLOCKING | \ 1051 VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING) 1052 1053 static void 1054 vmx_inject_nmi(struct vmx *vmx, int vcpu) 1055 { 1056 uint32_t gi, info; 1057 1058 gi = vmcs_read(VMCS_GUEST_INTERRUPTIBILITY); 1059 KASSERT((gi & NMI_BLOCKING) == 0, ("vmx_inject_nmi: invalid guest " 1060 "interruptibility-state %#x", gi)); 1061 1062 info = vmcs_read(VMCS_ENTRY_INTR_INFO); 1063 KASSERT((info & VMCS_INTR_VALID) == 0, ("vmx_inject_nmi: invalid " 1064 "VM-entry interruption information %#x", info)); 1065 1066 /* 1067 * Inject the virtual NMI. The vector must be the NMI IDT entry 1068 * or the VMCS entry check will fail. 1069 */ 1070 info = IDT_NMI | VMCS_INTR_T_NMI | VMCS_INTR_VALID; 1071 vmcs_write(VMCS_ENTRY_INTR_INFO, info); 1072 1073 VCPU_CTR0(vmx->vm, vcpu, "Injecting vNMI"); 1074 1075 /* Clear the request */ 1076 vm_nmi_clear(vmx->vm, vcpu); 1077 } 1078 1079 static void 1080 vmx_inject_interrupts(struct vmx *vmx, int vcpu, struct vlapic *vlapic) 1081 { 1082 int vector, need_nmi_exiting; 1083 uint64_t rflags; 1084 uint32_t gi, info; 1085 1086 if (vm_nmi_pending(vmx->vm, vcpu)) { 1087 /* 1088 * If there are no conditions blocking NMI injection then 1089 * inject it directly here otherwise enable "NMI window 1090 * exiting" to inject it as soon as we can. 1091 * 1092 * We also check for STI_BLOCKING because some implementations 1093 * don't allow NMI injection in this case. If we are running 1094 * on a processor that doesn't have this restriction it will 1095 * immediately exit and the NMI will be injected in the 1096 * "NMI window exiting" handler. 1097 */ 1098 need_nmi_exiting = 1; 1099 gi = vmcs_read(VMCS_GUEST_INTERRUPTIBILITY); 1100 if ((gi & (HWINTR_BLOCKING | NMI_BLOCKING)) == 0) { 1101 info = vmcs_read(VMCS_ENTRY_INTR_INFO); 1102 if ((info & VMCS_INTR_VALID) == 0) { 1103 vmx_inject_nmi(vmx, vcpu); 1104 need_nmi_exiting = 0; 1105 } else { 1106 VCPU_CTR1(vmx->vm, vcpu, "Cannot inject NMI " 1107 "due to VM-entry intr info %#x", info); 1108 } 1109 } else { 1110 VCPU_CTR1(vmx->vm, vcpu, "Cannot inject NMI due to " 1111 "Guest Interruptibility-state %#x", gi); 1112 } 1113 1114 if (need_nmi_exiting) 1115 vmx_set_nmi_window_exiting(vmx, vcpu); 1116 } 1117 1118 if (virtual_interrupt_delivery) { 1119 vmx_inject_pir(vlapic); 1120 return; 1121 } 1122 1123 /* 1124 * If interrupt-window exiting is already in effect then don't bother 1125 * checking for pending interrupts. This is just an optimization and 1126 * not needed for correctness. 1127 */ 1128 if ((vmx->cap[vcpu].proc_ctls & PROCBASED_INT_WINDOW_EXITING) != 0) { 1129 VCPU_CTR0(vmx->vm, vcpu, "Skip interrupt injection due to " 1130 "pending int_window_exiting"); 1131 return; 1132 } 1133 1134 /* Ask the local apic for a vector to inject */ 1135 if (!vlapic_pending_intr(vlapic, &vector)) 1136 return; 1137 1138 KASSERT(vector >= 32 && vector <= 255, ("invalid vector %d", vector)); 1139 1140 /* Check RFLAGS.IF and the interruptibility state of the guest */ 1141 rflags = vmcs_read(VMCS_GUEST_RFLAGS); 1142 if ((rflags & PSL_I) == 0) { 1143 VCPU_CTR2(vmx->vm, vcpu, "Cannot inject vector %d due to " 1144 "rflags %#lx", vector, rflags); 1145 goto cantinject; 1146 } 1147 1148 gi = vmcs_read(VMCS_GUEST_INTERRUPTIBILITY); 1149 if (gi & HWINTR_BLOCKING) { 1150 VCPU_CTR2(vmx->vm, vcpu, "Cannot inject vector %d due to " 1151 "Guest Interruptibility-state %#x", vector, gi); 1152 goto cantinject; 1153 } 1154 1155 info = vmcs_read(VMCS_ENTRY_INTR_INFO); 1156 if (info & VMCS_INTR_VALID) { 1157 /* 1158 * This is expected and could happen for multiple reasons: 1159 * - A vectoring VM-entry was aborted due to astpending 1160 * - A VM-exit happened during event injection. 1161 * - An NMI was injected above or after "NMI window exiting" 1162 */ 1163 VCPU_CTR2(vmx->vm, vcpu, "Cannot inject vector %d due to " 1164 "VM-entry intr info %#x", vector, info); 1165 goto cantinject; 1166 } 1167 1168 /* Inject the interrupt */ 1169 info = VMCS_INTR_T_HWINTR | VMCS_INTR_VALID; 1170 info |= vector; 1171 vmcs_write(VMCS_ENTRY_INTR_INFO, info); 1172 1173 /* Update the Local APIC ISR */ 1174 vlapic_intr_accepted(vlapic, vector); 1175 1176 VCPU_CTR1(vmx->vm, vcpu, "Injecting hwintr at vector %d", vector); 1177 1178 return; 1179 1180 cantinject: 1181 /* 1182 * Set the Interrupt Window Exiting execution control so we can inject 1183 * the interrupt as soon as blocking condition goes away. 1184 */ 1185 vmx_set_int_window_exiting(vmx, vcpu); 1186 } 1187 1188 /* 1189 * If the Virtual NMIs execution control is '1' then the logical processor 1190 * tracks virtual-NMI blocking in the Guest Interruptibility-state field of 1191 * the VMCS. An IRET instruction in VMX non-root operation will remove any 1192 * virtual-NMI blocking. 1193 * 1194 * This unblocking occurs even if the IRET causes a fault. In this case the 1195 * hypervisor needs to restore virtual-NMI blocking before resuming the guest. 1196 */ 1197 static void 1198 vmx_restore_nmi_blocking(struct vmx *vmx, int vcpuid) 1199 { 1200 uint32_t gi; 1201 1202 VCPU_CTR0(vmx->vm, vcpuid, "Restore Virtual-NMI blocking"); 1203 gi = vmcs_read(VMCS_GUEST_INTERRUPTIBILITY); 1204 gi |= VMCS_INTERRUPTIBILITY_NMI_BLOCKING; 1205 vmcs_write(VMCS_GUEST_INTERRUPTIBILITY, gi); 1206 } 1207 1208 static void 1209 vmx_clear_nmi_blocking(struct vmx *vmx, int vcpuid) 1210 { 1211 uint32_t gi; 1212 1213 VCPU_CTR0(vmx->vm, vcpuid, "Clear Virtual-NMI blocking"); 1214 gi = vmcs_read(VMCS_GUEST_INTERRUPTIBILITY); 1215 gi &= ~VMCS_INTERRUPTIBILITY_NMI_BLOCKING; 1216 vmcs_write(VMCS_GUEST_INTERRUPTIBILITY, gi); 1217 } 1218 1219 static int 1220 vmx_emulate_cr_access(struct vmx *vmx, int vcpu, uint64_t exitqual) 1221 { 1222 int cr, vmcs_guest_cr, vmcs_shadow_cr; 1223 uint64_t crval, regval, ones_mask, zeros_mask; 1224 const struct vmxctx *vmxctx; 1225 1226 /* We only handle mov to %cr0 or %cr4 at this time */ 1227 if ((exitqual & 0xf0) != 0x00) 1228 return (UNHANDLED); 1229 1230 cr = exitqual & 0xf; 1231 if (cr != 0 && cr != 4) 1232 return (UNHANDLED); 1233 1234 regval = 0; /* silence gcc */ 1235 vmxctx = &vmx->ctx[vcpu]; 1236 1237 /* 1238 * We must use vmcs_write() directly here because vmcs_setreg() will 1239 * call vmclear(vmcs) as a side-effect which we certainly don't want. 1240 */ 1241 switch ((exitqual >> 8) & 0xf) { 1242 case 0: 1243 regval = vmxctx->guest_rax; 1244 break; 1245 case 1: 1246 regval = vmxctx->guest_rcx; 1247 break; 1248 case 2: 1249 regval = vmxctx->guest_rdx; 1250 break; 1251 case 3: 1252 regval = vmxctx->guest_rbx; 1253 break; 1254 case 4: 1255 regval = vmcs_read(VMCS_GUEST_RSP); 1256 break; 1257 case 5: 1258 regval = vmxctx->guest_rbp; 1259 break; 1260 case 6: 1261 regval = vmxctx->guest_rsi; 1262 break; 1263 case 7: 1264 regval = vmxctx->guest_rdi; 1265 break; 1266 case 8: 1267 regval = vmxctx->guest_r8; 1268 break; 1269 case 9: 1270 regval = vmxctx->guest_r9; 1271 break; 1272 case 10: 1273 regval = vmxctx->guest_r10; 1274 break; 1275 case 11: 1276 regval = vmxctx->guest_r11; 1277 break; 1278 case 12: 1279 regval = vmxctx->guest_r12; 1280 break; 1281 case 13: 1282 regval = vmxctx->guest_r13; 1283 break; 1284 case 14: 1285 regval = vmxctx->guest_r14; 1286 break; 1287 case 15: 1288 regval = vmxctx->guest_r15; 1289 break; 1290 } 1291 1292 if (cr == 0) { 1293 ones_mask = cr0_ones_mask; 1294 zeros_mask = cr0_zeros_mask; 1295 vmcs_guest_cr = VMCS_GUEST_CR0; 1296 vmcs_shadow_cr = VMCS_CR0_SHADOW; 1297 } else { 1298 ones_mask = cr4_ones_mask; 1299 zeros_mask = cr4_zeros_mask; 1300 vmcs_guest_cr = VMCS_GUEST_CR4; 1301 vmcs_shadow_cr = VMCS_CR4_SHADOW; 1302 } 1303 vmcs_write(vmcs_shadow_cr, regval); 1304 1305 crval = regval | ones_mask; 1306 crval &= ~zeros_mask; 1307 vmcs_write(vmcs_guest_cr, crval); 1308 1309 if (cr == 0 && regval & CR0_PG) { 1310 uint64_t efer, entry_ctls; 1311 1312 /* 1313 * If CR0.PG is 1 and EFER.LME is 1 then EFER.LMA and 1314 * the "IA-32e mode guest" bit in VM-entry control must be 1315 * equal. 1316 */ 1317 efer = vmcs_read(VMCS_GUEST_IA32_EFER); 1318 if (efer & EFER_LME) { 1319 efer |= EFER_LMA; 1320 vmcs_write(VMCS_GUEST_IA32_EFER, efer); 1321 entry_ctls = vmcs_read(VMCS_ENTRY_CTLS); 1322 entry_ctls |= VM_ENTRY_GUEST_LMA; 1323 vmcs_write(VMCS_ENTRY_CTLS, entry_ctls); 1324 } 1325 } 1326 1327 return (HANDLED); 1328 } 1329 1330 static int 1331 ept_fault_type(uint64_t ept_qual) 1332 { 1333 int fault_type; 1334 1335 if (ept_qual & EPT_VIOLATION_DATA_WRITE) 1336 fault_type = VM_PROT_WRITE; 1337 else if (ept_qual & EPT_VIOLATION_INST_FETCH) 1338 fault_type = VM_PROT_EXECUTE; 1339 else 1340 fault_type= VM_PROT_READ; 1341 1342 return (fault_type); 1343 } 1344 1345 static boolean_t 1346 ept_emulation_fault(uint64_t ept_qual) 1347 { 1348 int read, write; 1349 1350 /* EPT fault on an instruction fetch doesn't make sense here */ 1351 if (ept_qual & EPT_VIOLATION_INST_FETCH) 1352 return (FALSE); 1353 1354 /* EPT fault must be a read fault or a write fault */ 1355 read = ept_qual & EPT_VIOLATION_DATA_READ ? 1 : 0; 1356 write = ept_qual & EPT_VIOLATION_DATA_WRITE ? 1 : 0; 1357 if ((read | write) == 0) 1358 return (FALSE); 1359 1360 /* 1361 * The EPT violation must have been caused by accessing a 1362 * guest-physical address that is a translation of a guest-linear 1363 * address. 1364 */ 1365 if ((ept_qual & EPT_VIOLATION_GLA_VALID) == 0 || 1366 (ept_qual & EPT_VIOLATION_XLAT_VALID) == 0) { 1367 return (FALSE); 1368 } 1369 1370 return (TRUE); 1371 } 1372 1373 static int 1374 vmx_handle_apic_write(struct vlapic *vlapic, uint64_t qual) 1375 { 1376 int error, handled, offset; 1377 bool retu; 1378 1379 if (!virtual_interrupt_delivery) 1380 return (UNHANDLED); 1381 1382 handled = 1; 1383 offset = APIC_WRITE_OFFSET(qual); 1384 switch (offset) { 1385 case APIC_OFFSET_ID: 1386 vlapic_id_write_handler(vlapic); 1387 break; 1388 case APIC_OFFSET_LDR: 1389 vlapic_ldr_write_handler(vlapic); 1390 break; 1391 case APIC_OFFSET_DFR: 1392 vlapic_dfr_write_handler(vlapic); 1393 break; 1394 case APIC_OFFSET_SVR: 1395 vlapic_svr_write_handler(vlapic); 1396 break; 1397 case APIC_OFFSET_ESR: 1398 vlapic_esr_write_handler(vlapic); 1399 break; 1400 case APIC_OFFSET_ICR_LOW: 1401 retu = false; 1402 error = vlapic_icrlo_write_handler(vlapic, &retu); 1403 if (error != 0 || retu) 1404 handled = 0; 1405 break; 1406 case APIC_OFFSET_CMCI_LVT: 1407 case APIC_OFFSET_TIMER_LVT ... APIC_OFFSET_ERROR_LVT: 1408 vlapic_lvt_write_handler(vlapic, offset); 1409 break; 1410 case APIC_OFFSET_TIMER_ICR: 1411 vlapic_icrtmr_write_handler(vlapic); 1412 break; 1413 case APIC_OFFSET_TIMER_DCR: 1414 vlapic_dcr_write_handler(vlapic); 1415 break; 1416 default: 1417 handled = 0; 1418 break; 1419 } 1420 return (handled); 1421 } 1422 1423 static bool 1424 apic_access_fault(uint64_t gpa) 1425 { 1426 1427 if (virtual_interrupt_delivery && 1428 (gpa >= DEFAULT_APIC_BASE && gpa < DEFAULT_APIC_BASE + PAGE_SIZE)) 1429 return (true); 1430 else 1431 return (false); 1432 } 1433 1434 static int 1435 vmx_handle_apic_access(struct vmx *vmx, int vcpuid, struct vm_exit *vmexit) 1436 { 1437 uint64_t qual; 1438 int access_type, offset, allowed; 1439 1440 if (!virtual_interrupt_delivery) 1441 return (UNHANDLED); 1442 1443 qual = vmexit->u.vmx.exit_qualification; 1444 access_type = APIC_ACCESS_TYPE(qual); 1445 offset = APIC_ACCESS_OFFSET(qual); 1446 1447 allowed = 0; 1448 if (access_type == 0) { 1449 /* 1450 * Read data access to the following registers is expected. 1451 */ 1452 switch (offset) { 1453 case APIC_OFFSET_APR: 1454 case APIC_OFFSET_PPR: 1455 case APIC_OFFSET_RRR: 1456 case APIC_OFFSET_CMCI_LVT: 1457 case APIC_OFFSET_TIMER_CCR: 1458 allowed = 1; 1459 break; 1460 default: 1461 break; 1462 } 1463 } else if (access_type == 1) { 1464 /* 1465 * Write data access to the following registers is expected. 1466 */ 1467 switch (offset) { 1468 case APIC_OFFSET_VER: 1469 case APIC_OFFSET_APR: 1470 case APIC_OFFSET_PPR: 1471 case APIC_OFFSET_RRR: 1472 case APIC_OFFSET_ISR0 ... APIC_OFFSET_ISR7: 1473 case APIC_OFFSET_TMR0 ... APIC_OFFSET_TMR7: 1474 case APIC_OFFSET_IRR0 ... APIC_OFFSET_IRR7: 1475 case APIC_OFFSET_CMCI_LVT: 1476 case APIC_OFFSET_TIMER_CCR: 1477 allowed = 1; 1478 break; 1479 default: 1480 break; 1481 } 1482 } 1483 1484 if (allowed) { 1485 vmexit->exitcode = VM_EXITCODE_INST_EMUL; 1486 vmexit->u.inst_emul.gpa = DEFAULT_APIC_BASE + offset; 1487 vmexit->u.inst_emul.gla = VIE_INVALID_GLA; 1488 vmexit->u.inst_emul.cr3 = vmcs_guest_cr3(); 1489 } 1490 1491 /* 1492 * Regardless of whether the APIC-access is allowed this handler 1493 * always returns UNHANDLED: 1494 * - if the access is allowed then it is handled by emulating the 1495 * instruction that caused the VM-exit (outside the critical section) 1496 * - if the access is not allowed then it will be converted to an 1497 * exitcode of VM_EXITCODE_VMX and will be dealt with in userland. 1498 */ 1499 return (UNHANDLED); 1500 } 1501 1502 static int 1503 vmx_exit_process(struct vmx *vmx, int vcpu, struct vm_exit *vmexit) 1504 { 1505 int error, handled; 1506 struct vmxctx *vmxctx; 1507 struct vlapic *vlapic; 1508 uint32_t eax, ecx, edx, idtvec_info, idtvec_err, intr_info, reason; 1509 uint64_t qual, gpa; 1510 bool retu; 1511 1512 CTASSERT((PINBASED_CTLS_ONE_SETTING & PINBASED_VIRTUAL_NMI) != 0); 1513 CTASSERT((PINBASED_CTLS_ONE_SETTING & PINBASED_NMI_EXITING) != 0); 1514 1515 handled = 0; 1516 vmxctx = &vmx->ctx[vcpu]; 1517 1518 qual = vmexit->u.vmx.exit_qualification; 1519 reason = vmexit->u.vmx.exit_reason; 1520 vmexit->exitcode = VM_EXITCODE_BOGUS; 1521 1522 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_COUNT, 1); 1523 1524 /* 1525 * VM exits that could be triggered during event injection on the 1526 * previous VM entry need to be handled specially by re-injecting 1527 * the event. 1528 * 1529 * See "Information for VM Exits During Event Delivery" in Intel SDM 1530 * for details. 1531 */ 1532 switch (reason) { 1533 case EXIT_REASON_EPT_FAULT: 1534 case EXIT_REASON_EPT_MISCONFIG: 1535 case EXIT_REASON_APIC_ACCESS: 1536 case EXIT_REASON_TASK_SWITCH: 1537 case EXIT_REASON_EXCEPTION: 1538 idtvec_info = vmcs_idt_vectoring_info(); 1539 if (idtvec_info & VMCS_IDT_VEC_VALID) { 1540 idtvec_info &= ~(1 << 12); /* clear undefined bit */ 1541 vmcs_write(VMCS_ENTRY_INTR_INFO, idtvec_info); 1542 if (idtvec_info & VMCS_IDT_VEC_ERRCODE_VALID) { 1543 idtvec_err = vmcs_idt_vectoring_err(); 1544 vmcs_write(VMCS_ENTRY_EXCEPTION_ERROR, 1545 idtvec_err); 1546 } 1547 /* 1548 * If 'virtual NMIs' are being used and the VM-exit 1549 * happened while injecting an NMI during the previous 1550 * VM-entry, then clear "blocking by NMI" in the Guest 1551 * Interruptibility-state. 1552 */ 1553 if ((idtvec_info & VMCS_INTR_T_MASK) == 1554 VMCS_INTR_T_NMI) { 1555 vmx_clear_nmi_blocking(vmx, vcpu); 1556 } 1557 vmcs_write(VMCS_ENTRY_INST_LENGTH, vmexit->inst_length); 1558 } 1559 default: 1560 idtvec_info = 0; 1561 break; 1562 } 1563 1564 switch (reason) { 1565 case EXIT_REASON_CR_ACCESS: 1566 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_CR_ACCESS, 1); 1567 handled = vmx_emulate_cr_access(vmx, vcpu, qual); 1568 break; 1569 case EXIT_REASON_RDMSR: 1570 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_RDMSR, 1); 1571 retu = false; 1572 ecx = vmxctx->guest_rcx; 1573 error = emulate_rdmsr(vmx->vm, vcpu, ecx, &retu); 1574 if (error) { 1575 vmexit->exitcode = VM_EXITCODE_RDMSR; 1576 vmexit->u.msr.code = ecx; 1577 } else if (!retu) { 1578 handled = 1; 1579 } else { 1580 /* Return to userspace with a valid exitcode */ 1581 KASSERT(vmexit->exitcode != VM_EXITCODE_BOGUS, 1582 ("emulate_wrmsr retu with bogus exitcode")); 1583 } 1584 break; 1585 case EXIT_REASON_WRMSR: 1586 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_WRMSR, 1); 1587 retu = false; 1588 eax = vmxctx->guest_rax; 1589 ecx = vmxctx->guest_rcx; 1590 edx = vmxctx->guest_rdx; 1591 error = emulate_wrmsr(vmx->vm, vcpu, ecx, 1592 (uint64_t)edx << 32 | eax, &retu); 1593 if (error) { 1594 vmexit->exitcode = VM_EXITCODE_WRMSR; 1595 vmexit->u.msr.code = ecx; 1596 vmexit->u.msr.wval = (uint64_t)edx << 32 | eax; 1597 } else if (!retu) { 1598 handled = 1; 1599 } else { 1600 /* Return to userspace with a valid exitcode */ 1601 KASSERT(vmexit->exitcode != VM_EXITCODE_BOGUS, 1602 ("emulate_wrmsr retu with bogus exitcode")); 1603 } 1604 break; 1605 case EXIT_REASON_HLT: 1606 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_HLT, 1); 1607 vmexit->exitcode = VM_EXITCODE_HLT; 1608 vmexit->u.hlt.rflags = vmcs_read(VMCS_GUEST_RFLAGS); 1609 break; 1610 case EXIT_REASON_MTF: 1611 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_MTRAP, 1); 1612 vmexit->exitcode = VM_EXITCODE_MTRAP; 1613 break; 1614 case EXIT_REASON_PAUSE: 1615 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_PAUSE, 1); 1616 vmexit->exitcode = VM_EXITCODE_PAUSE; 1617 break; 1618 case EXIT_REASON_INTR_WINDOW: 1619 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_INTR_WINDOW, 1); 1620 vmx_clear_int_window_exiting(vmx, vcpu); 1621 return (1); 1622 case EXIT_REASON_EXT_INTR: 1623 /* 1624 * External interrupts serve only to cause VM exits and allow 1625 * the host interrupt handler to run. 1626 * 1627 * If this external interrupt triggers a virtual interrupt 1628 * to a VM, then that state will be recorded by the 1629 * host interrupt handler in the VM's softc. We will inject 1630 * this virtual interrupt during the subsequent VM enter. 1631 */ 1632 intr_info = vmcs_read(VMCS_EXIT_INTR_INFO); 1633 KASSERT((intr_info & VMCS_INTR_VALID) != 0 && 1634 (intr_info & VMCS_INTR_T_MASK) == VMCS_INTR_T_HWINTR, 1635 ("VM exit interruption info invalid: %#x", intr_info)); 1636 vmx_trigger_hostintr(intr_info & 0xff); 1637 1638 /* 1639 * This is special. We want to treat this as an 'handled' 1640 * VM-exit but not increment the instruction pointer. 1641 */ 1642 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_EXTINT, 1); 1643 return (1); 1644 case EXIT_REASON_NMI_WINDOW: 1645 /* Exit to allow the pending virtual NMI to be injected */ 1646 if (vm_nmi_pending(vmx->vm, vcpu)) 1647 vmx_inject_nmi(vmx, vcpu); 1648 vmx_clear_nmi_window_exiting(vmx, vcpu); 1649 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_NMI_WINDOW, 1); 1650 return (1); 1651 case EXIT_REASON_INOUT: 1652 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_INOUT, 1); 1653 vmexit->exitcode = VM_EXITCODE_INOUT; 1654 vmexit->u.inout.bytes = (qual & 0x7) + 1; 1655 vmexit->u.inout.in = (qual & 0x8) ? 1 : 0; 1656 vmexit->u.inout.string = (qual & 0x10) ? 1 : 0; 1657 vmexit->u.inout.rep = (qual & 0x20) ? 1 : 0; 1658 vmexit->u.inout.port = (uint16_t)(qual >> 16); 1659 vmexit->u.inout.eax = (uint32_t)(vmxctx->guest_rax); 1660 break; 1661 case EXIT_REASON_CPUID: 1662 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_CPUID, 1); 1663 handled = vmx_handle_cpuid(vmx->vm, vcpu, vmxctx); 1664 break; 1665 case EXIT_REASON_EXCEPTION: 1666 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_EXCEPTION, 1); 1667 intr_info = vmcs_read(VMCS_EXIT_INTR_INFO); 1668 KASSERT((intr_info & VMCS_INTR_VALID) != 0, 1669 ("VM exit interruption info invalid: %#x", intr_info)); 1670 1671 /* 1672 * If Virtual NMIs control is 1 and the VM-exit is due to a 1673 * fault encountered during the execution of IRET then we must 1674 * restore the state of "virtual-NMI blocking" before resuming 1675 * the guest. 1676 * 1677 * See "Resuming Guest Software after Handling an Exception". 1678 */ 1679 if ((idtvec_info & VMCS_IDT_VEC_VALID) == 0 && 1680 (intr_info & 0xff) != IDT_DF && 1681 (intr_info & EXIT_QUAL_NMIUDTI) != 0) 1682 vmx_restore_nmi_blocking(vmx, vcpu); 1683 1684 /* 1685 * If the NMI-exiting VM execution control is set to '1' 1686 * then an NMI in non-root operation causes a VM-exit. 1687 * NMI blocking is in effect for this logical processor so 1688 * it is sufficient to simply vector to the NMI handler via 1689 * a software interrupt. 1690 */ 1691 if ((intr_info & VMCS_INTR_T_MASK) == VMCS_INTR_T_NMI) { 1692 KASSERT((intr_info & 0xff) == IDT_NMI, ("VM exit due " 1693 "to NMI has invalid vector: %#x", intr_info)); 1694 VCPU_CTR0(vmx->vm, vcpu, "Vectoring to NMI handler"); 1695 __asm __volatile("int $2"); 1696 return (1); 1697 } 1698 break; 1699 case EXIT_REASON_EPT_FAULT: 1700 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_EPT_FAULT, 1); 1701 /* 1702 * If 'gpa' lies within the address space allocated to 1703 * memory then this must be a nested page fault otherwise 1704 * this must be an instruction that accesses MMIO space. 1705 */ 1706 gpa = vmcs_gpa(); 1707 if (vm_mem_allocated(vmx->vm, gpa) || apic_access_fault(gpa)) { 1708 vmexit->exitcode = VM_EXITCODE_PAGING; 1709 vmexit->u.paging.gpa = gpa; 1710 vmexit->u.paging.fault_type = ept_fault_type(qual); 1711 } else if (ept_emulation_fault(qual)) { 1712 vmexit->exitcode = VM_EXITCODE_INST_EMUL; 1713 vmexit->u.inst_emul.gpa = gpa; 1714 vmexit->u.inst_emul.gla = vmcs_gla(); 1715 vmexit->u.inst_emul.cr3 = vmcs_guest_cr3(); 1716 } 1717 /* 1718 * If Virtual NMIs control is 1 and the VM-exit is due to an 1719 * EPT fault during the execution of IRET then we must restore 1720 * the state of "virtual-NMI blocking" before resuming. 1721 * 1722 * See description of "NMI unblocking due to IRET" in 1723 * "Exit Qualification for EPT Violations". 1724 */ 1725 if ((idtvec_info & VMCS_IDT_VEC_VALID) == 0 && 1726 (qual & EXIT_QUAL_NMIUDTI) != 0) 1727 vmx_restore_nmi_blocking(vmx, vcpu); 1728 break; 1729 case EXIT_REASON_VIRTUALIZED_EOI: 1730 vmexit->exitcode = VM_EXITCODE_IOAPIC_EOI; 1731 vmexit->u.ioapic_eoi.vector = qual & 0xFF; 1732 vmexit->inst_length = 0; /* trap-like */ 1733 break; 1734 case EXIT_REASON_APIC_ACCESS: 1735 handled = vmx_handle_apic_access(vmx, vcpu, vmexit); 1736 break; 1737 case EXIT_REASON_APIC_WRITE: 1738 /* 1739 * APIC-write VM exit is trap-like so the %rip is already 1740 * pointing to the next instruction. 1741 */ 1742 vmexit->inst_length = 0; 1743 vlapic = vm_lapic(vmx->vm, vcpu); 1744 handled = vmx_handle_apic_write(vlapic, qual); 1745 break; 1746 default: 1747 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_UNKNOWN, 1); 1748 break; 1749 } 1750 1751 if (handled) { 1752 /* 1753 * It is possible that control is returned to userland 1754 * even though we were able to handle the VM exit in the 1755 * kernel. 1756 * 1757 * In such a case we want to make sure that the userland 1758 * restarts guest execution at the instruction *after* 1759 * the one we just processed. Therefore we update the 1760 * guest rip in the VMCS and in 'vmexit'. 1761 */ 1762 vmexit->rip += vmexit->inst_length; 1763 vmexit->inst_length = 0; 1764 vmcs_write(VMCS_GUEST_RIP, vmexit->rip); 1765 } else { 1766 if (vmexit->exitcode == VM_EXITCODE_BOGUS) { 1767 /* 1768 * If this VM exit was not claimed by anybody then 1769 * treat it as a generic VMX exit. 1770 */ 1771 vmexit->exitcode = VM_EXITCODE_VMX; 1772 vmexit->u.vmx.status = VM_SUCCESS; 1773 vmexit->u.vmx.inst_type = 0; 1774 vmexit->u.vmx.inst_error = 0; 1775 } else { 1776 /* 1777 * The exitcode and collateral have been populated. 1778 * The VM exit will be processed further in userland. 1779 */ 1780 } 1781 } 1782 return (handled); 1783 } 1784 1785 static __inline int 1786 vmx_exit_astpending(struct vmx *vmx, int vcpu, struct vm_exit *vmexit) 1787 { 1788 1789 vmexit->rip = vmcs_guest_rip(); 1790 vmexit->inst_length = 0; 1791 vmexit->exitcode = VM_EXITCODE_BOGUS; 1792 vmx_astpending_trace(vmx, vcpu, vmexit->rip); 1793 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_ASTPENDING, 1); 1794 1795 return (HANDLED); 1796 } 1797 1798 static __inline int 1799 vmx_exit_rendezvous(struct vmx *vmx, int vcpu, struct vm_exit *vmexit) 1800 { 1801 1802 vmexit->rip = vmcs_guest_rip(); 1803 vmexit->inst_length = 0; 1804 vmexit->exitcode = VM_EXITCODE_RENDEZVOUS; 1805 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_RENDEZVOUS, 1); 1806 1807 return (UNHANDLED); 1808 } 1809 1810 static __inline int 1811 vmx_exit_inst_error(struct vmxctx *vmxctx, int rc, struct vm_exit *vmexit) 1812 { 1813 1814 KASSERT(vmxctx->inst_fail_status != VM_SUCCESS, 1815 ("vmx_exit_inst_error: invalid inst_fail_status %d", 1816 vmxctx->inst_fail_status)); 1817 1818 vmexit->inst_length = 0; 1819 vmexit->exitcode = VM_EXITCODE_VMX; 1820 vmexit->u.vmx.status = vmxctx->inst_fail_status; 1821 vmexit->u.vmx.inst_error = vmcs_instruction_error(); 1822 vmexit->u.vmx.exit_reason = ~0; 1823 vmexit->u.vmx.exit_qualification = ~0; 1824 1825 switch (rc) { 1826 case VMX_VMRESUME_ERROR: 1827 case VMX_VMLAUNCH_ERROR: 1828 case VMX_INVEPT_ERROR: 1829 vmexit->u.vmx.inst_type = rc; 1830 break; 1831 default: 1832 panic("vm_exit_inst_error: vmx_enter_guest returned %d", rc); 1833 } 1834 1835 return (UNHANDLED); 1836 } 1837 1838 static int 1839 vmx_run(void *arg, int vcpu, register_t startrip, pmap_t pmap, 1840 void *rendezvous_cookie) 1841 { 1842 int rc, handled, launched; 1843 struct vmx *vmx; 1844 struct vm *vm; 1845 struct vmxctx *vmxctx; 1846 struct vmcs *vmcs; 1847 struct vm_exit *vmexit; 1848 struct vlapic *vlapic; 1849 uint64_t rip; 1850 uint32_t exit_reason; 1851 1852 vmx = arg; 1853 vm = vmx->vm; 1854 vmcs = &vmx->vmcs[vcpu]; 1855 vmxctx = &vmx->ctx[vcpu]; 1856 vlapic = vm_lapic(vm, vcpu); 1857 vmexit = vm_exitinfo(vm, vcpu); 1858 launched = 0; 1859 1860 KASSERT(vmxctx->pmap == pmap, 1861 ("pmap %p different than ctx pmap %p", pmap, vmxctx->pmap)); 1862 KASSERT(vmxctx->eptp == vmx->eptp, 1863 ("eptp %p different than ctx eptp %#lx", eptp, vmxctx->eptp)); 1864 1865 VMPTRLD(vmcs); 1866 1867 /* 1868 * XXX 1869 * We do this every time because we may setup the virtual machine 1870 * from a different process than the one that actually runs it. 1871 * 1872 * If the life of a virtual machine was spent entirely in the context 1873 * of a single process we could do this once in vmx_vminit(). 1874 */ 1875 vmcs_write(VMCS_HOST_CR3, rcr3()); 1876 1877 vmcs_write(VMCS_GUEST_RIP, startrip); 1878 vmx_set_pcpu_defaults(vmx, vcpu); 1879 do { 1880 /* 1881 * Interrupts are disabled from this point on until the 1882 * guest starts executing. This is done for the following 1883 * reasons: 1884 * 1885 * If an AST is asserted on this thread after the check below, 1886 * then the IPI_AST notification will not be lost, because it 1887 * will cause a VM exit due to external interrupt as soon as 1888 * the guest state is loaded. 1889 * 1890 * A posted interrupt after 'vmx_inject_interrupts()' will 1891 * not be "lost" because it will be held pending in the host 1892 * APIC because interrupts are disabled. The pending interrupt 1893 * will be recognized as soon as the guest state is loaded. 1894 * 1895 * The same reasoning applies to the IPI generated by 1896 * pmap_invalidate_ept(). 1897 */ 1898 disable_intr(); 1899 if (curthread->td_flags & (TDF_ASTPENDING | TDF_NEEDRESCHED)) { 1900 enable_intr(); 1901 handled = vmx_exit_astpending(vmx, vcpu, vmexit); 1902 break; 1903 } 1904 1905 if (vcpu_rendezvous_pending(rendezvous_cookie)) { 1906 enable_intr(); 1907 handled = vmx_exit_rendezvous(vmx, vcpu, vmexit); 1908 break; 1909 } 1910 1911 vmx_inject_interrupts(vmx, vcpu, vlapic); 1912 vmx_run_trace(vmx, vcpu); 1913 rc = vmx_enter_guest(vmxctx, launched); 1914 1915 enable_intr(); 1916 1917 /* Collect some information for VM exit processing */ 1918 vmexit->rip = rip = vmcs_guest_rip(); 1919 vmexit->inst_length = vmexit_instruction_length(); 1920 vmexit->u.vmx.exit_reason = exit_reason = vmcs_exit_reason(); 1921 vmexit->u.vmx.exit_qualification = vmcs_exit_qualification(); 1922 1923 if (rc == VMX_GUEST_VMEXIT) { 1924 launched = 1; 1925 handled = vmx_exit_process(vmx, vcpu, vmexit); 1926 } else { 1927 handled = vmx_exit_inst_error(vmxctx, rc, vmexit); 1928 } 1929 1930 vmx_exit_trace(vmx, vcpu, rip, exit_reason, handled); 1931 } while (handled); 1932 1933 /* 1934 * If a VM exit has been handled then the exitcode must be BOGUS 1935 * If a VM exit is not handled then the exitcode must not be BOGUS 1936 */ 1937 if ((handled && vmexit->exitcode != VM_EXITCODE_BOGUS) || 1938 (!handled && vmexit->exitcode == VM_EXITCODE_BOGUS)) { 1939 panic("Mismatch between handled (%d) and exitcode (%d)", 1940 handled, vmexit->exitcode); 1941 } 1942 1943 if (!handled) 1944 vmm_stat_incr(vm, vcpu, VMEXIT_USERSPACE, 1); 1945 1946 VCPU_CTR1(vm, vcpu, "returning from vmx_run: exitcode %d", 1947 vmexit->exitcode); 1948 1949 VMCLEAR(vmcs); 1950 return (0); 1951 } 1952 1953 static void 1954 vmx_vmcleanup(void *arg) 1955 { 1956 int i, error; 1957 struct vmx *vmx = arg; 1958 1959 if (virtual_interrupt_delivery) 1960 vm_unmap_mmio(vmx->vm, DEFAULT_APIC_BASE, PAGE_SIZE); 1961 1962 for (i = 0; i < VM_MAXCPU; i++) 1963 vpid_free(vmx->state[i].vpid); 1964 1965 /* 1966 * XXXSMP we also need to clear the VMCS active on the other vcpus. 1967 */ 1968 error = vmclear(&vmx->vmcs[0]); 1969 if (error != 0) 1970 panic("vmx_vmcleanup: vmclear error %d on vcpu 0", error); 1971 1972 free(vmx, M_VMX); 1973 1974 return; 1975 } 1976 1977 static register_t * 1978 vmxctx_regptr(struct vmxctx *vmxctx, int reg) 1979 { 1980 1981 switch (reg) { 1982 case VM_REG_GUEST_RAX: 1983 return (&vmxctx->guest_rax); 1984 case VM_REG_GUEST_RBX: 1985 return (&vmxctx->guest_rbx); 1986 case VM_REG_GUEST_RCX: 1987 return (&vmxctx->guest_rcx); 1988 case VM_REG_GUEST_RDX: 1989 return (&vmxctx->guest_rdx); 1990 case VM_REG_GUEST_RSI: 1991 return (&vmxctx->guest_rsi); 1992 case VM_REG_GUEST_RDI: 1993 return (&vmxctx->guest_rdi); 1994 case VM_REG_GUEST_RBP: 1995 return (&vmxctx->guest_rbp); 1996 case VM_REG_GUEST_R8: 1997 return (&vmxctx->guest_r8); 1998 case VM_REG_GUEST_R9: 1999 return (&vmxctx->guest_r9); 2000 case VM_REG_GUEST_R10: 2001 return (&vmxctx->guest_r10); 2002 case VM_REG_GUEST_R11: 2003 return (&vmxctx->guest_r11); 2004 case VM_REG_GUEST_R12: 2005 return (&vmxctx->guest_r12); 2006 case VM_REG_GUEST_R13: 2007 return (&vmxctx->guest_r13); 2008 case VM_REG_GUEST_R14: 2009 return (&vmxctx->guest_r14); 2010 case VM_REG_GUEST_R15: 2011 return (&vmxctx->guest_r15); 2012 default: 2013 break; 2014 } 2015 return (NULL); 2016 } 2017 2018 static int 2019 vmxctx_getreg(struct vmxctx *vmxctx, int reg, uint64_t *retval) 2020 { 2021 register_t *regp; 2022 2023 if ((regp = vmxctx_regptr(vmxctx, reg)) != NULL) { 2024 *retval = *regp; 2025 return (0); 2026 } else 2027 return (EINVAL); 2028 } 2029 2030 static int 2031 vmxctx_setreg(struct vmxctx *vmxctx, int reg, uint64_t val) 2032 { 2033 register_t *regp; 2034 2035 if ((regp = vmxctx_regptr(vmxctx, reg)) != NULL) { 2036 *regp = val; 2037 return (0); 2038 } else 2039 return (EINVAL); 2040 } 2041 2042 static int 2043 vmx_shadow_reg(int reg) 2044 { 2045 int shreg; 2046 2047 shreg = -1; 2048 2049 switch (reg) { 2050 case VM_REG_GUEST_CR0: 2051 shreg = VMCS_CR0_SHADOW; 2052 break; 2053 case VM_REG_GUEST_CR4: 2054 shreg = VMCS_CR4_SHADOW; 2055 break; 2056 default: 2057 break; 2058 } 2059 2060 return (shreg); 2061 } 2062 2063 static int 2064 vmx_getreg(void *arg, int vcpu, int reg, uint64_t *retval) 2065 { 2066 int running, hostcpu; 2067 struct vmx *vmx = arg; 2068 2069 running = vcpu_is_running(vmx->vm, vcpu, &hostcpu); 2070 if (running && hostcpu != curcpu) 2071 panic("vmx_getreg: %s%d is running", vm_name(vmx->vm), vcpu); 2072 2073 if (vmxctx_getreg(&vmx->ctx[vcpu], reg, retval) == 0) 2074 return (0); 2075 2076 return (vmcs_getreg(&vmx->vmcs[vcpu], running, reg, retval)); 2077 } 2078 2079 static int 2080 vmx_setreg(void *arg, int vcpu, int reg, uint64_t val) 2081 { 2082 int error, hostcpu, running, shadow; 2083 uint64_t ctls; 2084 struct vmx *vmx = arg; 2085 2086 running = vcpu_is_running(vmx->vm, vcpu, &hostcpu); 2087 if (running && hostcpu != curcpu) 2088 panic("vmx_setreg: %s%d is running", vm_name(vmx->vm), vcpu); 2089 2090 if (vmxctx_setreg(&vmx->ctx[vcpu], reg, val) == 0) 2091 return (0); 2092 2093 error = vmcs_setreg(&vmx->vmcs[vcpu], running, reg, val); 2094 2095 if (error == 0) { 2096 /* 2097 * If the "load EFER" VM-entry control is 1 then the 2098 * value of EFER.LMA must be identical to "IA-32e mode guest" 2099 * bit in the VM-entry control. 2100 */ 2101 if ((entry_ctls & VM_ENTRY_LOAD_EFER) != 0 && 2102 (reg == VM_REG_GUEST_EFER)) { 2103 vmcs_getreg(&vmx->vmcs[vcpu], running, 2104 VMCS_IDENT(VMCS_ENTRY_CTLS), &ctls); 2105 if (val & EFER_LMA) 2106 ctls |= VM_ENTRY_GUEST_LMA; 2107 else 2108 ctls &= ~VM_ENTRY_GUEST_LMA; 2109 vmcs_setreg(&vmx->vmcs[vcpu], running, 2110 VMCS_IDENT(VMCS_ENTRY_CTLS), ctls); 2111 } 2112 2113 shadow = vmx_shadow_reg(reg); 2114 if (shadow > 0) { 2115 /* 2116 * Store the unmodified value in the shadow 2117 */ 2118 error = vmcs_setreg(&vmx->vmcs[vcpu], running, 2119 VMCS_IDENT(shadow), val); 2120 } 2121 } 2122 2123 return (error); 2124 } 2125 2126 static int 2127 vmx_getdesc(void *arg, int vcpu, int reg, struct seg_desc *desc) 2128 { 2129 struct vmx *vmx = arg; 2130 2131 return (vmcs_getdesc(&vmx->vmcs[vcpu], reg, desc)); 2132 } 2133 2134 static int 2135 vmx_setdesc(void *arg, int vcpu, int reg, struct seg_desc *desc) 2136 { 2137 struct vmx *vmx = arg; 2138 2139 return (vmcs_setdesc(&vmx->vmcs[vcpu], reg, desc)); 2140 } 2141 2142 static int 2143 vmx_inject(void *arg, int vcpu, int type, int vector, uint32_t code, 2144 int code_valid) 2145 { 2146 int error; 2147 uint64_t info; 2148 struct vmx *vmx = arg; 2149 struct vmcs *vmcs = &vmx->vmcs[vcpu]; 2150 2151 static uint32_t type_map[VM_EVENT_MAX] = { 2152 0x1, /* VM_EVENT_NONE */ 2153 0x0, /* VM_HW_INTR */ 2154 0x2, /* VM_NMI */ 2155 0x3, /* VM_HW_EXCEPTION */ 2156 0x4, /* VM_SW_INTR */ 2157 0x5, /* VM_PRIV_SW_EXCEPTION */ 2158 0x6, /* VM_SW_EXCEPTION */ 2159 }; 2160 2161 /* 2162 * If there is already an exception pending to be delivered to the 2163 * vcpu then just return. 2164 */ 2165 error = vmcs_getreg(vmcs, 0, VMCS_IDENT(VMCS_ENTRY_INTR_INFO), &info); 2166 if (error) 2167 return (error); 2168 2169 if (info & VMCS_INTR_VALID) 2170 return (EAGAIN); 2171 2172 info = vector | (type_map[type] << 8) | (code_valid ? 1 << 11 : 0); 2173 info |= VMCS_INTR_VALID; 2174 error = vmcs_setreg(vmcs, 0, VMCS_IDENT(VMCS_ENTRY_INTR_INFO), info); 2175 if (error != 0) 2176 return (error); 2177 2178 if (code_valid) { 2179 error = vmcs_setreg(vmcs, 0, 2180 VMCS_IDENT(VMCS_ENTRY_EXCEPTION_ERROR), 2181 code); 2182 } 2183 return (error); 2184 } 2185 2186 static int 2187 vmx_getcap(void *arg, int vcpu, int type, int *retval) 2188 { 2189 struct vmx *vmx = arg; 2190 int vcap; 2191 int ret; 2192 2193 ret = ENOENT; 2194 2195 vcap = vmx->cap[vcpu].set; 2196 2197 switch (type) { 2198 case VM_CAP_HALT_EXIT: 2199 if (cap_halt_exit) 2200 ret = 0; 2201 break; 2202 case VM_CAP_PAUSE_EXIT: 2203 if (cap_pause_exit) 2204 ret = 0; 2205 break; 2206 case VM_CAP_MTRAP_EXIT: 2207 if (cap_monitor_trap) 2208 ret = 0; 2209 break; 2210 case VM_CAP_UNRESTRICTED_GUEST: 2211 if (cap_unrestricted_guest) 2212 ret = 0; 2213 break; 2214 case VM_CAP_ENABLE_INVPCID: 2215 if (cap_invpcid) 2216 ret = 0; 2217 break; 2218 default: 2219 break; 2220 } 2221 2222 if (ret == 0) 2223 *retval = (vcap & (1 << type)) ? 1 : 0; 2224 2225 return (ret); 2226 } 2227 2228 static int 2229 vmx_setcap(void *arg, int vcpu, int type, int val) 2230 { 2231 struct vmx *vmx = arg; 2232 struct vmcs *vmcs = &vmx->vmcs[vcpu]; 2233 uint32_t baseval; 2234 uint32_t *pptr; 2235 int error; 2236 int flag; 2237 int reg; 2238 int retval; 2239 2240 retval = ENOENT; 2241 pptr = NULL; 2242 2243 switch (type) { 2244 case VM_CAP_HALT_EXIT: 2245 if (cap_halt_exit) { 2246 retval = 0; 2247 pptr = &vmx->cap[vcpu].proc_ctls; 2248 baseval = *pptr; 2249 flag = PROCBASED_HLT_EXITING; 2250 reg = VMCS_PRI_PROC_BASED_CTLS; 2251 } 2252 break; 2253 case VM_CAP_MTRAP_EXIT: 2254 if (cap_monitor_trap) { 2255 retval = 0; 2256 pptr = &vmx->cap[vcpu].proc_ctls; 2257 baseval = *pptr; 2258 flag = PROCBASED_MTF; 2259 reg = VMCS_PRI_PROC_BASED_CTLS; 2260 } 2261 break; 2262 case VM_CAP_PAUSE_EXIT: 2263 if (cap_pause_exit) { 2264 retval = 0; 2265 pptr = &vmx->cap[vcpu].proc_ctls; 2266 baseval = *pptr; 2267 flag = PROCBASED_PAUSE_EXITING; 2268 reg = VMCS_PRI_PROC_BASED_CTLS; 2269 } 2270 break; 2271 case VM_CAP_UNRESTRICTED_GUEST: 2272 if (cap_unrestricted_guest) { 2273 retval = 0; 2274 pptr = &vmx->cap[vcpu].proc_ctls2; 2275 baseval = *pptr; 2276 flag = PROCBASED2_UNRESTRICTED_GUEST; 2277 reg = VMCS_SEC_PROC_BASED_CTLS; 2278 } 2279 break; 2280 case VM_CAP_ENABLE_INVPCID: 2281 if (cap_invpcid) { 2282 retval = 0; 2283 pptr = &vmx->cap[vcpu].proc_ctls2; 2284 baseval = *pptr; 2285 flag = PROCBASED2_ENABLE_INVPCID; 2286 reg = VMCS_SEC_PROC_BASED_CTLS; 2287 } 2288 break; 2289 default: 2290 break; 2291 } 2292 2293 if (retval == 0) { 2294 if (val) { 2295 baseval |= flag; 2296 } else { 2297 baseval &= ~flag; 2298 } 2299 VMPTRLD(vmcs); 2300 error = vmwrite(reg, baseval); 2301 VMCLEAR(vmcs); 2302 2303 if (error) { 2304 retval = error; 2305 } else { 2306 /* 2307 * Update optional stored flags, and record 2308 * setting 2309 */ 2310 if (pptr != NULL) { 2311 *pptr = baseval; 2312 } 2313 2314 if (val) { 2315 vmx->cap[vcpu].set |= (1 << type); 2316 } else { 2317 vmx->cap[vcpu].set &= ~(1 << type); 2318 } 2319 } 2320 } 2321 2322 return (retval); 2323 } 2324 2325 struct vlapic_vtx { 2326 struct vlapic vlapic; 2327 struct pir_desc *pir_desc; 2328 struct vmx *vmx; 2329 }; 2330 2331 #define VMX_CTR_PIR(vm, vcpuid, pir_desc, notify, vector, level, msg) \ 2332 do { \ 2333 VCPU_CTR2(vm, vcpuid, msg " assert %s-triggered vector %d", \ 2334 level ? "level" : "edge", vector); \ 2335 VCPU_CTR1(vm, vcpuid, msg " pir0 0x%016lx", pir_desc->pir[0]); \ 2336 VCPU_CTR1(vm, vcpuid, msg " pir1 0x%016lx", pir_desc->pir[1]); \ 2337 VCPU_CTR1(vm, vcpuid, msg " pir2 0x%016lx", pir_desc->pir[2]); \ 2338 VCPU_CTR1(vm, vcpuid, msg " pir3 0x%016lx", pir_desc->pir[3]); \ 2339 VCPU_CTR1(vm, vcpuid, msg " notify: %s", notify ? "yes" : "no");\ 2340 } while (0) 2341 2342 /* 2343 * vlapic->ops handlers that utilize the APICv hardware assist described in 2344 * Chapter 29 of the Intel SDM. 2345 */ 2346 static int 2347 vmx_set_intr_ready(struct vlapic *vlapic, int vector, bool level) 2348 { 2349 struct vlapic_vtx *vlapic_vtx; 2350 struct pir_desc *pir_desc; 2351 uint64_t mask; 2352 int idx, notify; 2353 2354 vlapic_vtx = (struct vlapic_vtx *)vlapic; 2355 pir_desc = vlapic_vtx->pir_desc; 2356 2357 /* 2358 * Keep track of interrupt requests in the PIR descriptor. This is 2359 * because the virtual APIC page pointed to by the VMCS cannot be 2360 * modified if the vcpu is running. 2361 */ 2362 idx = vector / 64; 2363 mask = 1UL << (vector % 64); 2364 atomic_set_long(&pir_desc->pir[idx], mask); 2365 notify = atomic_cmpset_long(&pir_desc->pending, 0, 1); 2366 2367 VMX_CTR_PIR(vlapic->vm, vlapic->vcpuid, pir_desc, notify, vector, 2368 level, "vmx_set_intr_ready"); 2369 return (notify); 2370 } 2371 2372 static int 2373 vmx_pending_intr(struct vlapic *vlapic, int *vecptr) 2374 { 2375 struct vlapic_vtx *vlapic_vtx; 2376 struct pir_desc *pir_desc; 2377 struct LAPIC *lapic; 2378 uint64_t pending, pirval; 2379 uint32_t ppr, vpr; 2380 int i; 2381 2382 /* 2383 * This function is only expected to be called from the 'HLT' exit 2384 * handler which does not care about the vector that is pending. 2385 */ 2386 KASSERT(vecptr == NULL, ("vmx_pending_intr: vecptr must be NULL")); 2387 2388 vlapic_vtx = (struct vlapic_vtx *)vlapic; 2389 pir_desc = vlapic_vtx->pir_desc; 2390 2391 pending = atomic_load_acq_long(&pir_desc->pending); 2392 if (!pending) 2393 return (0); /* common case */ 2394 2395 /* 2396 * If there is an interrupt pending then it will be recognized only 2397 * if its priority is greater than the processor priority. 2398 * 2399 * Special case: if the processor priority is zero then any pending 2400 * interrupt will be recognized. 2401 */ 2402 lapic = vlapic->apic_page; 2403 ppr = lapic->ppr & 0xf0; 2404 if (ppr == 0) 2405 return (1); 2406 2407 VCPU_CTR1(vlapic->vm, vlapic->vcpuid, "HLT with non-zero PPR %d", 2408 lapic->ppr); 2409 2410 for (i = 3; i >= 0; i--) { 2411 pirval = pir_desc->pir[i]; 2412 if (pirval != 0) { 2413 vpr = (i * 64 + flsl(pirval) - 1) & 0xf0; 2414 return (vpr > ppr); 2415 } 2416 } 2417 return (0); 2418 } 2419 2420 static void 2421 vmx_intr_accepted(struct vlapic *vlapic, int vector) 2422 { 2423 2424 panic("vmx_intr_accepted: not expected to be called"); 2425 } 2426 2427 static void 2428 vmx_set_tmr(struct vlapic *vlapic, int vector, bool level) 2429 { 2430 struct vlapic_vtx *vlapic_vtx; 2431 struct vmx *vmx; 2432 struct vmcs *vmcs; 2433 uint64_t mask, val; 2434 2435 KASSERT(vector >= 0 && vector <= 255, ("invalid vector %d", vector)); 2436 KASSERT(!vcpu_is_running(vlapic->vm, vlapic->vcpuid, NULL), 2437 ("vmx_set_tmr: vcpu cannot be running")); 2438 2439 vlapic_vtx = (struct vlapic_vtx *)vlapic; 2440 vmx = vlapic_vtx->vmx; 2441 vmcs = &vmx->vmcs[vlapic->vcpuid]; 2442 mask = 1UL << (vector % 64); 2443 2444 VMPTRLD(vmcs); 2445 val = vmcs_read(VMCS_EOI_EXIT(vector)); 2446 if (level) 2447 val |= mask; 2448 else 2449 val &= ~mask; 2450 vmcs_write(VMCS_EOI_EXIT(vector), val); 2451 VMCLEAR(vmcs); 2452 } 2453 2454 static void 2455 vmx_post_intr(struct vlapic *vlapic, int hostcpu) 2456 { 2457 2458 ipi_cpu(hostcpu, pirvec); 2459 } 2460 2461 /* 2462 * Transfer the pending interrupts in the PIR descriptor to the IRR 2463 * in the virtual APIC page. 2464 */ 2465 static void 2466 vmx_inject_pir(struct vlapic *vlapic) 2467 { 2468 struct vlapic_vtx *vlapic_vtx; 2469 struct pir_desc *pir_desc; 2470 struct LAPIC *lapic; 2471 uint64_t val, pirval; 2472 int rvi, pirbase; 2473 uint16_t intr_status_old, intr_status_new; 2474 2475 vlapic_vtx = (struct vlapic_vtx *)vlapic; 2476 pir_desc = vlapic_vtx->pir_desc; 2477 if (atomic_cmpset_long(&pir_desc->pending, 1, 0) == 0) { 2478 VCPU_CTR0(vlapic->vm, vlapic->vcpuid, "vmx_inject_pir: " 2479 "no posted interrupt pending"); 2480 return; 2481 } 2482 2483 pirval = 0; 2484 lapic = vlapic->apic_page; 2485 2486 val = atomic_readandclear_long(&pir_desc->pir[0]); 2487 if (val != 0) { 2488 lapic->irr0 |= val; 2489 lapic->irr1 |= val >> 32; 2490 pirbase = 0; 2491 pirval = val; 2492 } 2493 2494 val = atomic_readandclear_long(&pir_desc->pir[1]); 2495 if (val != 0) { 2496 lapic->irr2 |= val; 2497 lapic->irr3 |= val >> 32; 2498 pirbase = 64; 2499 pirval = val; 2500 } 2501 2502 val = atomic_readandclear_long(&pir_desc->pir[2]); 2503 if (val != 0) { 2504 lapic->irr4 |= val; 2505 lapic->irr5 |= val >> 32; 2506 pirbase = 128; 2507 pirval = val; 2508 } 2509 2510 val = atomic_readandclear_long(&pir_desc->pir[3]); 2511 if (val != 0) { 2512 lapic->irr6 |= val; 2513 lapic->irr7 |= val >> 32; 2514 pirbase = 192; 2515 pirval = val; 2516 } 2517 VLAPIC_CTR_IRR(vlapic, "vmx_inject_pir"); 2518 2519 /* 2520 * Update RVI so the processor can evaluate pending virtual 2521 * interrupts on VM-entry. 2522 */ 2523 if (pirval != 0) { 2524 rvi = pirbase + flsl(pirval) - 1; 2525 intr_status_old = vmcs_read(VMCS_GUEST_INTR_STATUS); 2526 intr_status_new = (intr_status_old & 0xFF00) | rvi; 2527 if (intr_status_new > intr_status_old) { 2528 vmcs_write(VMCS_GUEST_INTR_STATUS, intr_status_new); 2529 VCPU_CTR2(vlapic->vm, vlapic->vcpuid, "vmx_inject_pir: " 2530 "guest_intr_status changed from 0x%04x to 0x%04x", 2531 intr_status_old, intr_status_new); 2532 } 2533 } 2534 } 2535 2536 static struct vlapic * 2537 vmx_vlapic_init(void *arg, int vcpuid) 2538 { 2539 struct vmx *vmx; 2540 struct vlapic *vlapic; 2541 struct vlapic_vtx *vlapic_vtx; 2542 2543 vmx = arg; 2544 2545 vlapic = malloc(sizeof(struct vlapic_vtx), M_VLAPIC, M_WAITOK | M_ZERO); 2546 vlapic->vm = vmx->vm; 2547 vlapic->vcpuid = vcpuid; 2548 vlapic->apic_page = (struct LAPIC *)&vmx->apic_page[vcpuid]; 2549 2550 vlapic_vtx = (struct vlapic_vtx *)vlapic; 2551 vlapic_vtx->pir_desc = &vmx->pir_desc[vcpuid]; 2552 vlapic_vtx->vmx = vmx; 2553 2554 if (virtual_interrupt_delivery) { 2555 vlapic->ops.set_intr_ready = vmx_set_intr_ready; 2556 vlapic->ops.pending_intr = vmx_pending_intr; 2557 vlapic->ops.intr_accepted = vmx_intr_accepted; 2558 vlapic->ops.set_tmr = vmx_set_tmr; 2559 } 2560 2561 if (posted_interrupts) 2562 vlapic->ops.post_intr = vmx_post_intr; 2563 2564 vlapic_init(vlapic); 2565 2566 return (vlapic); 2567 } 2568 2569 static void 2570 vmx_vlapic_cleanup(void *arg, struct vlapic *vlapic) 2571 { 2572 2573 vlapic_cleanup(vlapic); 2574 free(vlapic, M_VLAPIC); 2575 } 2576 2577 struct vmm_ops vmm_ops_intel = { 2578 vmx_init, 2579 vmx_cleanup, 2580 vmx_restore, 2581 vmx_vminit, 2582 vmx_run, 2583 vmx_vmcleanup, 2584 vmx_getreg, 2585 vmx_setreg, 2586 vmx_getdesc, 2587 vmx_setdesc, 2588 vmx_inject, 2589 vmx_getcap, 2590 vmx_setcap, 2591 ept_vmspace_alloc, 2592 ept_vmspace_free, 2593 vmx_vlapic_init, 2594 vmx_vlapic_cleanup, 2595 }; 2596