1 /*- 2 * Copyright (c) 2011 NetApp, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #include "opt_ddb.h" 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/pcpu.h> 37 38 #include <vm/vm.h> 39 #include <vm/pmap.h> 40 41 #include <machine/segments.h> 42 #include <machine/vmm.h> 43 #include "vmm_host.h" 44 #include "vmx_cpufunc.h" 45 #include "vmcs.h" 46 #include "ept.h" 47 #include "vmx.h" 48 49 #ifdef DDB 50 #include <ddb/ddb.h> 51 #endif 52 53 static uint64_t 54 vmcs_fix_regval(uint32_t encoding, uint64_t val) 55 { 56 57 switch (encoding) { 58 case VMCS_GUEST_CR0: 59 val = vmx_fix_cr0(val); 60 break; 61 case VMCS_GUEST_CR4: 62 val = vmx_fix_cr4(val); 63 break; 64 default: 65 break; 66 } 67 return (val); 68 } 69 70 static uint32_t 71 vmcs_field_encoding(int ident) 72 { 73 switch (ident) { 74 case VM_REG_GUEST_CR0: 75 return (VMCS_GUEST_CR0); 76 case VM_REG_GUEST_CR3: 77 return (VMCS_GUEST_CR3); 78 case VM_REG_GUEST_CR4: 79 return (VMCS_GUEST_CR4); 80 case VM_REG_GUEST_DR7: 81 return (VMCS_GUEST_DR7); 82 case VM_REG_GUEST_RSP: 83 return (VMCS_GUEST_RSP); 84 case VM_REG_GUEST_RIP: 85 return (VMCS_GUEST_RIP); 86 case VM_REG_GUEST_RFLAGS: 87 return (VMCS_GUEST_RFLAGS); 88 case VM_REG_GUEST_ES: 89 return (VMCS_GUEST_ES_SELECTOR); 90 case VM_REG_GUEST_CS: 91 return (VMCS_GUEST_CS_SELECTOR); 92 case VM_REG_GUEST_SS: 93 return (VMCS_GUEST_SS_SELECTOR); 94 case VM_REG_GUEST_DS: 95 return (VMCS_GUEST_DS_SELECTOR); 96 case VM_REG_GUEST_FS: 97 return (VMCS_GUEST_FS_SELECTOR); 98 case VM_REG_GUEST_GS: 99 return (VMCS_GUEST_GS_SELECTOR); 100 case VM_REG_GUEST_TR: 101 return (VMCS_GUEST_TR_SELECTOR); 102 case VM_REG_GUEST_LDTR: 103 return (VMCS_GUEST_LDTR_SELECTOR); 104 case VM_REG_GUEST_EFER: 105 return (VMCS_GUEST_IA32_EFER); 106 default: 107 return (-1); 108 } 109 110 } 111 112 static int 113 vmcs_seg_desc_encoding(int seg, uint32_t *base, uint32_t *lim, uint32_t *acc) 114 { 115 116 switch (seg) { 117 case VM_REG_GUEST_ES: 118 *base = VMCS_GUEST_ES_BASE; 119 *lim = VMCS_GUEST_ES_LIMIT; 120 *acc = VMCS_GUEST_ES_ACCESS_RIGHTS; 121 break; 122 case VM_REG_GUEST_CS: 123 *base = VMCS_GUEST_CS_BASE; 124 *lim = VMCS_GUEST_CS_LIMIT; 125 *acc = VMCS_GUEST_CS_ACCESS_RIGHTS; 126 break; 127 case VM_REG_GUEST_SS: 128 *base = VMCS_GUEST_SS_BASE; 129 *lim = VMCS_GUEST_SS_LIMIT; 130 *acc = VMCS_GUEST_SS_ACCESS_RIGHTS; 131 break; 132 case VM_REG_GUEST_DS: 133 *base = VMCS_GUEST_DS_BASE; 134 *lim = VMCS_GUEST_DS_LIMIT; 135 *acc = VMCS_GUEST_DS_ACCESS_RIGHTS; 136 break; 137 case VM_REG_GUEST_FS: 138 *base = VMCS_GUEST_FS_BASE; 139 *lim = VMCS_GUEST_FS_LIMIT; 140 *acc = VMCS_GUEST_FS_ACCESS_RIGHTS; 141 break; 142 case VM_REG_GUEST_GS: 143 *base = VMCS_GUEST_GS_BASE; 144 *lim = VMCS_GUEST_GS_LIMIT; 145 *acc = VMCS_GUEST_GS_ACCESS_RIGHTS; 146 break; 147 case VM_REG_GUEST_TR: 148 *base = VMCS_GUEST_TR_BASE; 149 *lim = VMCS_GUEST_TR_LIMIT; 150 *acc = VMCS_GUEST_TR_ACCESS_RIGHTS; 151 break; 152 case VM_REG_GUEST_LDTR: 153 *base = VMCS_GUEST_LDTR_BASE; 154 *lim = VMCS_GUEST_LDTR_LIMIT; 155 *acc = VMCS_GUEST_LDTR_ACCESS_RIGHTS; 156 break; 157 case VM_REG_GUEST_IDTR: 158 *base = VMCS_GUEST_IDTR_BASE; 159 *lim = VMCS_GUEST_IDTR_LIMIT; 160 *acc = VMCS_INVALID_ENCODING; 161 break; 162 case VM_REG_GUEST_GDTR: 163 *base = VMCS_GUEST_GDTR_BASE; 164 *lim = VMCS_GUEST_GDTR_LIMIT; 165 *acc = VMCS_INVALID_ENCODING; 166 break; 167 default: 168 return (EINVAL); 169 } 170 171 return (0); 172 } 173 174 int 175 vmcs_getreg(struct vmcs *vmcs, int running, int ident, uint64_t *retval) 176 { 177 int error; 178 uint32_t encoding; 179 180 /* 181 * If we need to get at vmx-specific state in the VMCS we can bypass 182 * the translation of 'ident' to 'encoding' by simply setting the 183 * sign bit. As it so happens the upper 16 bits are reserved (i.e 184 * set to 0) in the encodings for the VMCS so we are free to use the 185 * sign bit. 186 */ 187 if (ident < 0) 188 encoding = ident & 0x7fffffff; 189 else 190 encoding = vmcs_field_encoding(ident); 191 192 if (encoding == (uint32_t)-1) 193 return (EINVAL); 194 195 if (!running) 196 VMPTRLD(vmcs); 197 198 error = vmread(encoding, retval); 199 200 if (!running) 201 VMCLEAR(vmcs); 202 203 return (error); 204 } 205 206 int 207 vmcs_setreg(struct vmcs *vmcs, int running, int ident, uint64_t val) 208 { 209 int error; 210 uint32_t encoding; 211 212 if (ident < 0) 213 encoding = ident & 0x7fffffff; 214 else 215 encoding = vmcs_field_encoding(ident); 216 217 if (encoding == (uint32_t)-1) 218 return (EINVAL); 219 220 val = vmcs_fix_regval(encoding, val); 221 222 if (!running) 223 VMPTRLD(vmcs); 224 225 error = vmwrite(encoding, val); 226 227 if (!running) 228 VMCLEAR(vmcs); 229 230 return (error); 231 } 232 233 int 234 vmcs_setdesc(struct vmcs *vmcs, int seg, struct seg_desc *desc) 235 { 236 int error; 237 uint32_t base, limit, access; 238 239 error = vmcs_seg_desc_encoding(seg, &base, &limit, &access); 240 if (error != 0) 241 panic("vmcs_setdesc: invalid segment register %d", seg); 242 243 VMPTRLD(vmcs); 244 if ((error = vmwrite(base, desc->base)) != 0) 245 goto done; 246 247 if ((error = vmwrite(limit, desc->limit)) != 0) 248 goto done; 249 250 if (access != VMCS_INVALID_ENCODING) { 251 if ((error = vmwrite(access, desc->access)) != 0) 252 goto done; 253 } 254 done: 255 VMCLEAR(vmcs); 256 return (error); 257 } 258 259 int 260 vmcs_getdesc(struct vmcs *vmcs, int seg, struct seg_desc *desc) 261 { 262 int error; 263 uint32_t base, limit, access; 264 uint64_t u64; 265 266 error = vmcs_seg_desc_encoding(seg, &base, &limit, &access); 267 if (error != 0) 268 panic("vmcs_getdesc: invalid segment register %d", seg); 269 270 VMPTRLD(vmcs); 271 if ((error = vmread(base, &u64)) != 0) 272 goto done; 273 desc->base = u64; 274 275 if ((error = vmread(limit, &u64)) != 0) 276 goto done; 277 desc->limit = u64; 278 279 if (access != VMCS_INVALID_ENCODING) { 280 if ((error = vmread(access, &u64)) != 0) 281 goto done; 282 desc->access = u64; 283 } 284 done: 285 VMCLEAR(vmcs); 286 return (error); 287 } 288 289 int 290 vmcs_set_msr_save(struct vmcs *vmcs, u_long g_area, u_int g_count) 291 { 292 int error; 293 294 VMPTRLD(vmcs); 295 296 /* 297 * Guest MSRs are saved in the VM-exit MSR-store area. 298 * Guest MSRs are loaded from the VM-entry MSR-load area. 299 * Both areas point to the same location in memory. 300 */ 301 if ((error = vmwrite(VMCS_EXIT_MSR_STORE, g_area)) != 0) 302 goto done; 303 if ((error = vmwrite(VMCS_EXIT_MSR_STORE_COUNT, g_count)) != 0) 304 goto done; 305 306 if ((error = vmwrite(VMCS_ENTRY_MSR_LOAD, g_area)) != 0) 307 goto done; 308 if ((error = vmwrite(VMCS_ENTRY_MSR_LOAD_COUNT, g_count)) != 0) 309 goto done; 310 311 error = 0; 312 done: 313 VMCLEAR(vmcs); 314 return (error); 315 } 316 317 int 318 vmcs_init(struct vmcs *vmcs) 319 { 320 int error, codesel, datasel, tsssel; 321 u_long cr0, cr4, efer; 322 uint64_t pat, fsbase, idtrbase; 323 uint32_t exc_bitmap; 324 325 codesel = vmm_get_host_codesel(); 326 datasel = vmm_get_host_datasel(); 327 tsssel = vmm_get_host_tsssel(); 328 329 /* 330 * Make sure we have a "current" VMCS to work with. 331 */ 332 VMPTRLD(vmcs); 333 334 /* Initialize guest IA32_PAT MSR with the default value */ 335 pat = PAT_VALUE(0, PAT_WRITE_BACK) | 336 PAT_VALUE(1, PAT_WRITE_THROUGH) | 337 PAT_VALUE(2, PAT_UNCACHED) | 338 PAT_VALUE(3, PAT_UNCACHEABLE) | 339 PAT_VALUE(4, PAT_WRITE_BACK) | 340 PAT_VALUE(5, PAT_WRITE_THROUGH) | 341 PAT_VALUE(6, PAT_UNCACHED) | 342 PAT_VALUE(7, PAT_UNCACHEABLE); 343 if ((error = vmwrite(VMCS_GUEST_IA32_PAT, pat)) != 0) 344 goto done; 345 346 /* Host state */ 347 348 /* Initialize host IA32_PAT MSR */ 349 pat = vmm_get_host_pat(); 350 if ((error = vmwrite(VMCS_HOST_IA32_PAT, pat)) != 0) 351 goto done; 352 353 /* Load the IA32_EFER MSR */ 354 efer = vmm_get_host_efer(); 355 if ((error = vmwrite(VMCS_HOST_IA32_EFER, efer)) != 0) 356 goto done; 357 358 /* Load the control registers */ 359 360 cr0 = vmm_get_host_cr0(); 361 if ((error = vmwrite(VMCS_HOST_CR0, cr0)) != 0) 362 goto done; 363 364 cr4 = vmm_get_host_cr4() | CR4_VMXE; 365 if ((error = vmwrite(VMCS_HOST_CR4, cr4)) != 0) 366 goto done; 367 368 /* Load the segment selectors */ 369 if ((error = vmwrite(VMCS_HOST_ES_SELECTOR, datasel)) != 0) 370 goto done; 371 372 if ((error = vmwrite(VMCS_HOST_CS_SELECTOR, codesel)) != 0) 373 goto done; 374 375 if ((error = vmwrite(VMCS_HOST_SS_SELECTOR, datasel)) != 0) 376 goto done; 377 378 if ((error = vmwrite(VMCS_HOST_DS_SELECTOR, datasel)) != 0) 379 goto done; 380 381 if ((error = vmwrite(VMCS_HOST_FS_SELECTOR, datasel)) != 0) 382 goto done; 383 384 if ((error = vmwrite(VMCS_HOST_GS_SELECTOR, datasel)) != 0) 385 goto done; 386 387 if ((error = vmwrite(VMCS_HOST_TR_SELECTOR, tsssel)) != 0) 388 goto done; 389 390 /* 391 * Load the Base-Address for %fs and idtr. 392 * 393 * Note that we exclude %gs, tss and gdtr here because their base 394 * address is pcpu specific. 395 */ 396 fsbase = vmm_get_host_fsbase(); 397 if ((error = vmwrite(VMCS_HOST_FS_BASE, fsbase)) != 0) 398 goto done; 399 400 idtrbase = vmm_get_host_idtrbase(); 401 if ((error = vmwrite(VMCS_HOST_IDTR_BASE, idtrbase)) != 0) 402 goto done; 403 404 /* instruction pointer */ 405 if ((error = vmwrite(VMCS_HOST_RIP, (u_long)vmx_exit_guest)) != 0) 406 goto done; 407 408 /* exception bitmap */ 409 exc_bitmap = 1 << IDT_MC; 410 if ((error = vmwrite(VMCS_EXCEPTION_BITMAP, exc_bitmap)) != 0) 411 goto done; 412 413 /* link pointer */ 414 if ((error = vmwrite(VMCS_LINK_POINTER, ~0)) != 0) 415 goto done; 416 done: 417 VMCLEAR(vmcs); 418 return (error); 419 } 420 421 #ifdef DDB 422 extern int vmxon_enabled[]; 423 424 DB_SHOW_COMMAND(vmcs, db_show_vmcs) 425 { 426 uint64_t cur_vmcs, val; 427 uint32_t exit; 428 429 if (!vmxon_enabled[curcpu]) { 430 db_printf("VMX not enabled\n"); 431 return; 432 } 433 434 if (have_addr) { 435 db_printf("Only current VMCS supported\n"); 436 return; 437 } 438 439 vmptrst(&cur_vmcs); 440 if (cur_vmcs == VMCS_INITIAL) { 441 db_printf("No current VM context\n"); 442 return; 443 } 444 db_printf("VMCS: %jx\n", cur_vmcs); 445 db_printf("VPID: %lu\n", vmcs_read(VMCS_VPID)); 446 db_printf("Activity: "); 447 val = vmcs_read(VMCS_GUEST_ACTIVITY); 448 switch (val) { 449 case 0: 450 db_printf("Active"); 451 break; 452 case 1: 453 db_printf("HLT"); 454 break; 455 case 2: 456 db_printf("Shutdown"); 457 break; 458 case 3: 459 db_printf("Wait for SIPI"); 460 break; 461 default: 462 db_printf("Unknown: %#lx", val); 463 } 464 db_printf("\n"); 465 exit = vmcs_read(VMCS_EXIT_REASON); 466 if (exit & 0x80000000) 467 db_printf("Entry Failure Reason: %u\n", exit & 0xffff); 468 else 469 db_printf("Exit Reason: %u\n", exit & 0xffff); 470 db_printf("Qualification: %#lx\n", vmcs_exit_qualification()); 471 db_printf("Guest Linear Address: %#lx\n", 472 vmcs_read(VMCS_GUEST_LINEAR_ADDRESS)); 473 switch (exit & 0x8000ffff) { 474 case EXIT_REASON_EXCEPTION: 475 case EXIT_REASON_EXT_INTR: 476 val = vmcs_read(VMCS_EXIT_INTR_INFO); 477 db_printf("Interrupt Type: "); 478 switch (val >> 8 & 0x7) { 479 case 0: 480 db_printf("external"); 481 break; 482 case 2: 483 db_printf("NMI"); 484 break; 485 case 3: 486 db_printf("HW exception"); 487 break; 488 case 4: 489 db_printf("SW exception"); 490 break; 491 default: 492 db_printf("?? %lu", val >> 8 & 0x7); 493 break; 494 } 495 db_printf(" Vector: %lu", val & 0xff); 496 if (val & 0x800) 497 db_printf(" Error Code: %lx", 498 vmcs_read(VMCS_EXIT_INTR_ERRCODE)); 499 db_printf("\n"); 500 break; 501 case EXIT_REASON_EPT_FAULT: 502 case EXIT_REASON_EPT_MISCONFIG: 503 db_printf("Guest Physical Address: %#lx\n", 504 vmcs_read(VMCS_GUEST_PHYSICAL_ADDRESS)); 505 break; 506 } 507 db_printf("VM-instruction error: %#lx\n", vmcs_instruction_error()); 508 } 509 #endif 510